1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/dts-v1/; 7*4882a593Smuzhiyun#include <dt-bindings/display/drm_mipi_dsi.h> 8*4882a593Smuzhiyun#include "rk1808-evb.dtsi" 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun/ { 11*4882a593Smuzhiyun model = "Rockchip RK1808 EVB X4 Board"; 12*4882a593Smuzhiyun compatible = "rockchip,rk1808-evb-x4", "rockchip,rk1808"; 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun chosen { 15*4882a593Smuzhiyun bootargs = "earlycon=uart8250,mmio32,0xff550000 console=ttyFIQ0 dump_initrd init=/init kpti=0"; 16*4882a593Smuzhiyun }; 17*4882a593Smuzhiyun}; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun&adc_key { 20*4882a593Smuzhiyun power-key { 21*4882a593Smuzhiyun linux,code = <KEY_POWER>; 22*4882a593Smuzhiyun label = "power key"; 23*4882a593Smuzhiyun press-threshold-microvolt = <18000>; 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun}; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun/delete-node/ &backlight; 28*4882a593Smuzhiyun/delete-node/ &vcc1v8_dvp; 29*4882a593Smuzhiyun/delete-node/ &vdd1v5_dvp; 30*4882a593Smuzhiyun/delete-node/ &vcc2v8_dvp; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun&cif { 33*4882a593Smuzhiyun status = "okay"; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun port { 36*4882a593Smuzhiyun cif_in: endpoint@0 { 37*4882a593Smuzhiyun remote-endpoint = <&dphy_rx_out>; 38*4882a593Smuzhiyun data-lanes = <1 2 3 4>; 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun}; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun&cif_mmu { 44*4882a593Smuzhiyun status = "okay"; 45*4882a593Smuzhiyun}; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun&cru { 48*4882a593Smuzhiyun assigned-clocks = 49*4882a593Smuzhiyun <&cru PLL_GPLL>, <&cru PLL_CPLL>, 50*4882a593Smuzhiyun <&cru PLL_PPLL>, <&cru ARMCLK>, 51*4882a593Smuzhiyun <&cru MSCLK_PERI>, <&cru LSCLK_PERI>, 52*4882a593Smuzhiyun <&cru HSCLK_BUS_PRE>, <&cru MSCLK_BUS_PRE>, 53*4882a593Smuzhiyun <&cru LSCLK_BUS_PRE>, <&cru DCLK_VOPRAW>; 54*4882a593Smuzhiyun assigned-clock-rates = 55*4882a593Smuzhiyun <1188000000>, <1000000000>, 56*4882a593Smuzhiyun <100000000>, <816000000>, 57*4882a593Smuzhiyun <200000000>, <100000000>, 58*4882a593Smuzhiyun <300000000>, <200000000>, 59*4882a593Smuzhiyun <100000000>, <80000000>; 60*4882a593Smuzhiyun}; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun&csi_tx { 63*4882a593Smuzhiyun status = "okay"; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun panel@0 { 66*4882a593Smuzhiyun compatible = "simple-panel-dsi"; 67*4882a593Smuzhiyun reg = <0>; 68*4882a593Smuzhiyun dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 69*4882a593Smuzhiyun MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET | 70*4882a593Smuzhiyun MIPI_DSI_CLOCK_NON_CONTINUOUS)>; 71*4882a593Smuzhiyun dsi,format = <MIPI_CSI_FMT_RAW8>; 72*4882a593Smuzhiyun dsi,lanes = <4>; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun display-timings { 75*4882a593Smuzhiyun native-mode = <&timing_1280x3_720>; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun timing_1280x3_720: timing-1280x3-720 { 78*4882a593Smuzhiyun clock-frequency = <80000000>; 79*4882a593Smuzhiyun hactive = <3840>; 80*4882a593Smuzhiyun vactive = <720>; 81*4882a593Smuzhiyun hfront-porch = <1200>; 82*4882a593Smuzhiyun hsync-len = <500>; 83*4882a593Smuzhiyun hback-porch = <30>; 84*4882a593Smuzhiyun vfront-porch = <40>; 85*4882a593Smuzhiyun vsync-len = <20>; 86*4882a593Smuzhiyun vback-porch = <40>; 87*4882a593Smuzhiyun hsync-active = <0>; 88*4882a593Smuzhiyun vsync-active = <0>; 89*4882a593Smuzhiyun de-active = <0>; 90*4882a593Smuzhiyun pixelclk-active = <0>; 91*4882a593Smuzhiyun }; 92*4882a593Smuzhiyun timing_4k: timing-4k { 93*4882a593Smuzhiyun clock-frequency = <250000000>; 94*4882a593Smuzhiyun hactive = <3840>; 95*4882a593Smuzhiyun vactive = <2160>; 96*4882a593Smuzhiyun hfront-porch = <1500>; 97*4882a593Smuzhiyun hsync-len = <500>; 98*4882a593Smuzhiyun hback-porch = <30>; 99*4882a593Smuzhiyun vfront-porch = <40>; 100*4882a593Smuzhiyun vsync-len = <20>; 101*4882a593Smuzhiyun vback-porch = <40>; 102*4882a593Smuzhiyun hsync-active = <0>; 103*4882a593Smuzhiyun vsync-active = <0>; 104*4882a593Smuzhiyun de-active = <0>; 105*4882a593Smuzhiyun pixelclk-active = <0>; 106*4882a593Smuzhiyun }; 107*4882a593Smuzhiyun timing_4096: timing-4096 { 108*4882a593Smuzhiyun clock-frequency = <190000000>; 109*4882a593Smuzhiyun hactive = <4096>; 110*4882a593Smuzhiyun vactive = <2048>; 111*4882a593Smuzhiyun hfront-porch = <1500>; 112*4882a593Smuzhiyun hsync-len = <500>; 113*4882a593Smuzhiyun hback-porch = <30>; 114*4882a593Smuzhiyun vfront-porch = <40>; 115*4882a593Smuzhiyun vsync-len = <20>; 116*4882a593Smuzhiyun vback-porch = <40>; 117*4882a593Smuzhiyun hsync-active = <0>; 118*4882a593Smuzhiyun vsync-active = <0>; 119*4882a593Smuzhiyun de-active = <0>; 120*4882a593Smuzhiyun pixelclk-active = <0>; 121*4882a593Smuzhiyun }; 122*4882a593Smuzhiyun timing_1920x3_1080: timing-1920x3-1080 { 123*4882a593Smuzhiyun clock-frequency = <250000000>; 124*4882a593Smuzhiyun hactive = <5760>; 125*4882a593Smuzhiyun vactive = <1080>; 126*4882a593Smuzhiyun hfront-porch = <1500>; 127*4882a593Smuzhiyun hsync-len = <70>; 128*4882a593Smuzhiyun hback-porch = <30>; 129*4882a593Smuzhiyun vfront-porch = <40>; 130*4882a593Smuzhiyun vsync-len = <20>; 131*4882a593Smuzhiyun vback-porch = <40>; 132*4882a593Smuzhiyun hsync-active = <0>; 133*4882a593Smuzhiyun vsync-active = <0>; 134*4882a593Smuzhiyun de-active = <0>; 135*4882a593Smuzhiyun pixelclk-active = <0>; 136*4882a593Smuzhiyun }; 137*4882a593Smuzhiyun }; 138*4882a593Smuzhiyun }; 139*4882a593Smuzhiyun}; 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun&display_subsystem { 142*4882a593Smuzhiyun status = "okay"; 143*4882a593Smuzhiyun}; 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun&emmc { 146*4882a593Smuzhiyun status = "disabled"; 147*4882a593Smuzhiyun}; 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun&gmac { 150*4882a593Smuzhiyun status = "disabled"; 151*4882a593Smuzhiyun}; 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun&i2c0 { 154*4882a593Smuzhiyun status = "okay"; 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun vcamera@30 { 157*4882a593Smuzhiyun compatible = "rockchip,virtual-camera"; 158*4882a593Smuzhiyun reg = <0x30>; 159*4882a593Smuzhiyun width = <1280>; 160*4882a593Smuzhiyun height = <720>; 161*4882a593Smuzhiyun bus-format = <MEDIA_BUS_FMT_RGB888_1X24>; 162*4882a593Smuzhiyun 163*4882a593Smuzhiyun port { 164*4882a593Smuzhiyun vcamera_out: endpoint { 165*4882a593Smuzhiyun remote-endpoint = <&dphy_rx_in>; 166*4882a593Smuzhiyun link-frequencies = /bits/ 64 <320000000>; 167*4882a593Smuzhiyun }; 168*4882a593Smuzhiyun }; 169*4882a593Smuzhiyun }; 170*4882a593Smuzhiyun}; 171*4882a593Smuzhiyun 172*4882a593Smuzhiyun&i2c1 { 173*4882a593Smuzhiyun status = "disabled"; 174*4882a593Smuzhiyun}; 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun&i2c4 { 177*4882a593Smuzhiyun status = "disabled"; 178*4882a593Smuzhiyun}; 179*4882a593Smuzhiyun 180*4882a593Smuzhiyun&mipi_dphy { 181*4882a593Smuzhiyun status = "okay"; 182*4882a593Smuzhiyun}; 183*4882a593Smuzhiyun 184*4882a593Smuzhiyun&mipi_dphy_rx { 185*4882a593Smuzhiyun status = "okay"; 186*4882a593Smuzhiyun 187*4882a593Smuzhiyun ports { 188*4882a593Smuzhiyun #address-cells = <1>; 189*4882a593Smuzhiyun #size-cells = <0>; 190*4882a593Smuzhiyun 191*4882a593Smuzhiyun port@0 { 192*4882a593Smuzhiyun reg = <0>; 193*4882a593Smuzhiyun #address-cells = <1>; 194*4882a593Smuzhiyun #size-cells = <0>; 195*4882a593Smuzhiyun 196*4882a593Smuzhiyun dphy_rx_in: endpoint@1 { 197*4882a593Smuzhiyun reg = <1>; 198*4882a593Smuzhiyun remote-endpoint = <&vcamera_out>; 199*4882a593Smuzhiyun data-lanes = <1 2 3 4>; 200*4882a593Smuzhiyun }; 201*4882a593Smuzhiyun }; 202*4882a593Smuzhiyun 203*4882a593Smuzhiyun port@1 { 204*4882a593Smuzhiyun reg = <1>; 205*4882a593Smuzhiyun #address-cells = <1>; 206*4882a593Smuzhiyun #size-cells = <0>; 207*4882a593Smuzhiyun 208*4882a593Smuzhiyun dphy_rx_out: endpoint@0 { 209*4882a593Smuzhiyun reg = <0>; 210*4882a593Smuzhiyun remote-endpoint = <&cif_in>; 211*4882a593Smuzhiyun }; 212*4882a593Smuzhiyun }; 213*4882a593Smuzhiyun }; 214*4882a593Smuzhiyun}; 215*4882a593Smuzhiyun 216*4882a593Smuzhiyun&rk809_codec { 217*4882a593Smuzhiyun status = "disabled"; 218*4882a593Smuzhiyun}; 219*4882a593Smuzhiyun 220*4882a593Smuzhiyun&rk_rga { 221*4882a593Smuzhiyun status = "okay"; 222*4882a593Smuzhiyun}; 223*4882a593Smuzhiyun 224*4882a593Smuzhiyun&route_csi { 225*4882a593Smuzhiyun status = "disabled"; 226*4882a593Smuzhiyun}; 227*4882a593Smuzhiyun 228*4882a593Smuzhiyun&sdmmc { 229*4882a593Smuzhiyun status = "disabled"; 230*4882a593Smuzhiyun}; 231*4882a593Smuzhiyun 232*4882a593Smuzhiyun&sdio { 233*4882a593Smuzhiyun status = "disabled"; 234*4882a593Smuzhiyun}; 235*4882a593Smuzhiyun 236*4882a593Smuzhiyun&sfc { 237*4882a593Smuzhiyun status = "okay"; 238*4882a593Smuzhiyun}; 239*4882a593Smuzhiyun 240*4882a593Smuzhiyun&uart4 { 241*4882a593Smuzhiyun status = "disabled"; 242*4882a593Smuzhiyun}; 243*4882a593Smuzhiyun 244*4882a593Smuzhiyun&wireless_bluetooth { 245*4882a593Smuzhiyun status = "disabled"; 246*4882a593Smuzhiyun}; 247*4882a593Smuzhiyun 248*4882a593Smuzhiyun&wireless_wlan { 249*4882a593Smuzhiyun status = "disabled"; 250*4882a593Smuzhiyun}; 251*4882a593Smuzhiyun 252*4882a593Smuzhiyun&tsadc { 253*4882a593Smuzhiyun rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ 254*4882a593Smuzhiyun rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ 255*4882a593Smuzhiyun pinctrl-names = "init", "default"; 256*4882a593Smuzhiyun pinctrl-0 = <&tsadc_otp_gpio>; 257*4882a593Smuzhiyun pinctrl-1 = <&tsadc_otp_out>; 258*4882a593Smuzhiyun status = "okay"; 259*4882a593Smuzhiyun}; 260*4882a593Smuzhiyun 261*4882a593Smuzhiyun&vop_raw { 262*4882a593Smuzhiyun status = "okay"; 263*4882a593Smuzhiyun}; 264*4882a593Smuzhiyun 265*4882a593Smuzhiyun&vopr_mmu { 266*4882a593Smuzhiyun status = "okay"; 267*4882a593Smuzhiyun}; 268*4882a593Smuzhiyun 269*4882a593Smuzhiyun&vpu_mmu { 270*4882a593Smuzhiyun status = "okay"; 271*4882a593Smuzhiyun}; 272