1*4882a593Smuzhiyun================================ 2*4882a593SmuzhiyunDriver for PXA25x LCD controller 3*4882a593Smuzhiyun================================ 4*4882a593Smuzhiyun 5*4882a593SmuzhiyunThe driver supports the following options, either via 6*4882a593Smuzhiyunoptions=<OPTIONS> when modular or video=pxafb:<OPTIONS> when built in. 7*4882a593Smuzhiyun 8*4882a593SmuzhiyunFor example:: 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun modprobe pxafb options=vmem:2M,mode:640x480-8,passive 11*4882a593Smuzhiyun 12*4882a593Smuzhiyunor on the kernel command line:: 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun video=pxafb:vmem:2M,mode:640x480-8,passive 15*4882a593Smuzhiyun 16*4882a593Smuzhiyunvmem: VIDEO_MEM_SIZE 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun Amount of video memory to allocate (can be suffixed with K or M 19*4882a593Smuzhiyun for kilobytes or megabytes) 20*4882a593Smuzhiyun 21*4882a593Smuzhiyunmode:XRESxYRES[-BPP] 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun XRES == LCCR1_PPL + 1 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun YRES == LLCR2_LPP + 1 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun The resolution of the display in pixels 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun BPP == The bit depth. Valid values are 1, 2, 4, 8 and 16. 30*4882a593Smuzhiyun 31*4882a593Smuzhiyunpixclock:PIXCLOCK 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun Pixel clock in picoseconds 34*4882a593Smuzhiyun 35*4882a593Smuzhiyunleft:LEFT == LCCR1_BLW + 1 36*4882a593Smuzhiyun 37*4882a593Smuzhiyunright:RIGHT == LCCR1_ELW + 1 38*4882a593Smuzhiyun 39*4882a593Smuzhiyunhsynclen:HSYNC == LCCR1_HSW + 1 40*4882a593Smuzhiyun 41*4882a593Smuzhiyunupper:UPPER == LCCR2_BFW 42*4882a593Smuzhiyun 43*4882a593Smuzhiyunlower:LOWER == LCCR2_EFR 44*4882a593Smuzhiyun 45*4882a593Smuzhiyunvsynclen:VSYNC == LCCR2_VSW + 1 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun Display margins and sync times 48*4882a593Smuzhiyun 49*4882a593Smuzhiyuncolor | mono => LCCR0_CMS 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun umm... 52*4882a593Smuzhiyun 53*4882a593Smuzhiyunactive | passive => LCCR0_PAS 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun Active (TFT) or Passive (STN) display 56*4882a593Smuzhiyun 57*4882a593Smuzhiyunsingle | dual => LCCR0_SDS 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun Single or dual panel passive display 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun4pix | 8pix => LCCR0_DPD 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun 4 or 8 pixel monochrome single panel data 64*4882a593Smuzhiyun 65*4882a593Smuzhiyunhsync:HSYNC, vsync:VSYNC 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun Horizontal and vertical sync. 0 => active low, 1 => active 68*4882a593Smuzhiyun high. 69*4882a593Smuzhiyun 70*4882a593Smuzhiyundpc:DPC 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun Double pixel clock. 1=>true, 0=>false 73*4882a593Smuzhiyun 74*4882a593Smuzhiyunoutputen:POLARITY 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun Output Enable Polarity. 0 => active low, 1 => active high 77*4882a593Smuzhiyun 78*4882a593Smuzhiyunpixclockpol:POLARITY 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun pixel clock polarity 81*4882a593Smuzhiyun 0 => falling edge, 1 => rising edge 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun 84*4882a593SmuzhiyunOverlay Support for PXA27x and later LCD controllers 85*4882a593Smuzhiyun==================================================== 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun PXA27x and later processors support overlay1 and overlay2 on-top of the 88*4882a593Smuzhiyun base framebuffer (although under-neath the base is also possible). They 89*4882a593Smuzhiyun support palette and no-palette RGB formats, as well as YUV formats (only 90*4882a593Smuzhiyun available on overlay2). These overlays have dedicated DMA channels and 91*4882a593Smuzhiyun behave in a similar way as a framebuffer. 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun However, there are some differences between these overlay framebuffers 94*4882a593Smuzhiyun and normal framebuffers, as listed below: 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun 1. overlay can start at a 32-bit word aligned position within the base 97*4882a593Smuzhiyun framebuffer, which means they have a start (x, y). This information 98*4882a593Smuzhiyun is encoded into var->nonstd (no, var->xoffset and var->yoffset are 99*4882a593Smuzhiyun not for such purpose). 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun 2. overlay framebuffer is allocated dynamically according to specified 102*4882a593Smuzhiyun 'struct fb_var_screeninfo', the amount is decided by:: 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun var->xres_virtual * var->yres_virtual * bpp 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun bpp = 16 -- for RGB565 or RGBT555 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun bpp = 24 -- for YUV444 packed 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun bpp = 24 -- for YUV444 planar 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun bpp = 16 -- for YUV422 planar (1 pixel = 1 Y + 1/2 Cb + 1/2 Cr) 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun bpp = 12 -- for YUV420 planar (1 pixel = 1 Y + 1/4 Cb + 1/4 Cr) 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun NOTE: 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun a. overlay does not support panning in x-direction, thus 119*4882a593Smuzhiyun var->xres_virtual will always be equal to var->xres 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun b. line length of overlay(s) must be on a 32-bit word boundary, 122*4882a593Smuzhiyun for YUV planar modes, it is a requirement for the component 123*4882a593Smuzhiyun with minimum bits per pixel, e.g. for YUV420, Cr component 124*4882a593Smuzhiyun for one pixel is actually 2-bits, it means the line length 125*4882a593Smuzhiyun should be a multiple of 16-pixels 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun c. starting horizontal position (XPOS) should start on a 32-bit 128*4882a593Smuzhiyun word boundary, otherwise the fb_check_var() will just fail. 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun d. the rectangle of the overlay should be within the base plane, 131*4882a593Smuzhiyun otherwise fail 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun Applications should follow the sequence below to operate an overlay 134*4882a593Smuzhiyun framebuffer: 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun a. open("/dev/fb[1-2]", ...) 137*4882a593Smuzhiyun b. ioctl(fd, FBIOGET_VSCREENINFO, ...) 138*4882a593Smuzhiyun c. modify 'var' with desired parameters: 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun 1) var->xres and var->yres 141*4882a593Smuzhiyun 2) larger var->yres_virtual if more memory is required, 142*4882a593Smuzhiyun usually for double-buffering 143*4882a593Smuzhiyun 3) var->nonstd for starting (x, y) and color format 144*4882a593Smuzhiyun 4) var->{red, green, blue, transp} if RGB mode is to be used 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun d. ioctl(fd, FBIOPUT_VSCREENINFO, ...) 147*4882a593Smuzhiyun e. ioctl(fd, FBIOGET_FSCREENINFO, ...) 148*4882a593Smuzhiyun f. mmap 149*4882a593Smuzhiyun g. ... 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun 3. for YUV planar formats, these are actually not supported within the 152*4882a593Smuzhiyun framebuffer framework, application has to take care of the offsets 153*4882a593Smuzhiyun and lengths of each component within the framebuffer. 154*4882a593Smuzhiyun 155*4882a593Smuzhiyun 4. var->nonstd is used to pass starting (x, y) position and color format, 156*4882a593Smuzhiyun the detailed bit fields are shown below:: 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun 31 23 20 10 0 159*4882a593Smuzhiyun +-----------------+---+----------+----------+ 160*4882a593Smuzhiyun | ... unused ... |FOR| XPOS | YPOS | 161*4882a593Smuzhiyun +-----------------+---+----------+----------+ 162*4882a593Smuzhiyun 163*4882a593Smuzhiyun FOR - color format, as defined by OVERLAY_FORMAT_* in pxafb.h 164*4882a593Smuzhiyun 165*4882a593Smuzhiyun - 0 - RGB 166*4882a593Smuzhiyun - 1 - YUV444 PACKED 167*4882a593Smuzhiyun - 2 - YUV444 PLANAR 168*4882a593Smuzhiyun - 3 - YUV422 PLANAR 169*4882a593Smuzhiyun - 4 - YUR420 PLANAR 170*4882a593Smuzhiyun 171*4882a593Smuzhiyun XPOS - starting horizontal position 172*4882a593Smuzhiyun 173*4882a593Smuzhiyun YPOS - starting vertical position 174