xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/rv1126-rmsl.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun#include <dt-bindings/display/drm_mipi_dsi.h>
7*4882a593Smuzhiyun#include <dt-bindings/input/input.h>
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun/ {
10*4882a593Smuzhiyun	vcc5v0_sys: vccsys {
11*4882a593Smuzhiyun		compatible = "regulator-fixed";
12*4882a593Smuzhiyun		regulator-name = "vcc5v0_sys";
13*4882a593Smuzhiyun		regulator-always-on;
14*4882a593Smuzhiyun		regulator-boot-on;
15*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
16*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
17*4882a593Smuzhiyun	};
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun	vdd_arm: vdd-arm {
20*4882a593Smuzhiyun		compatible = "pwm-regulator";
21*4882a593Smuzhiyun		pwms = <&pwm0 0 5000 1>;
22*4882a593Smuzhiyun		regulator-name = "vdd_arm";
23*4882a593Smuzhiyun		regulator-min-microvolt = <725000>;
24*4882a593Smuzhiyun		regulator-max-microvolt = <1000000>;
25*4882a593Smuzhiyun		regulator-init-microvolt = <900000>;
26*4882a593Smuzhiyun		regulator-always-on;
27*4882a593Smuzhiyun		regulator-boot-on;
28*4882a593Smuzhiyun		regulator-settling-time-up-us = <250>;
29*4882a593Smuzhiyun		pwm-supply = <&vcc5v0_sys>;
30*4882a593Smuzhiyun		status = "okay";
31*4882a593Smuzhiyun	};
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun	vdd_npu: vdd-npu {
34*4882a593Smuzhiyun		compatible = "pwm-regulator";
35*4882a593Smuzhiyun		pwms = <&pwm1 0 5000 1>;
36*4882a593Smuzhiyun		regulator-name = "vdd_npu";
37*4882a593Smuzhiyun		regulator-min-microvolt = <725000>;
38*4882a593Smuzhiyun		regulator-max-microvolt = <875000>;
39*4882a593Smuzhiyun		regulator-init-microvolt = <825000>;
40*4882a593Smuzhiyun		regulator-always-on;
41*4882a593Smuzhiyun		regulator-boot-on;
42*4882a593Smuzhiyun		regulator-settling-time-up-us = <250>;
43*4882a593Smuzhiyun		pwm-supply = <&vcc5v0_sys>;
44*4882a593Smuzhiyun		status = "okay";
45*4882a593Smuzhiyun	};
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun	vdd_logic: vdd-logic {
48*4882a593Smuzhiyun		compatible = "pwm-regulator";
49*4882a593Smuzhiyun		pwms = <&pwm2 0 5000 1>;
50*4882a593Smuzhiyun		regulator-name = "vdd_logic";
51*4882a593Smuzhiyun		regulator-min-microvolt = <725000>;
52*4882a593Smuzhiyun		regulator-max-microvolt = <875000>;
53*4882a593Smuzhiyun		regulator-init-microvolt = <825000>;
54*4882a593Smuzhiyun		regulator-always-on;
55*4882a593Smuzhiyun		regulator-boot-on;
56*4882a593Smuzhiyun		regulator-settling-time-up-us = <250>;
57*4882a593Smuzhiyun		pwm-supply = <&vcc5v0_sys>;
58*4882a593Smuzhiyun		status = "disabled";
59*4882a593Smuzhiyun	};
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun	vdd_fixed: vdd-fixed {
62*4882a593Smuzhiyun		compatible = "regulator-fixed";
63*4882a593Smuzhiyun		regulator-name = "vdd_fixed";
64*4882a593Smuzhiyun		regulator-always-on;
65*4882a593Smuzhiyun		regulator-boot-on;
66*4882a593Smuzhiyun		regulator-min-microvolt = <825000>;
67*4882a593Smuzhiyun		regulator-max-microvolt = <825000>;
68*4882a593Smuzhiyun	};
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun	vcc_3v3: vcc-3v3 {
71*4882a593Smuzhiyun		compatible = "regulator-fixed";
72*4882a593Smuzhiyun		regulator-name = "vcc_3v3";
73*4882a593Smuzhiyun		regulator-always-on;
74*4882a593Smuzhiyun		regulator-boot-on;
75*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
76*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
77*4882a593Smuzhiyun	};
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun	vcc_1v8: vcc-1v8 {
80*4882a593Smuzhiyun		compatible = "regulator-fixed";
81*4882a593Smuzhiyun		regulator-name = "vcc_1v8";
82*4882a593Smuzhiyun		regulator-always-on;
83*4882a593Smuzhiyun		regulator-boot-on;
84*4882a593Smuzhiyun		regulator-min-microvolt = <1800000>;
85*4882a593Smuzhiyun		regulator-max-microvolt = <1800000>;
86*4882a593Smuzhiyun	};
87*4882a593Smuzhiyun};
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun&cpu0 {
90*4882a593Smuzhiyun	cpu-supply = <&vdd_arm>;
91*4882a593Smuzhiyun};
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun&cpu_tsadc {
94*4882a593Smuzhiyun	rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
95*4882a593Smuzhiyun	rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
96*4882a593Smuzhiyun	pinctrl-names = "gpio", "otpout";
97*4882a593Smuzhiyun	pinctrl-0 = <&tsadcm0_shut>;
98*4882a593Smuzhiyun	pinctrl-1 = <&tsadc_shutorg>;
99*4882a593Smuzhiyun	status = "okay";
100*4882a593Smuzhiyun};
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun&display_subsystem {
103*4882a593Smuzhiyun	status = "okay";
104*4882a593Smuzhiyun};
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun&emmc {
107*4882a593Smuzhiyun	bus-width = <8>;
108*4882a593Smuzhiyun	cap-mmc-highspeed;
109*4882a593Smuzhiyun	non-removable;
110*4882a593Smuzhiyun	mmc-hs200-1_8v;
111*4882a593Smuzhiyun	rockchip,default-sample-phase = <90>;
112*4882a593Smuzhiyun	no-sdio;
113*4882a593Smuzhiyun	no-sd;
114*4882a593Smuzhiyun	/delete-property/ pinctrl-names;
115*4882a593Smuzhiyun	/delete-property/ pinctrl-0;
116*4882a593Smuzhiyun	status = "okay";
117*4882a593Smuzhiyun};
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun&fiq_debugger {
120*4882a593Smuzhiyun	status = "okay";
121*4882a593Smuzhiyun};
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun&mpp_srv {
124*4882a593Smuzhiyun	status = "okay";
125*4882a593Smuzhiyun};
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun&nandc {
128*4882a593Smuzhiyun	#address-cells = <1>;
129*4882a593Smuzhiyun	#size-cells = <0>;
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun	nand@0 {
132*4882a593Smuzhiyun		reg = <0>;
133*4882a593Smuzhiyun		nand-bus-width = <8>;
134*4882a593Smuzhiyun		nand-ecc-mode = "hw";
135*4882a593Smuzhiyun		nand-ecc-strength = <16>;
136*4882a593Smuzhiyun		nand-ecc-step-size = <1024>;
137*4882a593Smuzhiyun	};
138*4882a593Smuzhiyun};
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun&npu {
141*4882a593Smuzhiyun	npu-supply = <&vdd_fixed>;
142*4882a593Smuzhiyun	status = "okay";
143*4882a593Smuzhiyun};
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun&npu_tsadc {
146*4882a593Smuzhiyun	rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
147*4882a593Smuzhiyun	rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
148*4882a593Smuzhiyun	pinctrl-names = "gpio", "otpout";
149*4882a593Smuzhiyun	pinctrl-0 = <&tsadcm0_shut>;
150*4882a593Smuzhiyun	pinctrl-1 = <&tsadc_shutorg>;
151*4882a593Smuzhiyun	status = "okay";
152*4882a593Smuzhiyun};
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun&optee {
155*4882a593Smuzhiyun	status = "disabled";
156*4882a593Smuzhiyun};
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun&otp {
159*4882a593Smuzhiyun	status = "okay";
160*4882a593Smuzhiyun};
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun&pinctrl {
163*4882a593Smuzhiyun	pmic {
164*4882a593Smuzhiyun		/omit-if-no-ref/
165*4882a593Smuzhiyun		pmic_int: pmic_int {
166*4882a593Smuzhiyun			rockchip,pins =
167*4882a593Smuzhiyun				<0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
168*4882a593Smuzhiyun		};
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun		/omit-if-no-ref/
171*4882a593Smuzhiyun		soc_slppin_gpio: soc_slppin_gpio {
172*4882a593Smuzhiyun			rockchip,pins =
173*4882a593Smuzhiyun				<0 RK_PB2 RK_FUNC_GPIO &pcfg_output_low>;
174*4882a593Smuzhiyun		};
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun		/omit-if-no-ref/
177*4882a593Smuzhiyun		soc_slppin_slp: soc_slppin_slp {
178*4882a593Smuzhiyun			rockchip,pins =
179*4882a593Smuzhiyun				<0 RK_PB2 1 &pcfg_pull_none>;
180*4882a593Smuzhiyun		};
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun		/omit-if-no-ref/
183*4882a593Smuzhiyun		soc_slppin_rst: soc_slppin_rst {
184*4882a593Smuzhiyun			rockchip,pins =
185*4882a593Smuzhiyun				<0 RK_PB2 2 &pcfg_pull_none>;
186*4882a593Smuzhiyun		};
187*4882a593Smuzhiyun	};
188*4882a593Smuzhiyun};
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun&pmu_io_domains {
191*4882a593Smuzhiyun	status = "okay";
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun	pmuio0-supply = <&vcc_1v8>;
194*4882a593Smuzhiyun	pmuio1-supply = <&vcc_1v8>;
195*4882a593Smuzhiyun	vccio1-supply = <&vcc_1v8>;
196*4882a593Smuzhiyun	vccio2-supply = <&vcc_3v3>;
197*4882a593Smuzhiyun	vccio3-supply = <&vcc_1v8>;
198*4882a593Smuzhiyun	vccio4-supply = <&vcc_1v8>;
199*4882a593Smuzhiyun	vccio5-supply = <&vcc_3v3>;
200*4882a593Smuzhiyun	vccio6-supply = <&vcc_1v8>;
201*4882a593Smuzhiyun	vccio7-supply = <&vcc_1v8>;
202*4882a593Smuzhiyun};
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun&pwm0 {
205*4882a593Smuzhiyun	status = "okay";
206*4882a593Smuzhiyun	pinctrl-names = "active";
207*4882a593Smuzhiyun	pinctrl-0 = <&pwm0m0_pins_pull_down>;
208*4882a593Smuzhiyun};
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun&pwm1 {
211*4882a593Smuzhiyun	status = "okay";
212*4882a593Smuzhiyun	pinctrl-names = "active";
213*4882a593Smuzhiyun	pinctrl-0 = <&pwm1m0_pins_pull_down>;
214*4882a593Smuzhiyun};
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun&pwm2 {
217*4882a593Smuzhiyun	status = "disabled";
218*4882a593Smuzhiyun	pinctrl-names = "active";
219*4882a593Smuzhiyun	pinctrl-0 = <&pwm2m0_pins_pull_down>;
220*4882a593Smuzhiyun};
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun&ramoops {
223*4882a593Smuzhiyun	status = "okay";
224*4882a593Smuzhiyun};
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun&rk_rga {
227*4882a593Smuzhiyun	status = "okay";
228*4882a593Smuzhiyun};
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun&rkisp {
231*4882a593Smuzhiyun	status = "okay";
232*4882a593Smuzhiyun};
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun&mipi_csi2 {
235*4882a593Smuzhiyun	status = "okay";
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun	ports {
238*4882a593Smuzhiyun		#address-cells = <1>;
239*4882a593Smuzhiyun		#size-cells = <0>;
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun		port@0 {
242*4882a593Smuzhiyun			reg = <0>;
243*4882a593Smuzhiyun			#address-cells = <1>;
244*4882a593Smuzhiyun			#size-cells = <0>;
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun			mipi_csi2_input: endpoint@1 {
247*4882a593Smuzhiyun				reg = <1>;
248*4882a593Smuzhiyun				remote-endpoint = <&csidphy0_out>;
249*4882a593Smuzhiyun				data-lanes = <1 2>;
250*4882a593Smuzhiyun			};
251*4882a593Smuzhiyun		};
252*4882a593Smuzhiyun
253*4882a593Smuzhiyun		port@1 {
254*4882a593Smuzhiyun			reg = <1>;
255*4882a593Smuzhiyun			#address-cells = <1>;
256*4882a593Smuzhiyun			#size-cells = <0>;
257*4882a593Smuzhiyun
258*4882a593Smuzhiyun			mipi_csi2_output: endpoint@0 {
259*4882a593Smuzhiyun				reg = <0>;
260*4882a593Smuzhiyun				remote-endpoint = <&cif_mipi_in>;
261*4882a593Smuzhiyun				data-lanes = <1 2>;
262*4882a593Smuzhiyun			};
263*4882a593Smuzhiyun		};
264*4882a593Smuzhiyun	};
265*4882a593Smuzhiyun};
266*4882a593Smuzhiyun
267*4882a593Smuzhiyun&rkcif {
268*4882a593Smuzhiyun	status = "okay";
269*4882a593Smuzhiyun};
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun&rkcif_mmu {
272*4882a593Smuzhiyun	status = "disabled";
273*4882a593Smuzhiyun};
274*4882a593Smuzhiyun
275*4882a593Smuzhiyun&rkcif_dvp {
276*4882a593Smuzhiyun	status = "okay";
277*4882a593Smuzhiyun
278*4882a593Smuzhiyun	port {
279*4882a593Smuzhiyun		/* Parallel bus endpoint */
280*4882a593Smuzhiyun		/*
281*4882a593Smuzhiyun		cif_para_in: endpoint {
282*4882a593Smuzhiyun			remote-endpoint = <&cam_para_out1>;
283*4882a593Smuzhiyun			bus-width = <12>;
284*4882a593Smuzhiyun			hsync-active = <1>;
285*4882a593Smuzhiyun			vsync-active = <0>;
286*4882a593Smuzhiyun		};
287*4882a593Smuzhiyun		*/
288*4882a593Smuzhiyun	};
289*4882a593Smuzhiyun};
290*4882a593Smuzhiyun
291*4882a593Smuzhiyun&rkcif_mipi_lvds {
292*4882a593Smuzhiyun	status = "okay";
293*4882a593Smuzhiyun
294*4882a593Smuzhiyun	port {
295*4882a593Smuzhiyun		/* MIPI CSI-2 endpoint */
296*4882a593Smuzhiyun		cif_mipi_in: endpoint {
297*4882a593Smuzhiyun			remote-endpoint = <&mipi_csi2_output>;
298*4882a593Smuzhiyun			data-lanes = <1 2>;
299*4882a593Smuzhiyun		};
300*4882a593Smuzhiyun	};
301*4882a593Smuzhiyun};
302*4882a593Smuzhiyun
303*4882a593Smuzhiyun&rkcif_mipi_lvds_sditf {
304*4882a593Smuzhiyun	status = "okay";
305*4882a593Smuzhiyun
306*4882a593Smuzhiyun	port {
307*4882a593Smuzhiyun		/* MIPI CSI-2 endpoint */
308*4882a593Smuzhiyun		mipi_lvds_sditf: endpoint {
309*4882a593Smuzhiyun			/*remote-endpoint = <&isp_in>;*/
310*4882a593Smuzhiyun			data-lanes = <1 2>;
311*4882a593Smuzhiyun		};
312*4882a593Smuzhiyun	};
313*4882a593Smuzhiyun};
314*4882a593Smuzhiyun
315*4882a593Smuzhiyun&rkisp_vir0 {
316*4882a593Smuzhiyun	status = "okay";
317*4882a593Smuzhiyun
318*4882a593Smuzhiyun	ports {
319*4882a593Smuzhiyun		port@0 {
320*4882a593Smuzhiyun			reg = <0>;
321*4882a593Smuzhiyun			#address-cells = <1>;
322*4882a593Smuzhiyun			#size-cells = <0>;
323*4882a593Smuzhiyun
324*4882a593Smuzhiyun			isp_in: endpoint@0 {
325*4882a593Smuzhiyun				reg = <0>;
326*4882a593Smuzhiyun				remote-endpoint = <&csidphy1_out>;
327*4882a593Smuzhiyun			};
328*4882a593Smuzhiyun		};
329*4882a593Smuzhiyun	};
330*4882a593Smuzhiyun};
331*4882a593Smuzhiyun
332*4882a593Smuzhiyun&rkisp_mmu {
333*4882a593Smuzhiyun	status = "disabled";
334*4882a593Smuzhiyun};
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun&rkispp {
337*4882a593Smuzhiyun	status = "okay";
338*4882a593Smuzhiyun	/* the max input w h and fps of mulit sensor */
339*4882a593Smuzhiyun	//max-input = <2688 1520 30>;
340*4882a593Smuzhiyun};
341*4882a593Smuzhiyun
342*4882a593Smuzhiyun&rkispp_vir0 {
343*4882a593Smuzhiyun	status = "okay";
344*4882a593Smuzhiyun};
345*4882a593Smuzhiyun
346*4882a593Smuzhiyun&rkispp_mmu {
347*4882a593Smuzhiyun	status = "okay";
348*4882a593Smuzhiyun};
349*4882a593Smuzhiyun
350*4882a593Smuzhiyun&rkvdec {
351*4882a593Smuzhiyun	status = "okay";
352*4882a593Smuzhiyun};
353*4882a593Smuzhiyun
354*4882a593Smuzhiyun&rkvdec_mmu {
355*4882a593Smuzhiyun	status = "okay";
356*4882a593Smuzhiyun};
357*4882a593Smuzhiyun
358*4882a593Smuzhiyun&rkvenc {
359*4882a593Smuzhiyun	venc-supply = <&vdd_fixed>;
360*4882a593Smuzhiyun	status = "okay";
361*4882a593Smuzhiyun};
362*4882a593Smuzhiyun
363*4882a593Smuzhiyun&rkvenc_mmu {
364*4882a593Smuzhiyun	status = "okay";
365*4882a593Smuzhiyun};
366*4882a593Smuzhiyun
367*4882a593Smuzhiyun&rng {
368*4882a593Smuzhiyun	status = "okay";
369*4882a593Smuzhiyun};
370*4882a593Smuzhiyun
371*4882a593Smuzhiyun&saradc {
372*4882a593Smuzhiyun	status = "okay";
373*4882a593Smuzhiyun	vref-supply = <&vcc_1v8>;
374*4882a593Smuzhiyun};
375*4882a593Smuzhiyun
376*4882a593Smuzhiyun&u2phy0 {
377*4882a593Smuzhiyun	status = "okay";
378*4882a593Smuzhiyun	vup-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_LOW>;
379*4882a593Smuzhiyun	u2phy_otg: otg-port {
380*4882a593Smuzhiyun		status = "okay";
381*4882a593Smuzhiyun		rockchip,vbus-always-on;
382*4882a593Smuzhiyun	};
383*4882a593Smuzhiyun};
384*4882a593Smuzhiyun
385*4882a593Smuzhiyun&usbdrd {
386*4882a593Smuzhiyun	status = "okay";
387*4882a593Smuzhiyun};
388*4882a593Smuzhiyun
389*4882a593Smuzhiyun&usbdrd_dwc3 {
390*4882a593Smuzhiyun	status = "okay";
391*4882a593Smuzhiyun	snps,tx-fifo-resize;
392*4882a593Smuzhiyun	dr_mode = "peripheral";
393*4882a593Smuzhiyun};
394*4882a593Smuzhiyun
395*4882a593Smuzhiyun&vdpu {
396*4882a593Smuzhiyun	status = "okay";
397*4882a593Smuzhiyun};
398*4882a593Smuzhiyun
399*4882a593Smuzhiyun&vepu {
400*4882a593Smuzhiyun	status = "okay";
401*4882a593Smuzhiyun};
402*4882a593Smuzhiyun
403*4882a593Smuzhiyun&vpu_mmu {
404*4882a593Smuzhiyun	status = "okay";
405*4882a593Smuzhiyun};
406*4882a593Smuzhiyun
407*4882a593Smuzhiyun&vop {
408*4882a593Smuzhiyun	status = "okay";
409*4882a593Smuzhiyun};
410*4882a593Smuzhiyun
411*4882a593Smuzhiyun&vop_mmu {
412*4882a593Smuzhiyun	status = "okay";
413*4882a593Smuzhiyun};
414