1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6/dts-v1/; 7#include <dt-bindings/display/drm_mipi_dsi.h> 8#include "rk1808-evb.dtsi" 9 10/ { 11 model = "Rockchip RK1808 EVB V10 Board"; 12 compatible = "rockchip,rk1808-evb-v10", "rockchip,rk1808"; 13 14 chosen { 15 bootargs = "earlycon=uart8250,mmio32,0xff550000 console=ttyFIQ0 root=PARTUUID=614e0000-0000 rootfstype=ext4 rootwait kpti=0 snd_aloop.index=7"; 16 }; 17 18 vad-sound { 19 status = "okay"; 20 compatible = "rockchip,multicodecs-card"; 21 rockchip,card-name = "rockchip,rk1808-vad"; 22 rockchip,cpu = <&i2s0>; 23 rockchip,codec = <&vad>; 24 }; 25}; 26 27&adc_key { 28 vol-down-key { 29 linux,code = <KEY_VOLUMEDOWN>; 30 label = "volume down"; 31 press-threshold-microvolt = <300000>; 32 }; 33 34 vol-up-key { 35 linux,code = <KEY_VOLUMEUP>; 36 label = "volume up"; 37 press-threshold-microvolt = <18000>; 38 }; 39}; 40 41&display_subsystem { 42 status = "okay"; 43}; 44 45&dsi { 46 status = "okay"; 47 48 panel@0 { 49 compatible = "sitronix,st7703", "simple-panel-dsi"; 50 reg = <0>; 51 backlight = <&backlight>; 52 enable-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; 53 power-supply = <&vcc5v0_sys>; 54 prepare-delay-ms = <2>; 55 reset-delay-ms = <1>; 56 init-delay-ms = <20>; 57 enable-delay-ms = <120>; 58 disable-delay-ms = <50>; 59 unprepare-delay-ms = <20>; 60 61 width-mm = <68>; 62 height-mm = <121>; 63 64 dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 65 MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; 66 dsi,format = <MIPI_DSI_FMT_RGB888>; 67 dsi,lanes = <4>; 68 69 panel-init-sequence = [ 70 05 fa 01 11 71 39 00 04 b9 f1 12 83 72 39 00 1c ba 33 81 05 f9 0e 0e 00 00 00 73 00 00 00 00 00 44 25 00 91 0a 74 00 00 02 4f 01 00 00 37 75 15 00 02 b8 25 76 39 00 04 bf 02 11 00 77 39 00 0b b3 0c 10 0a 50 03 ff 00 00 00 78 00 79 39 00 0a c0 73 73 50 50 00 00 08 70 00 80 15 00 02 bc 46 81 15 00 02 cc 0b 82 15 00 02 b4 80 83 39 00 04 b2 c8 12 30 84 39 00 0f e3 07 07 0b 0b 03 0b 00 00 00 85 00 ff 00 c0 10 86 39 00 0d c1 53 00 1e 1e 77 e1 cc dd 67 87 77 33 33 88 39 00 07 c6 00 00 ff ff 01 ff 89 39 00 03 b5 09 09 90 39 00 03 b6 87 95 91 39 00 40 e9 c2 10 05 05 10 05 a0 12 31 92 23 3f 81 0a a0 37 18 00 80 01 93 00 00 00 00 80 01 00 00 00 48 94 f8 86 42 08 88 88 80 88 88 88 95 58 f8 87 53 18 88 88 81 88 88 96 88 00 00 00 01 00 00 00 00 00 97 00 00 00 00 98 39 00 3e ea 00 1a 00 00 00 00 02 00 00 99 00 00 00 1f 88 81 35 78 88 88 100 85 88 88 88 0f 88 80 24 68 88 101 88 84 88 88 88 23 10 00 00 1c 102 00 00 00 00 00 00 00 00 00 00 103 00 00 00 00 00 30 05 a0 00 00 104 00 00 105 39 00 23 e0 00 06 08 2a 31 3f 38 36 07 106 0c 0d 11 13 12 13 11 18 00 06 107 08 2a 31 3f 38 36 07 0c 0d 11 108 13 12 13 11 18 109 05 32 01 29 110 ]; 111 112 panel-exit-sequence = [ 113 05 00 01 28 114 05 00 01 10 115 ]; 116 117 display-timings { 118 native-mode = <&timing0>; 119 120 timing0: timing0 { 121 clock-frequency = <64000000>; 122 hactive = <720>; 123 vactive = <1280>; 124 hfront-porch = <40>; 125 hsync-len = <10>; 126 hback-porch = <40>; 127 vfront-porch = <22>; 128 vsync-len = <4>; 129 vback-porch = <11>; 130 hsync-active = <0>; 131 vsync-active = <0>; 132 de-active = <0>; 133 pixelclk-active = <0>; 134 }; 135 }; 136 137 ports { 138 #address-cells = <1>; 139 #size-cells = <0>; 140 141 port@0 { 142 reg = <0>; 143 panel_in_dsi: endpoint { 144 remote-endpoint = <&dsi_out_panel>; 145 }; 146 }; 147 }; 148 }; 149 150 ports { 151 #address-cells = <1>; 152 #size-cells = <0>; 153 154 port@1 { 155 reg = <1>; 156 dsi_out_panel: endpoint { 157 remote-endpoint = <&panel_in_dsi>; 158 }; 159 }; 160 }; 161}; 162 163&i2c3 { 164 status = "okay"; 165 166 clock-frequency = <100000>; 167 168 ov5695: ov5695@36 { 169 compatible = "ovti,ov5695"; 170 reg = <0x36>; 171 clocks = <&cru SCLK_CIF_OUT>; 172 clock-names = "xvclk"; 173 avdd-supply = <&vcc2v8_dvp>; 174 dovdd-supply = <&vdd1v5_dvp>; 175 dvdd-supply = <&vcc1v8_dvp>; 176 pwdn-gpios = <&gpio0 23 GPIO_ACTIVE_HIGH>; 177 pinctrl-names = "default"; 178 pinctrl-0 = <&cif_clkout_m0>; 179 port { 180 ucam_out: endpoint { 181 remote-endpoint = <&mipi_in_ucam>; 182 data-lanes = <1 2>; 183 }; 184 }; 185 }; 186}; 187 188&i2s0 { 189 status = "okay"; 190 #sound-dai-cells = <0>; 191}; 192 193&i2s1 { 194 status = "okay"; 195 #sound-dai-cells = <0>; 196}; 197 198&isp_mmu { 199 status = "okay"; 200}; 201 202&mipi_dphy { 203 status = "okay"; 204}; 205 206&mipi_dphy_rx { 207 status = "okay"; 208 209 ports { 210 #address-cells = <1>; 211 #size-cells = <0>; 212 213 port@0 { 214 reg = <0>; 215 #address-cells = <1>; 216 #size-cells = <0>; 217 218 mipi_in_ucam: endpoint@1 { 219 reg = <1>; 220 remote-endpoint = <&ucam_out>; 221 data-lanes = <1 2>; 222 }; 223 }; 224 225 port@1 { 226 reg = <1>; 227 #address-cells = <1>; 228 #size-cells = <0>; 229 230 dphy_rx0_out: endpoint@0 { 231 reg = <0>; 232 remote-endpoint = <&isp0_mipi_in>; 233 }; 234 }; 235 }; 236}; 237 238&rk_rga { 239 status = "okay"; 240}; 241 242&rk809_sound { 243 status = "okay"; 244}; 245 246&rkisp1 { 247 status = "okay"; 248 249 port { 250 #address-cells = <1>; 251 #size-cells = <0>; 252 253 isp0_mipi_in: endpoint@0 { 254 reg = <0>; 255 remote-endpoint = <&dphy_rx0_out>; 256 }; 257 }; 258}; 259 260&rng { 261 status = "okay"; 262}; 263 264&rockchip_suspend { 265 status = "okay"; 266 rockchip,sleep-debug-en = <1>; 267}; 268 269&route_dsi { 270 status = "disabled"; 271}; 272 273&tsadc { 274 rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ 275 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ 276 pinctrl-names = "gpio", "otpout"; 277 pinctrl-0 = <&tsadc_otp_gpio>; 278 pinctrl-1 = <&tsadc_otp_out>; 279 status = "okay"; 280}; 281 282&vad { 283 status = "okay"; 284 rockchip,audio-src = <&i2s0>; 285 rockchip,buffer-time-ms = <200>; 286 rockchip,det-channel = <0>; 287 rockchip,mode = <1>; 288 #sound-dai-cells = <0>; 289}; 290 291&vop_lite { 292 status = "okay"; 293}; 294 295&vopl_mmu { 296 status = "okay"; 297}; 298 299&vpu_mmu { 300 status = "okay"; 301}; 302 303&vpu_service { 304 status = "okay"; 305}; 306