1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2020 Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/display/drm_mipi_dsi.h> 7#include <dt-bindings/input/input.h> 8 9/ { 10 vcc5v0_sys: vccsys { 11 compatible = "regulator-fixed"; 12 regulator-name = "vcc5v0_sys"; 13 regulator-always-on; 14 regulator-boot-on; 15 regulator-min-microvolt = <5000000>; 16 regulator-max-microvolt = <5000000>; 17 }; 18 19 vdd_arm: vdd-arm { 20 compatible = "pwm-regulator"; 21 pwms = <&pwm0 0 5000 1>; 22 regulator-name = "vdd_arm"; 23 regulator-min-microvolt = <725000>; 24 regulator-max-microvolt = <1000000>; 25 regulator-init-microvolt = <900000>; 26 regulator-always-on; 27 regulator-boot-on; 28 regulator-settling-time-up-us = <250>; 29 pwm-supply = <&vcc5v0_sys>; 30 status = "okay"; 31 }; 32 33 vdd_npu: vdd-npu { 34 compatible = "pwm-regulator"; 35 pwms = <&pwm1 0 5000 1>; 36 regulator-name = "vdd_npu"; 37 regulator-min-microvolt = <725000>; 38 regulator-max-microvolt = <875000>; 39 regulator-init-microvolt = <825000>; 40 regulator-always-on; 41 regulator-boot-on; 42 regulator-settling-time-up-us = <250>; 43 pwm-supply = <&vcc5v0_sys>; 44 status = "okay"; 45 }; 46 47 vdd_logic: vdd-logic { 48 compatible = "pwm-regulator"; 49 pwms = <&pwm2 0 5000 1>; 50 regulator-name = "vdd_logic"; 51 regulator-min-microvolt = <725000>; 52 regulator-max-microvolt = <875000>; 53 regulator-init-microvolt = <825000>; 54 regulator-always-on; 55 regulator-boot-on; 56 regulator-settling-time-up-us = <250>; 57 pwm-supply = <&vcc5v0_sys>; 58 status = "disabled"; 59 }; 60 61 vdd_fixed: vdd-fixed { 62 compatible = "regulator-fixed"; 63 regulator-name = "vdd_fixed"; 64 regulator-always-on; 65 regulator-boot-on; 66 regulator-min-microvolt = <825000>; 67 regulator-max-microvolt = <825000>; 68 }; 69 70 vcc_3v3: vcc-3v3 { 71 compatible = "regulator-fixed"; 72 regulator-name = "vcc_3v3"; 73 regulator-always-on; 74 regulator-boot-on; 75 regulator-min-microvolt = <3300000>; 76 regulator-max-microvolt = <3300000>; 77 }; 78 79 vcc_1v8: vcc-1v8 { 80 compatible = "regulator-fixed"; 81 regulator-name = "vcc_1v8"; 82 regulator-always-on; 83 regulator-boot-on; 84 regulator-min-microvolt = <1800000>; 85 regulator-max-microvolt = <1800000>; 86 }; 87}; 88 89&cpu0 { 90 cpu-supply = <&vdd_arm>; 91}; 92 93&cpu_tsadc { 94 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ 95 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ 96 pinctrl-names = "gpio", "otpout"; 97 pinctrl-0 = <&tsadcm0_shut>; 98 pinctrl-1 = <&tsadc_shutorg>; 99 status = "okay"; 100}; 101 102&display_subsystem { 103 status = "okay"; 104}; 105 106&emmc { 107 bus-width = <8>; 108 cap-mmc-highspeed; 109 non-removable; 110 mmc-hs200-1_8v; 111 rockchip,default-sample-phase = <90>; 112 no-sdio; 113 no-sd; 114 /delete-property/ pinctrl-names; 115 /delete-property/ pinctrl-0; 116 status = "okay"; 117}; 118 119&fiq_debugger { 120 status = "okay"; 121}; 122 123&mpp_srv { 124 status = "okay"; 125}; 126 127&nandc { 128 #address-cells = <1>; 129 #size-cells = <0>; 130 131 nand@0 { 132 reg = <0>; 133 nand-bus-width = <8>; 134 nand-ecc-mode = "hw"; 135 nand-ecc-strength = <16>; 136 nand-ecc-step-size = <1024>; 137 }; 138}; 139 140&npu { 141 npu-supply = <&vdd_fixed>; 142 status = "okay"; 143}; 144 145&npu_tsadc { 146 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ 147 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ 148 pinctrl-names = "gpio", "otpout"; 149 pinctrl-0 = <&tsadcm0_shut>; 150 pinctrl-1 = <&tsadc_shutorg>; 151 status = "okay"; 152}; 153 154&optee { 155 status = "disabled"; 156}; 157 158&otp { 159 status = "okay"; 160}; 161 162&pinctrl { 163 pmic { 164 /omit-if-no-ref/ 165 pmic_int: pmic_int { 166 rockchip,pins = 167 <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; 168 }; 169 170 /omit-if-no-ref/ 171 soc_slppin_gpio: soc_slppin_gpio { 172 rockchip,pins = 173 <0 RK_PB2 RK_FUNC_GPIO &pcfg_output_low>; 174 }; 175 176 /omit-if-no-ref/ 177 soc_slppin_slp: soc_slppin_slp { 178 rockchip,pins = 179 <0 RK_PB2 1 &pcfg_pull_none>; 180 }; 181 182 /omit-if-no-ref/ 183 soc_slppin_rst: soc_slppin_rst { 184 rockchip,pins = 185 <0 RK_PB2 2 &pcfg_pull_none>; 186 }; 187 }; 188}; 189 190&pmu_io_domains { 191 status = "okay"; 192 193 pmuio0-supply = <&vcc_1v8>; 194 pmuio1-supply = <&vcc_1v8>; 195 vccio1-supply = <&vcc_1v8>; 196 vccio2-supply = <&vcc_3v3>; 197 vccio3-supply = <&vcc_1v8>; 198 vccio4-supply = <&vcc_1v8>; 199 vccio5-supply = <&vcc_3v3>; 200 vccio6-supply = <&vcc_1v8>; 201 vccio7-supply = <&vcc_1v8>; 202}; 203 204&pwm0 { 205 status = "okay"; 206 pinctrl-names = "active"; 207 pinctrl-0 = <&pwm0m0_pins_pull_down>; 208}; 209 210&pwm1 { 211 status = "okay"; 212 pinctrl-names = "active"; 213 pinctrl-0 = <&pwm1m0_pins_pull_down>; 214}; 215 216&pwm2 { 217 status = "disabled"; 218 pinctrl-names = "active"; 219 pinctrl-0 = <&pwm2m0_pins_pull_down>; 220}; 221 222&ramoops { 223 status = "okay"; 224}; 225 226&rk_rga { 227 status = "okay"; 228}; 229 230&rkisp { 231 status = "okay"; 232}; 233 234&mipi_csi2 { 235 status = "okay"; 236 237 ports { 238 #address-cells = <1>; 239 #size-cells = <0>; 240 241 port@0 { 242 reg = <0>; 243 #address-cells = <1>; 244 #size-cells = <0>; 245 246 mipi_csi2_input: endpoint@1 { 247 reg = <1>; 248 remote-endpoint = <&csidphy0_out>; 249 data-lanes = <1 2>; 250 }; 251 }; 252 253 port@1 { 254 reg = <1>; 255 #address-cells = <1>; 256 #size-cells = <0>; 257 258 mipi_csi2_output: endpoint@0 { 259 reg = <0>; 260 remote-endpoint = <&cif_mipi_in>; 261 data-lanes = <1 2>; 262 }; 263 }; 264 }; 265}; 266 267&rkcif { 268 status = "okay"; 269}; 270 271&rkcif_mmu { 272 status = "disabled"; 273}; 274 275&rkcif_dvp { 276 status = "okay"; 277 278 port { 279 /* Parallel bus endpoint */ 280 /* 281 cif_para_in: endpoint { 282 remote-endpoint = <&cam_para_out1>; 283 bus-width = <12>; 284 hsync-active = <1>; 285 vsync-active = <0>; 286 }; 287 */ 288 }; 289}; 290 291&rkcif_mipi_lvds { 292 status = "okay"; 293 294 port { 295 /* MIPI CSI-2 endpoint */ 296 cif_mipi_in: endpoint { 297 remote-endpoint = <&mipi_csi2_output>; 298 data-lanes = <1 2>; 299 }; 300 }; 301}; 302 303&rkcif_mipi_lvds_sditf { 304 status = "okay"; 305 306 port { 307 /* MIPI CSI-2 endpoint */ 308 mipi_lvds_sditf: endpoint { 309 /*remote-endpoint = <&isp_in>;*/ 310 data-lanes = <1 2>; 311 }; 312 }; 313}; 314 315&rkisp_vir0 { 316 status = "okay"; 317 318 ports { 319 port@0 { 320 reg = <0>; 321 #address-cells = <1>; 322 #size-cells = <0>; 323 324 isp_in: endpoint@0 { 325 reg = <0>; 326 remote-endpoint = <&csidphy1_out>; 327 }; 328 }; 329 }; 330}; 331 332&rkisp_mmu { 333 status = "disabled"; 334}; 335 336&rkispp { 337 status = "okay"; 338 /* the max input w h and fps of mulit sensor */ 339 //max-input = <2688 1520 30>; 340}; 341 342&rkispp_vir0 { 343 status = "okay"; 344}; 345 346&rkispp_mmu { 347 status = "okay"; 348}; 349 350&rkvdec { 351 status = "okay"; 352}; 353 354&rkvdec_mmu { 355 status = "okay"; 356}; 357 358&rkvenc { 359 venc-supply = <&vdd_fixed>; 360 status = "okay"; 361}; 362 363&rkvenc_mmu { 364 status = "okay"; 365}; 366 367&rng { 368 status = "okay"; 369}; 370 371&saradc { 372 status = "okay"; 373 vref-supply = <&vcc_1v8>; 374}; 375 376&u2phy0 { 377 status = "okay"; 378 vup-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_LOW>; 379 u2phy_otg: otg-port { 380 status = "okay"; 381 rockchip,vbus-always-on; 382 }; 383}; 384 385&usbdrd { 386 status = "okay"; 387}; 388 389&usbdrd_dwc3 { 390 status = "okay"; 391 snps,tx-fifo-resize; 392 dr_mode = "peripheral"; 393}; 394 395&vdpu { 396 status = "okay"; 397}; 398 399&vepu { 400 status = "okay"; 401}; 402 403&vpu_mmu { 404 status = "okay"; 405}; 406 407&vop { 408 status = "okay"; 409}; 410 411&vop_mmu { 412 status = "okay"; 413}; 414