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Searched full:pll5 (Results 1 – 25 of 45) sorted by relevance

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/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dsun5i.dtsi149 pll5: clk@01c20020 { label
151 compatible = "allwinner,sun4i-a10-pll5-clk";
242 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
250 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
258 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
268 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
278 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
288 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
296 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
304 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
[all …]
H A Dsun4i-a10.dtsi249 pll5: clk@01c20020 { label
251 compatible = "allwinner,sun4i-a10-pll5-clk";
411 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
419 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
427 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
437 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
447 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
457 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
467 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
475 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
[all …]
H A Dsun5i-gr8.dtsi149 pll5: clk@01c20020 { label
151 compatible = "allwinner,sun4i-a10-pll5-clk";
293 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
301 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
309 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
319 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
329 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
339 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
347 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
355 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
[all …]
H A Dsun7i-a20.dtsi251 pll5: clk@01c20020 { label
253 compatible = "allwinner,sun4i-a10-pll5-clk";
410 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
418 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
426 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
436 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
446 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
456 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
466 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
474 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
[all …]
H A Dsun5i-a10s.dtsi68 clocks = <&pll3>, <&pll5 1>, <&ahb_gates 36>,
77 clocks = <&pll3>, <&pll5 1>, <&ahb_gates 36>,
86 clocks = <&pll3>, <&pll5 1>, <&ahb_gates 34>,
H A Dsun5i-a13.dtsi159 clocks = <&pll5 0>;
179 clocks = <&pll3>, <&pll7>, <&pll5 1>;
188 clocks = <&pll3>, <&pll7>, <&pll5 1>;
H A Dsun8i-a23.dtsi82 clocks = <&osc24M>, <&pll6 1>, <&pll5>;
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/
H A Dallwinner,sun4i-a10-pll5-clk.yaml4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-pll5-clk.yaml#
23 const: allwinner,sun4i-a10-pll5-clk
47 compatible = "allwinner,sun4i-a10-pll5-clk";
H A Dallwinner,sun4i-a10-mbus-clk.yaml50 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
59 clocks = <&osc24M>, <&pll6 1>, <&pll5>;
H A Dallwinner,sun4i-a10-display-clk.yaml53 clocks = <&pll3>, <&pll7>, <&pll5 1>;
H A Dallwinner,sun4i-a10-mmc-clk.yaml71 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
H A Dallwinner,sun4i-a10-mod0-clk.yaml67 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dclock_sun8i_a83t.h25 u32 pll5_cfg; /* 0x20 pll5 ddr control */
99 u32 pll5_bias_cfg; /* 0x230 PLL5 ddr Bias config */
113 u32 pll5_pattern_cfg0; /* 0x290 PLL5 Pattern register 0*/
118 u32 pll5_pattern_cfg1; /* 0x2b0 PLL5 Pattern register 1 */
254 #define CCM_DRAMPLL_CFG_SRC_PLL5 (0x0 << 16) /* Select PLL5 (DDR0) */
H A Dclock_sun4i.h23 u32 pll5_cfg; /* 0x20 pll5 control */
24 u32 pll5_tun; /* 0x24 pll5 tuning */
28 u32 pll1_tun2; /* 0x34 pll5 tuning2 */
30 u32 pll5_tun2; /* 0x3c pll5 tuning2 */
H A Dclock_sun6i.h23 u32 pll5_cfg; /* 0x20 pll5 control */
127 u32 pll5_bias_cfg; /* 0x230 PLL5 Bias config */
135 u32 pll5_tuning_cfg; /* 0x260 PLL5 Tuning config */
141 u32 pll5_pattern_cfg; /* 0x290 PLL5 Pattern config */
381 #define CCM_DRAMPLL_CFG_SRC_PLL5 (0x0 << 16) /* Select PLL5 (DDR0) */
/OK3568_Linux_fs/u-boot/arch/arm/mach-imx/mx6/
H A Dclock.c558 debug("pll5 div = %d, num = %d, denom = %d\n", in enable_pll_video()
561 /* Power up PLL5 video */ in enable_pll_video()
595 /* Wait PLL5 lock */ in enable_pll_video()
608 puts("Lock PLL5 timeout\n"); in enable_pll_video()
716 /* Select pre-lcd clock to PLL5 and set pre divider */ in mxs_set_lcdclk()
730 /* Select pre-lcd clock to PLL5 and set pre divider */ in mxs_set_lcdclk()
752 /* Select pre-lcd clock to PLL5 and set pre divider */ in mxs_set_lcdclk()
1337 /* Disable PLL5 */ in disable_ldb_di_clock_sources()
1362 * function temporarily disables PLL2 PFD's, PLL3 PFD's and PLL5.
/OK3568_Linux_fs/kernel/drivers/clk/renesas/
H A Dr8a779a0-cpg-mssr.c101 DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_R8A779A0_PLL5, CLK_MAIN),
231 * MD EXTAL PLL1 PLL20 PLL30 PLL4 PLL5 OSC
243 /* EXTAL div PLL1 mult/div PLL5 mult/div OSC prediv */
/OK3568_Linux_fs/u-boot/board/aristainetos/
H A Daristainetos-v2.c411 /* set PLL5 clock */ in enable_lvds()
416 /* set PLL5 to 232720000Hz */ in enable_lvds()
442 /* set LDB0, LDB1 clk select to 000/000 (PLL5 clock) */ in enable_lvds()
504 /* set PLL5 to 197994996Hz */ in enable_spi_display()
530 /* set LDB0, LDB1 clk select to 000/000 (PLL5 clock) */ in enable_spi_display()
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mips/
H A Dmscc.txt48 configuration and status of PLL5, RCOMP, SyncE, SerDes configurations and
/OK3568_Linux_fs/u-boot/arch/arm/mach-imx/mx7/
H A Dclock.c782 debug("pll5 div = %d, num = %d, denom = %d\n", in enable_pll_video()
785 /* Power up PLL5 video and disable its output */ in enable_pll_video()
835 /* Wait PLL5 lock */ in enable_pll_video()
848 printf("Lock PLL5 timeout\n"); in enable_pll_video()
/OK3568_Linux_fs/kernel/drivers/clk/mmp/
H A Dclk-of-pxa1928.c41 {0, "pll5", NULL, 0, 1248000000},
146 static const char *sdh_parent_names[] = {"pll1_624", "pll5p", "pll5", "pll1_416"};
/OK3568_Linux_fs/kernel/drivers/clk/sunxi/
H A Dclk-sunxi.c195 * sun4i_get_pll5_factors() - calculates n, k factors for PLL5
196 * PLL5 rate is calculated as follows
1017 clkflags = !strcmp("pll5", parent) ? 0 : CLK_SET_RATE_PARENT; in sunxi_divs_clk_setup()
1114 CLK_OF_DECLARE(sun4i_pll5, "allwinner,sun4i-a10-pll5-clk",
/OK3568_Linux_fs/u-boot/arch/arm/mach-sunxi/
H A Dclock_sun8i_a83t.c114 /* A83T PLL5 DDR rate = 24000000 * (n+1)/(div1+1)/(div2+1) */ in clock_set_pll5()
/OK3568_Linux_fs/u-boot/doc/
H A DREADME.Heterogeneous-SoCs55 PLL5, PLL3 is Reserved(as mentioned in RM), so this define contains the
/OK3568_Linux_fs/kernel/include/dt-bindings/clock/
H A Dqcom,gcc-msm8660.h258 #define PLL5 249 macro

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