xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mips/mscc.txt (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1*4882a593Smuzhiyun* Microsemi MIPS CPUs
2*4882a593Smuzhiyun
3*4882a593SmuzhiyunBoards with a SoC of the Microsemi MIPS family shall have the following
4*4882a593Smuzhiyunproperties:
5*4882a593Smuzhiyun
6*4882a593SmuzhiyunRequired properties:
7*4882a593Smuzhiyun- compatible: "mscc,ocelot"
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun* Other peripherals:
11*4882a593Smuzhiyun
12*4882a593Smuzhiyuno CPU chip regs:
13*4882a593Smuzhiyun
14*4882a593SmuzhiyunThe SoC has a few registers (DEVCPU_GCB:CHIP_REGS) handling miscellaneous
15*4882a593Smuzhiyunfunctionalities: chip ID, general purpose register for software use, reset
16*4882a593Smuzhiyuncontroller, hardware status and configuration, efuses.
17*4882a593Smuzhiyun
18*4882a593SmuzhiyunRequired properties:
19*4882a593Smuzhiyun- compatible: Should be "mscc,ocelot-chip-regs", "simple-mfd", "syscon"
20*4882a593Smuzhiyun- reg : Should contain registers location and length
21*4882a593Smuzhiyun
22*4882a593SmuzhiyunExample:
23*4882a593Smuzhiyun	syscon@71070000 {
24*4882a593Smuzhiyun		compatible = "mscc,ocelot-chip-regs", "simple-mfd", "syscon";
25*4882a593Smuzhiyun		reg = <0x71070000 0x1c>;
26*4882a593Smuzhiyun	};
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun
29*4882a593Smuzhiyuno CPU system control:
30*4882a593Smuzhiyun
31*4882a593SmuzhiyunThe SoC has a few registers (ICPU_CFG:CPU_SYSTEM_CTRL) handling configuration of
32*4882a593Smuzhiyunthe CPU: 8 general purpose registers, reset control, CPU en/disabling, CPU
33*4882a593Smuzhiyunendianness, CPU bus control, CPU status.
34*4882a593Smuzhiyun
35*4882a593SmuzhiyunRequired properties:
36*4882a593Smuzhiyun- compatible: Should be "mscc,ocelot-cpu-syscon", "syscon"
37*4882a593Smuzhiyun- reg : Should contain registers location and length
38*4882a593Smuzhiyun
39*4882a593SmuzhiyunExample:
40*4882a593Smuzhiyun	syscon@70000000 {
41*4882a593Smuzhiyun		compatible = "mscc,ocelot-cpu-syscon", "syscon";
42*4882a593Smuzhiyun		reg = <0x70000000 0x2c>;
43*4882a593Smuzhiyun	};
44*4882a593Smuzhiyun
45*4882a593Smuzhiyuno HSIO regs:
46*4882a593Smuzhiyun
47*4882a593SmuzhiyunThe SoC has a few registers (HSIO) handling miscellaneous functionalities:
48*4882a593Smuzhiyunconfiguration and status of PLL5, RCOMP, SyncE, SerDes configurations and
49*4882a593Smuzhiyunstatus, SerDes muxing and a thermal sensor.
50*4882a593Smuzhiyun
51*4882a593SmuzhiyunRequired properties:
52*4882a593Smuzhiyun- compatible: Should be "mscc,ocelot-hsio", "syscon", "simple-mfd"
53*4882a593Smuzhiyun- reg : Should contain registers location and length
54*4882a593Smuzhiyun
55*4882a593SmuzhiyunExample:
56*4882a593Smuzhiyun	syscon@10d0000 {
57*4882a593Smuzhiyun		compatible = "mscc,ocelot-hsio", "syscon", "simple-mfd";
58*4882a593Smuzhiyun		reg = <0x10d0000 0x10000>;
59*4882a593Smuzhiyun	};
60