1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun%YAML 1.2
3*4882a593Smuzhiyun---
4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-display-clk.yaml#
5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml#
6*4882a593Smuzhiyun
7*4882a593Smuzhiyuntitle: Allwinner A10 Display Clock Device Tree Bindings
8*4882a593Smuzhiyun
9*4882a593Smuzhiyunmaintainers:
10*4882a593Smuzhiyun  - Chen-Yu Tsai <wens@csie.org>
11*4882a593Smuzhiyun  - Maxime Ripard <mripard@kernel.org>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyundeprecated: true
14*4882a593Smuzhiyun
15*4882a593Smuzhiyunproperties:
16*4882a593Smuzhiyun  "#clock-cells":
17*4882a593Smuzhiyun    const: 0
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun  "#reset-cells":
20*4882a593Smuzhiyun    const: 0
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun  compatible:
23*4882a593Smuzhiyun    const: allwinner,sun4i-a10-display-clk
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun  reg:
26*4882a593Smuzhiyun    maxItems: 1
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun  clocks:
29*4882a593Smuzhiyun    maxItems: 3
30*4882a593Smuzhiyun    description: >
31*4882a593Smuzhiyun      The parent order must match the hardware programming order.
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun  clock-output-names:
34*4882a593Smuzhiyun    maxItems: 1
35*4882a593Smuzhiyun
36*4882a593Smuzhiyunrequired:
37*4882a593Smuzhiyun  - "#clock-cells"
38*4882a593Smuzhiyun  - "#reset-cells"
39*4882a593Smuzhiyun  - compatible
40*4882a593Smuzhiyun  - reg
41*4882a593Smuzhiyun  - clocks
42*4882a593Smuzhiyun  - clock-output-names
43*4882a593Smuzhiyun
44*4882a593SmuzhiyunadditionalProperties: false
45*4882a593Smuzhiyun
46*4882a593Smuzhiyunexamples:
47*4882a593Smuzhiyun  - |
48*4882a593Smuzhiyun    clk@1c20104 {
49*4882a593Smuzhiyun        #clock-cells = <0>;
50*4882a593Smuzhiyun        #reset-cells = <0>;
51*4882a593Smuzhiyun        compatible = "allwinner,sun4i-a10-display-clk";
52*4882a593Smuzhiyun        reg = <0x01c20104 0x4>;
53*4882a593Smuzhiyun        clocks = <&pll3>, <&pll7>, <&pll5 1>;
54*4882a593Smuzhiyun        clock-output-names = "de-be";
55*4882a593Smuzhiyun    };
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun...
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