1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * A83 specific clock code
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * (C) Copyright 2007-2012
5*4882a593Smuzhiyun * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
6*4882a593Smuzhiyun * Tom Cubie <tangliang@allwinnertech.com>
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com>
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
11*4882a593Smuzhiyun */
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include <common.h>
14*4882a593Smuzhiyun #include <asm/io.h>
15*4882a593Smuzhiyun #include <asm/arch/clock.h>
16*4882a593Smuzhiyun #include <asm/arch/prcm.h>
17*4882a593Smuzhiyun #include <asm/arch/sys_proto.h>
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #ifdef CONFIG_SPL_BUILD
clock_init_safe(void)20*4882a593Smuzhiyun void clock_init_safe(void)
21*4882a593Smuzhiyun {
22*4882a593Smuzhiyun struct sunxi_ccm_reg * const ccm =
23*4882a593Smuzhiyun (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun clock_set_pll1(408000000);
26*4882a593Smuzhiyun /* enable pll_hsic, default is 480M */
27*4882a593Smuzhiyun writel(PLL8_CFG_DEFAULT, &ccm->pll8_cfg);
28*4882a593Smuzhiyun writel(readl(&ccm->pll8_cfg) | (0x1 << 31), &ccm->pll8_cfg);
29*4882a593Smuzhiyun while (!(readl(&ccm->pll_stable_status) & (1 << 8))) {}
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun /* switch to default 24MHz before changing to hsic */
32*4882a593Smuzhiyun writel(0x0, &ccm->cci400_cfg);
33*4882a593Smuzhiyun sdelay(50);
34*4882a593Smuzhiyun writel(CCM_CCI400_CLK_SEL_HSIC, &ccm->cci400_cfg);
35*4882a593Smuzhiyun sdelay(100);
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun /* switch before changing pll6 */
38*4882a593Smuzhiyun clrsetbits_le32(&ccm->ahb1_apb1_div, AHB1_CLK_SRC_MASK,
39*4882a593Smuzhiyun AHB1_CLK_SRC_OSC24M);
40*4882a593Smuzhiyun writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
41*4882a593Smuzhiyun while (!(readl(&ccm->pll_stable_status) & (1 << 6))) {}
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div);
44*4882a593Smuzhiyun writel(CCM_MBUS_RESET_RESET, &ccm->mbus_reset);
45*4882a593Smuzhiyun writel(MBUS_CLK_DEFAULT, &ccm->mbus_clk_cfg);
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun /* timestamp */
48*4882a593Smuzhiyun writel(1, 0x01720000);
49*4882a593Smuzhiyun }
50*4882a593Smuzhiyun #endif
51*4882a593Smuzhiyun
clock_init_uart(void)52*4882a593Smuzhiyun void clock_init_uart(void)
53*4882a593Smuzhiyun {
54*4882a593Smuzhiyun struct sunxi_ccm_reg *const ccm =
55*4882a593Smuzhiyun (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun /* uart clock source is apb2 */
58*4882a593Smuzhiyun writel(APB2_CLK_SRC_OSC24M|
59*4882a593Smuzhiyun APB2_CLK_RATE_N_1|
60*4882a593Smuzhiyun APB2_CLK_RATE_M(1),
61*4882a593Smuzhiyun &ccm->apb2_div);
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun /* open the clock for uart */
64*4882a593Smuzhiyun setbits_le32(&ccm->apb2_gate,
65*4882a593Smuzhiyun CLK_GATE_OPEN << (APB2_GATE_UART_SHIFT +
66*4882a593Smuzhiyun CONFIG_CONS_INDEX - 1));
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun /* deassert uart reset */
69*4882a593Smuzhiyun setbits_le32(&ccm->apb2_reset_cfg,
70*4882a593Smuzhiyun 1 << (APB2_RESET_UART_SHIFT +
71*4882a593Smuzhiyun CONFIG_CONS_INDEX - 1));
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun #ifdef CONFIG_SPL_BUILD
clock_set_pll1(unsigned int clk)75*4882a593Smuzhiyun void clock_set_pll1(unsigned int clk)
76*4882a593Smuzhiyun {
77*4882a593Smuzhiyun struct sunxi_ccm_reg * const ccm =
78*4882a593Smuzhiyun (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
79*4882a593Smuzhiyun const int p = 0;
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun /* Switch to 24MHz clock while changing PLL1 */
82*4882a593Smuzhiyun writel(AXI_DIV_2 << AXI0_DIV_SHIFT |
83*4882a593Smuzhiyun AXI_DIV_2 << AXI1_DIV_SHIFT |
84*4882a593Smuzhiyun CPU_CLK_SRC_OSC24M << C0_CPUX_CLK_SRC_SHIFT |
85*4882a593Smuzhiyun CPU_CLK_SRC_OSC24M << C1_CPUX_CLK_SRC_SHIFT,
86*4882a593Smuzhiyun &ccm->cpu_axi_cfg);
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun /* clk = 24*n/p, p is ignored if clock is >288MHz */
89*4882a593Smuzhiyun writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) | CMM_PLL1_CLOCK_TIME_2 |
90*4882a593Smuzhiyun CCM_PLL1_CTRL_N(clk / 24000000),
91*4882a593Smuzhiyun &ccm->pll1_c0_cfg);
92*4882a593Smuzhiyun while (!(readl(&ccm->pll_stable_status) & 0x01)) {}
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) | CMM_PLL1_CLOCK_TIME_2 |
95*4882a593Smuzhiyun CCM_PLL1_CTRL_N(clk / (24000000)),
96*4882a593Smuzhiyun &ccm->pll1_c1_cfg);
97*4882a593Smuzhiyun while (!(readl(&ccm->pll_stable_status) & 0x02)) {}
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun /* Switch CPU to PLL1 */
100*4882a593Smuzhiyun writel(AXI_DIV_2 << AXI0_DIV_SHIFT |
101*4882a593Smuzhiyun AXI_DIV_2 << AXI1_DIV_SHIFT |
102*4882a593Smuzhiyun CPU_CLK_SRC_PLL1 << C0_CPUX_CLK_SRC_SHIFT |
103*4882a593Smuzhiyun CPU_CLK_SRC_PLL1 << C1_CPUX_CLK_SRC_SHIFT,
104*4882a593Smuzhiyun &ccm->cpu_axi_cfg);
105*4882a593Smuzhiyun }
106*4882a593Smuzhiyun #endif
107*4882a593Smuzhiyun
clock_set_pll5(unsigned int clk)108*4882a593Smuzhiyun void clock_set_pll5(unsigned int clk)
109*4882a593Smuzhiyun {
110*4882a593Smuzhiyun struct sunxi_ccm_reg * const ccm =
111*4882a593Smuzhiyun (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
112*4882a593Smuzhiyun unsigned int div1 = 0, div2 = 0;
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun /* A83T PLL5 DDR rate = 24000000 * (n+1)/(div1+1)/(div2+1) */
115*4882a593Smuzhiyun writel(CCM_PLL5_CTRL_EN | CCM_PLL5_CTRL_UPD |
116*4882a593Smuzhiyun CCM_PLL5_CTRL_N(clk / (24000000)) |
117*4882a593Smuzhiyun div2 << CCM_PLL5_DIV2_SHIFT |
118*4882a593Smuzhiyun div1 << CCM_PLL5_DIV1_SHIFT, &ccm->pll5_cfg);
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun udelay(5500);
121*4882a593Smuzhiyun }
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun
clock_get_pll6(void)124*4882a593Smuzhiyun unsigned int clock_get_pll6(void)
125*4882a593Smuzhiyun {
126*4882a593Smuzhiyun struct sunxi_ccm_reg *const ccm =
127*4882a593Smuzhiyun (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun uint32_t rval = readl(&ccm->pll6_cfg);
130*4882a593Smuzhiyun int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT);
131*4882a593Smuzhiyun int div1 = ((rval & CCM_PLL6_CTRL_DIV1_MASK) >>
132*4882a593Smuzhiyun CCM_PLL6_CTRL_DIV1_SHIFT) + 1;
133*4882a593Smuzhiyun int div2 = ((rval & CCM_PLL6_CTRL_DIV2_MASK) >>
134*4882a593Smuzhiyun CCM_PLL6_CTRL_DIV2_SHIFT) + 1;
135*4882a593Smuzhiyun return 24000000 * n / div1 / div2;
136*4882a593Smuzhiyun }
137