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/OK3568_Linux_fs/kernel/include/linux/
H A Dclk.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/include/linux/clk.h
7 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
17 struct clk;
22 * DOC: clk notifier callback types
24 * PRE_RATE_CHANGE - called immediately before the clk rate is changed,
32 * the clk will be called with ABORT_RATE_CHANGE. Callbacks must
35 * POST_RATE_CHANGE - called after the clk rate change has successfully
44 * struct clk_notifier - associate a clk with a notifier
45 * @clk: struct clk * to associate the notifier with
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/OK3568_Linux_fs/kernel/drivers/clk/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
6 The <linux/clk.h> calls support software clock gating and
20 Select this option when the clock API in <linux/clk.h> is implemented
23 'struct clk'.
34 clk, useful across many platforms, as well as an
35 implementation of the clock API in include/linux/clk.h.
36 Architectures utilizing the common struct clk should select
55 source "drivers/clk/versatile/Kconfig"
83 These multi-function devices have two fixed-rate oscillators, clocked at 32KHz each.
93 multi-function device has one fixed-rate oscillator, clocked
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/OK3568_Linux_fs/u-boot/drivers/clk/
H A DKconfig3 config CLK config
11 choose the source for each clock.
15 depends on CLK && SPL && SPL_DM
21 used as U-Boot proper.
25 depends on CLK && TPL_DM
31 used as U-Boot proper.
35 depends on CLK && ARCH_BMIPS
43 depends on CLK
51 depends on CLK && ARCH_ZYNQ
80 source "drivers/clk/tegra/Kconfig"
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/OK3568_Linux_fs/u-boot/arch/arm/mach-tegra/tegra114/
H A Dclock.c2 * (C) Copyright 2010-2015
5 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/arch-tegra/clk_rst.h>
16 #include <asm/arch-tegra/timer.h>
21 * Clock types that we can use as a source. The Tegra114 has muxes for the
23 * source. This gives us a clock 'type' and exploits what commonality exists
48 CLOCK_TYPE_NONE = -1, /* invalid clock type */
52 CLOCK_MAX_MUX = 8 /* number of source options for each clock */
56 * Clock source mux for each clock type. This just converts our enum into
60 * The extra column in each clock source array is used to store the mask
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/OK3568_Linux_fs/u-boot/arch/arm/mach-tegra/tegra30/
H A Dclock.c2 * (C) Copyright 2010-2015
5 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/arch-tegra/clk_rst.h>
16 #include <asm/arch-tegra/timer.h>
21 * Clock types that we can use as a source. The Tegra30 has muxes for the
23 * source. This gives us a clock 'type' and exploits what commonality exists
48 CLOCK_TYPE_NONE = -1, /* invalid clock type */
52 CLOCK_MAX_MUX = 8 /* number of source options for each clock */
56 * Clock source mux for each clock type. This just converts our enum into
60 * The extra column in each clock source array is used to store the mask
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/OK3568_Linux_fs/u-boot/arch/arm/mach-tegra/tegra124/
H A Dclock.c2 * (C) Copyright 2013-2015
5 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/arch-tegra/clk_rst.h>
16 #include <asm/arch-tegra/timer.h>
21 * Clock types that we can use as a source. The Tegra124 has muxes for the
23 * source. This gives us a clock 'type' and exploits what commonality exists
50 CLOCK_TYPE_PC2CC3M_T16, /* PC2CC3M_T, but w/16-bit divisor (I2C) */
58 CLOCK_TYPE_NONE = -1, /* invalid clock type */
62 CLOCK_MAX_MUX = 8 /* number of source options for each clock */
66 * Clock source mux for each clock type. This just converts our enum into
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/OK3568_Linux_fs/u-boot/arch/arm/mach-tegra/tegra20/
H A Dclock.c3 * (C) Copyright 2010-2015
6 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm/arch-tegra/clk_rst.h>
17 #include <asm/arch-tegra/timer.h>
22 * Clock types that we can use as a source. The Tegra20 has muxes for the
24 * source. This gives us a clock 'type' and exploits what commonality exists
41 CLOCK_TYPE_PCMT16, /* CLOCK_TYPE_PCMT with 16-bit divider */
46 CLOCK_TYPE_NONE = -1, /* invalid clock type */
50 CLOCK_MAX_MUX = 4 /* number of source options for each clock */
54 * Clock source mux for each clock type. This just converts our enum into
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/OK3568_Linux_fs/kernel/drivers/cpufreq/
H A Dspear-cpufreq.c2 * drivers/cpufreq/spear-cpufreq.c
16 #include <linux/clk.h>
28 struct clk *clk; member
34 static struct clk *spear1340_cpu_get_possible_parent(unsigned long newfreq) in spear1340_cpu_get_possible_parent()
36 struct clk *sys_pclk; in spear1340_cpu_get_possible_parent()
39 * In SPEAr1340, cpu clk's parent sys clk can take input from in spear1340_cpu_get_possible_parent()
50 * As sys clk can have multiple source with their own range in spear1340_cpu_get_possible_parent()
60 return ERR_PTR(-EINVAL); in spear1340_cpu_get_possible_parent()
72 * access a source clock (clk) which might not be ancestor of cpu at present.
73 * Hence in SPEAr1340 we would operate on source clock directly before switching
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H A Dtegra124-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/clk.h>
21 struct clk *cpu_clk;
22 struct clk *pllp_clk;
23 struct clk *pllx_clk;
24 struct clk *dfll_clk;
30 struct clk *orig_parent; in tegra124_cpu_switch_to_dfll()
33 ret = clk_set_rate(priv->dfll_clk, clk_get_rate(priv->cpu_clk)); in tegra124_cpu_switch_to_dfll()
37 orig_parent = clk_get_parent(priv->cpu_clk); in tegra124_cpu_switch_to_dfll()
38 clk_set_parent(priv->cpu_clk, priv->pllp_clk); in tegra124_cpu_switch_to_dfll()
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/OK3568_Linux_fs/kernel/drivers/clk/tegra/
H A Dclk-super.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/clk-provider.h>
13 #include "clk.h"
28 #define super_state_to_src_shift(m, s) ((m->width * s))
29 #define super_state_to_src_mask(m) (((1 << m->width) - 1))
38 u8 source, shift; in clk_super_get_parent() local
40 val = readl_relaxed(mux->reg); in clk_super_get_parent()
50 source = (val >> shift) & super_state_to_src_mask(mux); in clk_super_get_parent()
54 * PLLX/2 is the input source to CCLKLP. in clk_super_get_parent()
56 if ((mux->flags & TEGRA_DIVIDER_2) && !(val & SUPER_LP_DIV2_BYPASS) && in clk_super_get_parent()
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H A Dclk-tegra210-emc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved.
7 #include <linux/clk.h>
8 #include <linux/clk-provider.h>
9 #include <linux/clk/tegra.h>
15 #include "clk.h"
37 struct clk *parents[8];
57 value = readl_relaxed(emc->regs + CLK_SOURCE_EMC); in tegra210_clk_emc_get_parent()
71 * ->set_rate(), so the parent rate passed in here was cached from the in tegra210_clk_emc_recalc_rate()
72 * parent before the ->set_rate() call. in tegra210_clk_emc_recalc_rate()
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H A Dclk-tegra124-emc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/clk/tegra/clk-emc.c
11 #include <linux/clk-provider.h>
12 #include <linux/clk.h>
26 #include "clk.h"
48 * clock source as the current parent, we must first change to a backup
49 * timing that has a different clock source.
67 struct clk *parent;
74 struct clk *prev_parent;
101 val = readl(tegra->clk_regs + CLK_SOURCE_EMC); in emc_recalc_rate()
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/OK3568_Linux_fs/u-boot/arch/arm/mach-tegra/tegra210/
H A Dclock.c2 * (C) Copyright 2013-2015
5 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm/arch-tegra/clk_rst.h>
17 #include <asm/arch-tegra/timer.h>
22 * Clock types that we can use as a source. The Tegra210 has muxes for the
24 * source. This gives us a clock 'type' and exploits what commonality exists
51 CLOCK_TYPE_PC2CC3M_T16, /* PC2CC3M_T, but w/16-bit divisor (I2C) */
60 CLOCK_TYPE_NONE = -1, /* invalid clock type */
64 CLOCK_MAX_MUX = 8 /* number of source options for each clock */
68 * Clock source mux for each clock type. This just converts our enum into
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/OK3568_Linux_fs/kernel/drivers/net/can/mscan/
H A Dmpc5xxx_can.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2004-2005 Andrey Volkov <avolkov@varma-el.com>,
7 * Copyright (C) 2008-2009 Wolfgang Grandegger <wg@grandegger.com>
19 #include <linux/clk.h>
36 { .compatible = "fsl,mpc5200-cdm", },
53 * (IP_CLK) can be selected as MSCAN clock source. According to in mpc52xx_can_get_clock()
64 freq = mpc5xxx_get_bus_frequency(ofdev->dev.of_node); in mpc52xx_can_get_clock()
74 dev_err(&ofdev->dev, "can't get clock node!\n"); in mpc52xx_can_get_clock()
80 dev_err(&ofdev->dev, "can't map clock node!\n"); in mpc52xx_can_get_clock()
84 if (in_8(&cdm->ipb_clk_sel) & 0x1) in mpc52xx_can_get_clock()
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/OK3568_Linux_fs/kernel/drivers/clk/renesas/
H A Dr9a06g032-clocks.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/clk.h>
11 #include <linux/clk-provider.h>
24 #include <dt-bindings/clock/r9a06g032-sysctrl.h>
37 uint32_t source : 8; /* source index + 1 (0 == none) */ member
46 /* For fixed-factor ones */
66 .source = 1 + R9A06G032_##_src, .name = _n, \
70 .source = 1 + R9A06G032_##_src, .name = _n, \
77 .source = 1 + R9A06G032_##_src, .name = _n, \
81 .source = 1 + R9A06G032_##_src, .name = _n, \
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/OK3568_Linux_fs/kernel/drivers/clocksource/
H A Dtimer-nps.c7 * COPYING in the main directory of this source tree, or the
10 * Redistribution and use in source and binary forms, with or
14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
36 #include <linux/clk.h>
51 struct clk **clk) in nps_get_timer_clk() argument
55 *clk = of_clk_get(node, 0); in nps_get_timer_clk()
56 ret = PTR_ERR_OR_ZERO(*clk); in nps_get_timer_clk()
58 pr_err("timer missing clk\n"); in nps_get_timer_clk()
62 ret = clk_prepare_enable(*clk); in nps_get_timer_clk()
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H A Dtimer-fsl-ftm.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 #include <linux/clk.h>
34 if (priv->big_endian) in ftm_readl()
42 if (priv->big_endian) in ftm_writel()
52 /* select and enable counter clock source */ in ftm_counter_enable()
55 val |= priv->ps | FTM_SC_CLK(1); in ftm_counter_enable()
63 /* disable counter clock source */ in ftm_counter_disable()
108 return ftm_readl(priv->clksrc_base + FTM_CNT); in ftm_read_sched_clock()
119 * a, the counter source clock is diabled. in ftm_set_next_event()
121 ftm_counter_disable(priv->clkevt_base); in ftm_set_next_event()
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/OK3568_Linux_fs/kernel/drivers/mmc/host/
H A Dsdhci-s3c.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* linux/drivers/mmc/host/sdhci-s3c.c
14 #include <linux/dma-mapping.h>
16 #include <linux/platform_data/mmc-sdhci-s3c.h>
18 #include <linux/clk.h>
104 * struct sdhci_s3c - S3C SDHCI instance
114 * @no_divider: No or non-standard internal clock divider.
124 struct clk *clk_io;
125 struct clk *clk_bus[MAX_BUS_CLK];
132 * struct sdhci_s3c_driver_data - S3C SDHCI platform specific driver data
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/OK3568_Linux_fs/u-boot/arch/arm/mach-imx/mx7ulp/
H A Dpcc.c4 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/imx-regs.h>
84 int pcc_clock_enable(enum pcc_clk clk, bool enable) in pcc_clock_enable() argument
88 if (clk >= ARRAY_SIZE(pcc_arrays)) in pcc_clock_enable()
89 return -EINVAL; in pcc_clock_enable()
91 reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4; in pcc_clock_enable()
95 clk_debug("pcc_clock_enable: clk %d, reg 0x%x, val 0x%x, enable %d\n", in pcc_clock_enable()
96 clk, reg, val, enable); in pcc_clock_enable()
99 return -EPERM; in pcc_clock_enable()
113 /* The clock source select needs clock is disabled */
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H A Dscg.c4 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/imx-regs.h>
25 reg = readl(&scg1_regs->sosccsr); in scg_src_get_rate()
31 reg = readl(&scg1_regs->firccsr); in scg_src_get_rate()
37 reg = readl(&scg1_regs->sirccsr); in scg_src_get_rate()
43 reg = readl(&scg1_regs->rtccsr); in scg_src_get_rate()
55 static u32 scg_sircdiv_get_rate(enum scg_clk clk) in scg_sircdiv_get_rate() argument
60 switch (clk) { in scg_sircdiv_get_rate()
77 reg = readl(&scg1_regs->sirccsr); in scg_sircdiv_get_rate()
81 reg = readl(&scg1_regs->sircdiv); in scg_sircdiv_get_rate()
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/OK3568_Linux_fs/kernel/drivers/pwm/
H A Dpwm-tegra.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * drivers/pwm/pwm-tegra.c
5 * Tegra pulse-width-modulation controller driver
7 * Copyright (c) 2010-2020, NVIDIA Corporation.
8 * Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer <s.hauer@pengutronix.de>
11 * 1. 13-bit: Frequency division (SCALE)
12 * 2. 8-bit : Pulse division (DUTY)
13 * 3. 1-bit : Enable bit
18 * achieved is (max rate of source clock) / 256.
19 * e.g. if source clock rate is 408 MHz, maximum output frequency can be:
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/OK3568_Linux_fs/kernel/drivers/media/platform/rockchip/ispp/
H A Ddev.c1 // SPDX-License-Identifier: GPL-2.0
4 #include <linux/clk.h>
17 #include <media/videobuf2-dma-contig.h>
18 #include <media/v4l2-fwnode.h>
28 MODULE_PARM_DESC(debug, "Debug level (0-3)");
32 MODULE_PARM_DESC(clk_dbg, "rkispp clk set by user");
40 MODULE_PARM_DESC(mode, "isp->ispp mode: bit0 fbc, bit1 yuv422, bit2 quick");
71 void rkispp_set_clk_rate(struct clk *clk, unsigned long rate) in rkispp_set_clk_rate() argument
76 clk_set_rate(clk, rate); in rkispp_set_clk_rate()
81 struct device *dev = ispp_dev->dev; in get_remote_node_dev()
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/OK3568_Linux_fs/u-boot/drivers/clk/rockchip/
H A Dclk_rk3308.c4 * SPDX-License-Identifier: GPL-2.0
8 #include <clk-uclass.h>
18 #include <dt-bindings/clock/rk3308-cru.h>
89 * (1 << 8) - 1, (1 << 5) - 1, &n, &d);
139 struct rk3308_cru *cru = priv->cru; in rk3308_armclk_set_clk()
146 return -EINVAL; in rk3308_armclk_set_clk()
150 * select apll as cpu/core clock pll source and in rk3308_armclk_set_clk()
155 priv->cru, APLL); in rk3308_armclk_set_clk()
158 priv->cru, APLL, hz)) in rk3308_armclk_set_clk()
159 return -EINVAL; in rk3308_armclk_set_clk()
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H A Dclk_rk1808.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <clk-uclass.h>
12 #include <clk.h>
18 #include <dt-bindings/clock/rk1808-cru.h>
97 struct rk1808_cru *cru = priv->cru; in rk1808_i2c_get_clk()
102 con = readl(&cru->pmu_clksel_con[7]); in rk1808_i2c_get_clk()
106 con = readl(&cru->clksel_con[59]); in rk1808_i2c_get_clk()
110 con = readl(&cru->clksel_con[59]); in rk1808_i2c_get_clk()
114 con = readl(&cru->clksel_con[60]); in rk1808_i2c_get_clk()
118 con = readl(&cru->clksel_con[71]); in rk1808_i2c_get_clk()
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/OK3568_Linux_fs/kernel/drivers/watchdog/
H A Ddavinci_wdt.c1 // SPDX-License-Identifier: GPL-2.0
7 * Copyright (C) 2006-2013 Texas Instruments.
21 #include <linux/clk.h>
24 #define MODULE_NAME "DAVINCI-WDT: "
60 * @base - base io address of WD device
61 * @clk - source clock of WDT
62 * @wdd - hold watchdog device as is in WDT core
66 struct clk *clk; member
77 wdt_freq = clk_get_rate(davinci_wdt->clk); in davinci_wdt_start()
79 /* disable, internal clock source */ in davinci_wdt_start()
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