Lines Matching +full:clk +full:- +full:source
2 * (C) Copyright 2010-2015
5 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/arch-tegra/clk_rst.h>
16 #include <asm/arch-tegra/timer.h>
21 * Clock types that we can use as a source. The Tegra30 has muxes for the
23 * source. This gives us a clock 'type' and exploits what commonality exists
48 CLOCK_TYPE_NONE = -1, /* invalid clock type */
52 CLOCK_MAX_MUX = 8 /* number of source options for each clock */
56 * Clock source mux for each clock type. This just converts our enum into
60 * The extra column in each clock source array is used to store the mask
61 * bits in its register for the source.
63 #define CLK(x) CLOCK_ID_ ## x macro
65 { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC),
66 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
68 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO),
69 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
71 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
72 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
74 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE),
75 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
77 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
78 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
80 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
81 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
83 { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC),
84 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
86 { CLK(AUDIO), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
87 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
89 { CLK(AUDIO), CLK(SFROM32KHZ), CLK(PERIPH), CLK(OSC),
90 CLK(EPCI), CLK(NONE), CLK(NONE), CLK(NONE),
92 { CLK(PERIPH), CLK(MEMORY), CLK(DISPLAY), CLK(AUDIO),
93 CLK(CGENERAL), CLK(DISPLAY2), CLK(OSC), CLK(NONE),
95 { CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC),
96 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
101 * Clock type for each peripheral clock source. We put the name in each
142 TYPE(PERIPHC_MIPI, CLOCK_TYPE_PCMT), /* MIPI base-band HSI */
176 /* 0x38h */ /* Jumps to reg offset 0x3B0h - new for T30 */
221 * SPDIF - which is both 0x08 and 0x0c
224 #define NONE(name) (-1)
449 reg = readl(&clkrst->crc_osc_ctrl); in clock_get_osc_freq()
458 /* Returns a pointer to the clock source register for a peripheral */
467 return &clkrst->crc_clk_src[PERIPH_ID_CSI+1]; in get_periph_source_reg()
471 assert(internal_id != -1); in get_periph_source_reg()
473 internal_id -= PERIPHC_VW_FIRST; in get_periph_source_reg()
474 return &clkrst->crc_clk_src_vw[internal_id]; in get_periph_source_reg()
476 return &clkrst->crc_clk_src[internal_id]; in get_periph_source_reg()
485 return -1; in get_periph_clock_info()
489 return -1; in get_periph_clock_info()
493 return -1; in get_periph_clock_info()
505 enum clock_id get_periph_clock_id(enum periph_id periph_id, int source) in get_periph_clock_id() argument
521 return clock_source[type][source]; in get_periph_clock_id()
525 * Given a peripheral ID and the required source clock, this returns which
526 * value should be programmed into the source mux for that peripheral.
528 * There is special code here to handle the one source type with 5 sources.
531 * @param source PLL id of required parent clock
534 * @return mux value (0-4, or -1 if not found)
552 return -1; in get_periph_clock_source()
559 u32 *clk; in clock_set_enable() local
565 clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)]; in clock_set_enable()
567 clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)]; in clock_set_enable()
568 reg = readl(clk); in clock_set_enable()
573 writel(reg, clk); in clock_set_enable()
586 reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)]; in reset_set_enable()
588 reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)]; in reset_set_enable()
696 } while (--timeout); in tegra_plle_train()
700 return -ETIMEDOUT; in tegra_plle_train()
772 } while (--timeout); in tegra_plle_enable()
776 return -ETIMEDOUT; in tegra_plle_enable()
819 { -1, },