4  * SPDX-License-Identifier:	GPL-2.0+
11 #include <asm/arch/imx-regs.h>
84 int pcc_clock_enable(enum pcc_clk clk, bool enable)  in pcc_clock_enable()  argument
88 	if (clk >= ARRAY_SIZE(pcc_arrays))  in pcc_clock_enable()
89 		return -EINVAL;  in pcc_clock_enable()
91 	reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4;  in pcc_clock_enable()
95 	clk_debug("pcc_clock_enable: clk %d, reg 0x%x, val 0x%x, enable %d\n",  in pcc_clock_enable()
96 		  clk, reg, val, enable);  in pcc_clock_enable()
99 		return -EPERM;  in pcc_clock_enable()
113 /* The clock source select needs clock is disabled */
114 int pcc_clock_sel(enum pcc_clk clk, enum scg_clk src)  in pcc_clock_sel()  argument
118 	if (clk >= ARRAY_SIZE(pcc_arrays))  in pcc_clock_sel()
119 		return -EINVAL;  in pcc_clock_sel()
121 	clksrc_type = pcc_arrays[clk].clksrc;  in pcc_clock_sel()
124 		       clk, clksrc_type);  in pcc_clock_sel()
125 		return -EPERM;  in pcc_clock_sel()
136 		printf("Not find the parent scg_clk in PCS of PCC %d, invalid scg_clk %d\n", clk, src);  in pcc_clock_sel()
137 		return -EINVAL;  in pcc_clock_sel()
140 	reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4;  in pcc_clock_sel()
144 	clk_debug("pcc_clock_sel: clk %d, reg 0x%x, val 0x%x, clksrc_type %d\n",  in pcc_clock_sel()
145 		  clk, reg, val, clksrc_type);  in pcc_clock_sel()
149 		printf("Not permit to select clock source val = 0x%x\n", val);  in pcc_clock_sel()
150 		return -EPERM;  in pcc_clock_sel()
163 int pcc_clock_div_config(enum pcc_clk clk, bool frac, u8 div)  in pcc_clock_div_config()  argument
167 	if (clk >= ARRAY_SIZE(pcc_arrays) || div > 8 ||  in pcc_clock_div_config()
169 		return -EINVAL;  in pcc_clock_div_config()
171 	if (pcc_arrays[clk].div >= PCC_NO_DIV) {  in pcc_clock_div_config()
172 		printf("No DIV/FRAC field for the PCC %d\n", clk);  in pcc_clock_div_config()
173 		return -EPERM;  in pcc_clock_div_config()
176 	reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4;  in pcc_clock_div_config()
183 		return -EPERM;  in pcc_clock_div_config()
192 	val |= (div - 1) & PCC_PCD_MASK;  in pcc_clock_div_config()
199 bool pcc_clock_is_enable(enum pcc_clk clk)  in pcc_clock_is_enable()  argument
203 	if (clk >= ARRAY_SIZE(pcc_arrays))  in pcc_clock_is_enable()
204 		return -EINVAL;  in pcc_clock_is_enable()
206 	reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4;  in pcc_clock_is_enable()
215 int pcc_clock_get_clksrc(enum pcc_clk clk, enum scg_clk *src)  in pcc_clock_get_clksrc()  argument
219 	if (clk >= ARRAY_SIZE(pcc_arrays))  in pcc_clock_get_clksrc()
220 		return -EINVAL;  in pcc_clock_get_clksrc()
222 	clksrc_type = pcc_arrays[clk].clksrc;  in pcc_clock_get_clksrc()
225 		       clk, clksrc_type);  in pcc_clock_get_clksrc()
226 		return -EPERM;  in pcc_clock_get_clksrc()
229 	reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4;  in pcc_clock_get_clksrc()
233 	clk_debug("pcc_clock_get_clksrc: clk %d, reg 0x%x, val 0x%x, type %d\n",  in pcc_clock_get_clksrc()
234 		  clk, reg, val, clksrc_type);  in pcc_clock_get_clksrc()
238 		return -EPERM;  in pcc_clock_get_clksrc()
245 		printf("Clock source is off\n");  in pcc_clock_get_clksrc()
246 		return -EIO;  in pcc_clock_get_clksrc()
249 	*src = pcc_clksrc[clksrc_type][val - 1];  in pcc_clock_get_clksrc()
251 	clk_debug("pcc_clock_get_clksrc: parent scg clk %d\n", *src);  in pcc_clock_get_clksrc()
256 u32 pcc_clock_get_rate(enum pcc_clk clk)  in pcc_clock_get_rate()  argument
262 	ret = pcc_clock_get_clksrc(clk, &parent);  in pcc_clock_get_rate()
270 	if (pcc_arrays[clk].div == PCC_HAS_DIV) {  in pcc_clock_get_rate()
271 		reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4;  in pcc_clock_get_rate()