Lines Matching +full:clk +full:- +full:source
2 * (C) Copyright 2013-2015
5 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm/arch-tegra/clk_rst.h>
17 #include <asm/arch-tegra/timer.h>
22 * Clock types that we can use as a source. The Tegra210 has muxes for the
24 * source. This gives us a clock 'type' and exploits what commonality exists
51 CLOCK_TYPE_PC2CC3M_T16, /* PC2CC3M_T, but w/16-bit divisor (I2C) */
60 CLOCK_TYPE_NONE = -1, /* invalid clock type */
64 CLOCK_MAX_MUX = 8 /* number of source options for each clock */
68 * Clock source mux for each clock type. This just converts our enum into
72 * The extra column in each clock source array is used to store the mask
73 * bits in its register for the source.
75 #define CLK(x) CLOCK_ID_ ## x macro
77 { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC),
78 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
80 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO),
81 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
83 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
84 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
86 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE),
87 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
89 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
90 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
92 { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC),
93 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
95 { CLK(AUDIO), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
96 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
98 { CLK(AUDIO), CLK(SFROM32KHZ), CLK(PERIPH), CLK(OSC),
99 CLK(EPCI), CLK(NONE), CLK(NONE), CLK(NONE),
101 { CLK(PERIPH), CLK(MEMORY), CLK(DISPLAY), CLK(AUDIO),
102 CLK(CGENERAL), CLK(DISPLAY2), CLK(OSC), CLK(NONE),
104 { CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC),
105 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
108 { CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
109 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
114 { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
115 CLK(MEMORY), CLK(NONE), CLK(NONE), CLK(NONE),
118 { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
119 CLK(SFROM32KHZ), CLK(NONE), CLK(OSC), CLK(NONE),
122 { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
123 CLK(MEMORY), CLK(NONE), CLK(OSC), CLK(NONE),
125 /* CLOCK_TYPE_PC2CC3M_T, w/16-bit divisor (I2C) */
126 { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
127 CLK(MEMORY), CLK(NONE), CLK(OSC), CLK(NONE),
130 { CLK(MEMORY), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
131 CLK(PERIPH), CLK(NONE), CLK(AUDIO), CLK(NONE),
134 { CLK(MEMORY), CLK(NONE), CLK(NONE), CLK(NONE),
135 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
138 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
139 CLK(MEMORY2), CLK(CGENERAL2), CLK(CGENERAL3), CLK(NONE),
142 { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
143 CLK(OSC), CLK(NONE), CLK(SFROM32KHZ), CLK(NONE),
146 { CLK(AUDIO), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
147 CLK(PERIPH), CLK(NONE), CLK(OSC), CLK(SRC2),
150 { CLK(PERIPH), CLK(CGENERAL_1), CLK(CGENERAL_0), CLK(NONE),
151 CLK(CGENERAL4_2), CLK(CGENERAL4_1), CLK(OSC), CLK(CGENERAL4_0),
156 * Clock type for each peripheral clock source. We put the name in each
351 * SPDIF - which is both 0x08 and 0x0c
354 #define NONE(name) (-1)
598 /* Y: 192 (192 - 223) */
680 reg = readl(&clkrst->crc_osc_ctrl); in clock_get_osc_freq()
699 /* Returns a pointer to the clock source register for a peripheral */
708 return &clkrst->crc_clk_src[PERIPH_ID_CSI+1]; in get_periph_source_reg()
712 assert(internal_id != -1); in get_periph_source_reg()
716 return &clkrst->crc_clk_src[internal_id]; in get_periph_source_reg()
720 internal_id -= PERIPHC_VW_FIRST; in get_periph_source_reg()
721 return &clkrst->crc_clk_src_vw[internal_id]; in get_periph_source_reg()
726 internal_id -= PERIPHC_X_FIRST; in get_periph_source_reg()
727 return &clkrst->crc_clk_src_x[internal_id]; in get_periph_source_reg()
731 internal_id -= PERIPHC_Y_FIRST; in get_periph_source_reg()
732 return &clkrst->crc_clk_src_y[internal_id]; in get_periph_source_reg()
741 return -1; in get_periph_clock_info()
745 return -1; in get_periph_clock_info()
749 return -1; in get_periph_clock_info()
761 enum clock_id get_periph_clock_id(enum periph_id periph_id, int source) in get_periph_clock_id() argument
777 return clock_source[type][source]; in get_periph_clock_id()
781 * Given a peripheral ID and the required source clock, this returns which
782 * value should be programmed into the source mux for that peripheral.
784 * There is special code here to handle the one source type with 5 sources.
787 * @param source PLL id of required parent clock
790 * @return mux value (0-4, or -1 if not found)
808 return -1; in get_periph_clock_source()
815 u32 *clk; in clock_set_enable() local
821 clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)]; in clock_set_enable()
823 clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)]; in clock_set_enable()
825 clk = &clkrst->crc_clk_out_enb_x; in clock_set_enable()
827 clk = &clkrst->crc_clk_out_enb_y; in clock_set_enable()
829 reg = readl(clk); in clock_set_enable()
834 writel(reg, clk); in clock_set_enable()
847 reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)]; in reset_set_enable()
849 reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)]; in reset_set_enable()
851 reset = &clkrst->crc_rst_devices_x; in reset_set_enable()
853 reset = &clkrst->crc_rst_devices_y; in reset_set_enable()
932 * T210 redefines PLLP_OUT2 as PLLP_VCO/DIVP, so do different OUT1-4 setup here.
945 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]); in tegra210_setup_pllp()
949 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]); in tegra210_setup_pllp()
954 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]); in tegra210_setup_pllp()
960 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]); in tegra210_setup_pllp()
1016 clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, in clock_early_init()
1024 clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1], in clock_early_init()
1029 data = (1 << PLLD_ENABLE_CLK) | (1 << pllinfo->lock_ena); in clock_early_init()
1030 writel(data, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc); in clock_early_init()
1039 value = readl(&clkrst->crc_spare_reg0); in clk_m_get_rate()
1058 writel(freq, &sysctr->cntfid0); in arch_timer_init()
1060 val = readl(&sysctr->cntcr); in arch_timer_init()
1062 writel(val, &sysctr->cntcr); in arch_timer_init()
1087 * Recovery Mode or Boot from USB", sub-section "PLLREFE". in tegra_pllref_enable()
1112 return -ETIMEDOUT; in tegra_pllref_enable()
1162 * Recovery Mode or Boot from USB", sub-section "PLLEs". in tegra_plle_enable()
1165 /* 1. Select XTAL as the source */ in tegra_plle_enable()
1214 return -ETIMEDOUT; in tegra_plle_enable()
1281 { -1, },