Lines Matching +full:clk +full:- +full:source
4 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/imx-regs.h>
25 reg = readl(&scg1_regs->sosccsr); in scg_src_get_rate()
31 reg = readl(&scg1_regs->firccsr); in scg_src_get_rate()
37 reg = readl(&scg1_regs->sirccsr); in scg_src_get_rate()
43 reg = readl(&scg1_regs->rtccsr); in scg_src_get_rate()
55 static u32 scg_sircdiv_get_rate(enum scg_clk clk) in scg_sircdiv_get_rate() argument
60 switch (clk) { in scg_sircdiv_get_rate()
77 reg = readl(&scg1_regs->sirccsr); in scg_sircdiv_get_rate()
81 reg = readl(&scg1_regs->sircdiv); in scg_sircdiv_get_rate()
88 rate = rate / (1 << (val - 1)); in scg_sircdiv_get_rate()
93 static u32 scg_fircdiv_get_rate(enum scg_clk clk) in scg_fircdiv_get_rate() argument
98 switch (clk) { in scg_fircdiv_get_rate()
115 reg = readl(&scg1_regs->firccsr); in scg_fircdiv_get_rate()
119 reg = readl(&scg1_regs->fircdiv); in scg_fircdiv_get_rate()
126 rate = rate / (1 << (val - 1)); in scg_fircdiv_get_rate()
131 static u32 scg_soscdiv_get_rate(enum scg_clk clk) in scg_soscdiv_get_rate() argument
136 switch (clk) { in scg_soscdiv_get_rate()
153 reg = readl(&scg1_regs->sosccsr); in scg_soscdiv_get_rate()
157 reg = readl(&scg1_regs->soscdiv); in scg_soscdiv_get_rate()
164 rate = rate / (1 << (val - 1)); in scg_soscdiv_get_rate()
169 static u32 scg_apll_pfd_get_rate(enum scg_clk clk) in scg_apll_pfd_get_rate() argument
174 switch (clk) { in scg_apll_pfd_get_rate()
203 reg = readl(&scg1_regs->apllpfd); in scg_apll_pfd_get_rate()
219 static u32 scg_spll_pfd_get_rate(enum scg_clk clk) in scg_spll_pfd_get_rate() argument
224 switch (clk) { in scg_spll_pfd_get_rate()
253 reg = readl(&scg1_regs->spllpfd); in scg_spll_pfd_get_rate()
273 reg = readl(&scg1_regs->apllcfg); in scg_apll_get_rate()
301 reg = readl(&scg1_regs->spllcfg); in scg_spll_get_rate()
336 reg = readl(&scg1_regs->ddrccr); in scg_ddr_get_rate()
344 reg = readl(&scg1_regs->apllcfg); in scg_ddr_get_rate()
352 rate = rate / (1 << (div - 1)); in scg_ddr_get_rate()
356 static u32 scg_nic_get_rate(enum scg_clk clk) in scg_nic_get_rate() argument
361 reg = readl(&scg1_regs->niccsr); in scg_nic_get_rate()
379 switch (clk) { in scg_nic_get_rate()
401 switch (clk) { in scg_nic_get_rate()
429 static u32 scg_sys_get_rate(enum scg_clk clk) in scg_sys_get_rate() argument
433 if (clk != SCG_CORE_CLK && clk != SCG_BUS_CLK) in scg_sys_get_rate()
436 reg = readl(&scg1_regs->csr); in scg_sys_get_rate()
464 if (clk == SCG_BUS_CLK) { in scg_sys_get_rate()
483 reg = readl(&scg1_regs->spllcsr); in decode_pll()
488 reg = readl(&scg1_regs->spllcfg); in decode_pll()
504 num = readl(&scg1_regs->spllnum); in decode_pll()
505 denom = readl(&scg1_regs->splldenom); in decode_pll()
512 reg = readl(&scg1_regs->apllcsr); in decode_pll()
517 reg = readl(&scg1_regs->apllcfg); in decode_pll()
533 num = readl(&scg1_regs->apllnum); in decode_pll()
534 denom = readl(&scg1_regs->aplldenom); in decode_pll()
541 reg = readl(&scg1_regs->upllcsr); in decode_pll()
558 u32 scg_clk_get_rate(enum scg_clk clk) in scg_clk_get_rate() argument
560 switch (clk) { in scg_clk_get_rate()
564 return scg_sircdiv_get_rate(clk); in scg_clk_get_rate()
569 return scg_fircdiv_get_rate(clk); in scg_clk_get_rate()
574 return scg_soscdiv_get_rate(clk); in scg_clk_get_rate()
578 return scg_sys_get_rate(clk); in scg_clk_get_rate()
584 return scg_spll_pfd_get_rate(clk); in scg_clk_get_rate()
590 return scg_apll_pfd_get_rate(clk); in scg_clk_get_rate()
600 return scg_nic_get_rate(clk); in scg_clk_get_rate()
612 return scg_src_get_rate(clk); in scg_clk_get_rate()
618 int scg_enable_pll_pfd(enum scg_clk clk, u32 frac) in scg_enable_pll_pfd() argument
625 return -EINVAL; in scg_enable_pll_pfd()
627 switch (clk) { in scg_enable_pll_pfd()
635 if (clk == SCG_SPLL_PFD0_CLK) in scg_enable_pll_pfd()
636 addr = (u32)(&scg1_regs->spllpfd); in scg_enable_pll_pfd()
638 addr = (u32)(&scg1_regs->apllpfd); in scg_enable_pll_pfd()
647 if (clk == SCG_SPLL_PFD1_CLK) in scg_enable_pll_pfd()
648 addr = (u32)(&scg1_regs->spllpfd); in scg_enable_pll_pfd()
650 addr = (u32)(&scg1_regs->apllpfd); in scg_enable_pll_pfd()
659 if (clk == SCG_SPLL_PFD2_CLK) in scg_enable_pll_pfd()
660 addr = (u32)(&scg1_regs->spllpfd); in scg_enable_pll_pfd()
662 addr = (u32)(&scg1_regs->apllpfd); in scg_enable_pll_pfd()
671 if (clk == SCG_SPLL_PFD3_CLK) in scg_enable_pll_pfd()
672 addr = (u32)(&scg1_regs->spllpfd); in scg_enable_pll_pfd()
674 addr = (u32)(&scg1_regs->apllpfd); in scg_enable_pll_pfd()
677 return -EINVAL; in scg_enable_pll_pfd()
691 * Un-gate the PFD in scg_enable_pll_pfd()
692 * (Need un-gate before checking valid, not align with RM) in scg_enable_pll_pfd()
717 return -EPERM; in scg_enable_usb_pll()
726 if (!(readl(&usbphy->usb1_pll_480_ctrl) & PLL_USB_LOCK_MASK)) { in scg_enable_usb_pll()
727 writel(0x1c00000, &usbphy->usb1_pll_480_ctrl_clr); in scg_enable_usb_pll()
731 writel(0xc00000, &usbphy->usb1_pll_480_ctrl_set); in scg_enable_usb_pll()
735 writel(0x800000, &usbphy->usb1_pll_480_ctrl_set); in scg_enable_usb_pll()
739 writel(0x1400000, &usbphy->usb1_pll_480_ctrl_set); in scg_enable_usb_pll()
743 writel(0xc00000, &usbphy->usb1_pll_480_ctrl_set); in scg_enable_usb_pll()
749 &usbphy->usb1_pll_480_ctrl_set); in scg_enable_usb_pll()
755 writel(PLL_USB_PWR_MASK, &usbphy->usb1_pll_480_ctrl_set); in scg_enable_usb_pll()
758 while (timeout--) { in scg_enable_usb_pll()
759 if (readl(&usbphy->usb1_pll_480_ctrl) & in scg_enable_usb_pll()
767 &usbphy->usb1_pll_480_ctrl_clr); in scg_enable_usb_pll()
768 return -ETIME; in scg_enable_usb_pll()
773 writel(PLL_USB_BYPASS_MASK, &usbphy->usb1_pll_480_ctrl_clr); in scg_enable_usb_pll()
777 &usbphy->usb1_pll_480_ctrl_set); in scg_enable_usb_pll()
780 while (timeout--) { in scg_enable_usb_pll()
781 if (readl(&scg1_regs->upllcsr) & in scg_enable_usb_pll()
790 return -ETIME; in scg_enable_usb_pll()
798 /* A7 domain system clock source is SPLL */
813 rccr_reg_val = readl(&scg1_regs->rccr); in scg_a7_rccr_init()
818 writel(rccr_reg_val, &scg1_regs->rccr); in scg_a7_rccr_init()
837 /* Clock source is System OSC */
855 val = readl(&scg1_regs->spllcsr); in scg_a7_spll_init()
857 writel(val, &scg1_regs->spllcsr); in scg_a7_spll_init()
869 val = readl(&scg1_regs->spllpfd); in scg_a7_spll_init()
874 writel(val, &scg1_regs->spllpfd); in scg_a7_spll_init()
879 writel(SCG1_SPLL_CFG_NUM_24M_OSC, &scg1_regs->spllcfg); in scg_a7_spll_init()
882 val = readl(&scg1_regs->spllcsr); in scg_a7_spll_init()
884 writel(val, &scg1_regs->spllcsr); in scg_a7_spll_init()
887 while (!(readl(&scg1_regs->spllcsr) & SCG_SPLL_CSR_SPLLVLD_MASK)) in scg_a7_spll_init()
891 val = readl(&scg1_regs->spllpfd); in scg_a7_spll_init()
894 writel(val, &scg1_regs->spllpfd); in scg_a7_spll_init()
896 /* Un-gate A7 SPLL PFD0 */ in scg_a7_spll_init()
897 val = readl(&scg1_regs->spllpfd); in scg_a7_spll_init()
899 writel(val, &scg1_regs->spllpfd); in scg_a7_spll_init()
902 while (!(readl(&scg1_regs->spllpfd) & SCG_PLL_PFD0_VALID_MASK)) in scg_a7_spll_init()
908 /* DDR clock source is APLL PFD0 (396MHz) */
920 writel(SCG1_DDRCCR_CFG_NUM, &scg1_regs->ddrccr); in scg_a7_ddrclk_init()
938 /* Clock source is System OSC <<0 */
944 * APLL clock source is system OSC (24MHz)
964 val = readl(&scg1_regs->apllcsr); in scg_a7_apll_init()
966 writel(val, &scg1_regs->apllcsr); in scg_a7_apll_init()
969 val = readl(&scg1_regs->apllpfd); in scg_a7_apll_init()
971 writel(val, &scg1_regs->apllpfd); in scg_a7_apll_init()
975 writel(SCG1_APLL_CFG_NUM_24M_OSC, &scg1_regs->apllcfg); in scg_a7_apll_init()
978 val = readl(&scg1_regs->apllcsr); in scg_a7_apll_init()
980 writel(val, &scg1_regs->apllcsr); in scg_a7_apll_init()
983 while (!(readl(&scg1_regs->apllcsr) & SCG_APLL_CSR_APLLVLD_MASK)) in scg_a7_apll_init()
987 val = readl(&scg1_regs->apllpfd); in scg_a7_apll_init()
990 writel(val, &scg1_regs->apllpfd); in scg_a7_apll_init()
992 /* Un-gate A7 APLL PFD0 */ in scg_a7_apll_init()
993 val = readl(&scg1_regs->apllpfd); in scg_a7_apll_init()
995 writel(val, &scg1_regs->apllpfd); in scg_a7_apll_init()
998 while (!(readl(&scg1_regs->apllpfd) & SCG_PLL_PFD0_VALID_MASK)) in scg_a7_apll_init()
1013 while (!(readl(&scg1_regs->firccsr) & SCG_FIRC_CSR_FIRCVLD_MASK)) in scg_a7_firc_init()
1019 SCG1_FIRCDIV_DIV1_NUM), &scg1_regs->fircdiv); in scg_a7_firc_init()
1023 /* NIC clock source is DDR clock (396/198MHz) */
1041 writel(SCG1_NICCCR_CFG_NUM, &scg1_regs->nicccr); in scg_a7_nicclk_init()
1055 while (!(readl(&scg1_regs->sosccsr) & SCG_SOSC_CSR_SOSCVLD_MASK)) in scg_a7_soscdiv_init()
1060 SCG1_SOSCDIV_DIV1_NUM), &scg1_regs->soscdiv); in scg_a7_soscdiv_init()
1063 void scg_a7_sys_clk_sel(enum scg_sys_src clk) in scg_a7_sys_clk_sel() argument
1068 clk == SCG_SCS_SYS_OSC ? "SYS_OSC" : in scg_a7_sys_clk_sel()
1069 clk == SCG_SCS_SLOW_IRC ? "SLOW_IRC" : in scg_a7_sys_clk_sel()
1070 clk == SCG_SCS_FAST_IRC ? "FAST_IRC" : in scg_a7_sys_clk_sel()
1071 clk == SCG_SCS_RTC_OSC ? "RTC_OSC" : in scg_a7_sys_clk_sel()
1072 clk == SCG_SCS_AUX_PLL ? "AUX_PLL" : in scg_a7_sys_clk_sel()
1073 clk == SCG_SCS_SYS_PLL ? "SYS_PLL" : in scg_a7_sys_clk_sel()
1074 clk == SCG_SCS_USBPHY_PLL ? "USBPHY_PLL" : in scg_a7_sys_clk_sel()
1075 "Invalid source" in scg_a7_sys_clk_sel()
1078 rccr_reg_val = readl(&scg1_regs->rccr); in scg_a7_sys_clk_sel()
1080 rccr_reg_val |= (clk << SCG_CCR_SCS_SHIFT); in scg_a7_sys_clk_sel()
1081 writel(rccr_reg_val, &scg1_regs->rccr); in scg_a7_sys_clk_sel()
1086 debug("SCG Version: 0x%x\n", readl(&scg1_regs->verid)); in scg_a7_info()
1087 debug("SCG Parameter: 0x%x\n", readl(&scg1_regs->param)); in scg_a7_info()
1088 debug("SCG RCCR Value: 0x%x\n", readl(&scg1_regs->rccr)); in scg_a7_info()
1089 debug("SCG Clock Status: 0x%x\n", readl(&scg1_regs->csr)); in scg_a7_info()