Lines Matching +full:clk +full:- +full:source
2 * (C) Copyright 2013-2015
5 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/arch-tegra/clk_rst.h>
16 #include <asm/arch-tegra/timer.h>
21 * Clock types that we can use as a source. The Tegra124 has muxes for the
23 * source. This gives us a clock 'type' and exploits what commonality exists
50 CLOCK_TYPE_PC2CC3M_T16, /* PC2CC3M_T, but w/16-bit divisor (I2C) */
58 CLOCK_TYPE_NONE = -1, /* invalid clock type */
62 CLOCK_MAX_MUX = 8 /* number of source options for each clock */
66 * Clock source mux for each clock type. This just converts our enum into
70 * The extra column in each clock source array is used to store the mask
71 * bits in its register for the source.
73 #define CLK(x) CLOCK_ID_ ## x macro
75 { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC),
76 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
78 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO),
79 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
81 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
82 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
84 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE),
85 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
87 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
88 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
90 { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC),
91 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
93 { CLK(AUDIO), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
94 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
96 { CLK(AUDIO), CLK(SFROM32KHZ), CLK(PERIPH), CLK(OSC),
97 CLK(EPCI), CLK(NONE), CLK(NONE), CLK(NONE),
99 { CLK(PERIPH), CLK(MEMORY), CLK(DISPLAY), CLK(AUDIO),
100 CLK(CGENERAL), CLK(DISPLAY2), CLK(OSC), CLK(NONE),
102 { CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC),
103 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
106 { CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
107 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
112 { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
113 CLK(MEMORY), CLK(NONE), CLK(NONE), CLK(NONE),
116 { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
117 CLK(SFROM32KHZ), CLK(NONE), CLK(OSC), CLK(NONE),
120 { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
121 CLK(MEMORY), CLK(NONE), CLK(OSC), CLK(NONE),
123 /* CLOCK_TYPE_PC2CC3M_T, w/16-bit divisor (I2C) */
124 { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
125 CLK(MEMORY), CLK(NONE), CLK(OSC), CLK(NONE),
128 { CLK(MEMORY), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
129 CLK(PERIPH), CLK(NONE), CLK(AUDIO), CLK(NONE),
132 { CLK(MEMORY), CLK(NONE), CLK(NONE), CLK(NONE),
133 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
136 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
137 CLK(MEMORY2), CLK(CGENERAL2), CLK(CGENERAL3), CLK(NONE),
140 { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
141 CLK(OSC), CLK(NONE), CLK(SFROM32KHZ), CLK(NONE),
144 { CLK(AUDIO), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
145 CLK(PERIPH), CLK(NONE), CLK(OSC), CLK(SRC2),
150 * Clock type for each peripheral clock source. We put the name in each
321 * SPDIF - which is both 0x08 and 0x0c
324 #define NONE(name) (-1)
611 reg = readl(&clkrst->crc_osc_ctrl); in clock_get_osc_freq()
620 /* Returns a pointer to the clock source register for a peripheral */
629 return &clkrst->crc_clk_src[PERIPH_ID_CSI+1]; in get_periph_source_reg()
633 assert(internal_id != -1); in get_periph_source_reg()
635 internal_id -= PERIPHC_X_FIRST; in get_periph_source_reg()
636 return &clkrst->crc_clk_src_x[internal_id]; in get_periph_source_reg()
638 internal_id -= PERIPHC_VW_FIRST; in get_periph_source_reg()
639 return &clkrst->crc_clk_src_vw[internal_id]; in get_periph_source_reg()
641 return &clkrst->crc_clk_src[internal_id]; in get_periph_source_reg()
651 return -1; in get_periph_clock_info()
655 return -1; in get_periph_clock_info()
659 return -1; in get_periph_clock_info()
671 enum clock_id get_periph_clock_id(enum periph_id periph_id, int source) in get_periph_clock_id() argument
687 return clock_source[type][source]; in get_periph_clock_id()
691 * Given a peripheral ID and the required source clock, this returns which
692 * value should be programmed into the source mux for that peripheral.
694 * There is special code here to handle the one source type with 5 sources.
697 * @param source PLL id of required parent clock
700 * @return mux value (0-4, or -1 if not found)
718 return -1; in get_periph_clock_source()
725 u32 *clk; in clock_set_enable() local
731 clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)]; in clock_set_enable()
733 clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)]; in clock_set_enable()
735 clk = &clkrst->crc_clk_out_enb_x; in clock_set_enable()
736 reg = readl(clk); in clock_set_enable()
741 writel(reg, clk); in clock_set_enable()
754 reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)]; in reset_set_enable()
756 reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)]; in reset_set_enable()
758 reset = &clkrst->crc_rst_devices_x; in reset_set_enable()
846 clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, PLLC_IDDQ); in clock_early_init()
879 writel(0x00561600, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1]); in clock_early_init()
883 setbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, (1 << pllinfo->lock_ena)); in clock_early_init()
888 data = (12 << pllinfo->kcp_shift) | (1 << pllinfo->kvco_shift); in clock_early_init()
889 data |= (1 << PLLD_CLKENABLE) | (1 << pllinfo->lock_ena); in clock_early_init()
890 writel(data, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc); in clock_early_init()
895 * clock_early_init_done - Check if clock_early_init() has been called
907 val = readl(&clkrst->crc_sclk_brst_pol); in clock_early_init_done()
925 writel(freq, &sysctr->cntfid0); in arch_timer_init()
927 val = readl(&sysctr->cntcr); in arch_timer_init()
929 writel(val, &sysctr->cntcr); in arch_timer_init()
1046 /* uses PLLP, has a non-standard bit layout. */ in clock_sor_enable_edp_clock()
1073 int mux_bits, divider_bits, source; in clock_set_display_rate() local
1098 diff = vco - divn * cf; in clock_set_display_rate()
1101 diff = cf - diff; in clock_set_display_rate()
1130 source = get_periph_clock_source(PERIPH_ID_DISP1, CLOCK_ID_DISPLAY, in clock_set_display_rate()
1132 clock_ll_set_source_bits(PERIPH_ID_DISP1, mux_bits, source); in clock_set_display_rate()
1145 writel(value | PLLDP_SS_CFG_CLAMP, &clkrst->crc_plldp_ss_cfg); in clock_set_up_plldp()
1147 writel(value, &clkrst->crc_plldp_ss_cfg); in clock_set_up_plldp()
1156 return &clkrst->plldp; in clock_get_simple_pll()
1181 { -1, },