Home
last modified time | relevance | path

Searched +full:clk +full:- +full:phase +full:- (Results 1 – 25 of 274) sorted by relevance

1234567891011

/OK3568_Linux_fs/kernel/drivers/clk/meson/
H A Dclk-phase.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <linux/clk-provider.h>
10 #include "clk-regmap.h"
11 #include "clk-phase.h"
16 meson_clk_phase_data(struct clk_regmap *clk) in meson_clk_phase_data() argument
18 return (struct meson_clk_phase_data *)clk->data; in meson_clk_phase_data()
39 struct clk_regmap *clk = to_clk_regmap(hw); in meson_clk_phase_get_phase() local
40 struct meson_clk_phase_data *phase = meson_clk_phase_data(clk); in meson_clk_phase_get_phase() local
43 val = meson_parm_read(clk->map, &phase->ph); in meson_clk_phase_get_phase()
45 return meson_clk_degrees_from_val(val, phase->ph.width); in meson_clk_phase_get_phase()
[all …]
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0-only
4 obj-$(CONFIG_COMMON_CLK_MESON_AO_CLKC) += meson-aoclk.o
5 obj-$(CONFIG_COMMON_CLK_MESON_CPU_DYNDIV) += clk-cpu-dyndiv.o
6 obj-$(CONFIG_COMMON_CLK_MESON_DUALDIV) += clk-dualdiv.o
7 obj-$(CONFIG_COMMON_CLK_MESON_EE_CLKC) += meson-eeclk.o
8 obj-$(CONFIG_COMMON_CLK_MESON_MPLL) += clk-mpll.o
9 obj-$(CONFIG_COMMON_CLK_MESON_PHASE) += clk-phase.o
10 obj-$(CONFIG_COMMON_CLK_MESON_PLL) += clk-pll.o
11 obj-$(CONFIG_COMMON_CLK_MESON_REGMAP) += clk-regmap.o
12 obj-$(CONFIG_COMMON_CLK_MESON_SCLK_DIV) += sclk-div.o
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/sunxi/
H A Dclk-mod0.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
15 #include "clk-factors.h"
18 * sun4i_a10_get_mod0_factors() - calculates m, n factors for MOD0-style clocks
29 if (req->rate > req->parent_rate) in sun4i_a10_get_mod0_factors()
30 req->rate = req->parent_rate; in sun4i_a10_get_mod0_factors()
32 div = DIV_ROUND_UP(req->parent_rate, req->rate); in sun4i_a10_get_mod0_factors()
45 req->rate = (req->parent_rate >> calcp) / calcm; in sun4i_a10_get_mod0_factors()
46 req->m = calcm - 1; in sun4i_a10_get_mod0_factors()
[all …]
/OK3568_Linux_fs/kernel/drivers/mmc/host/
H A Dsdhci-sirf.c1 // SPDX-License-Identifier: GPL-2.0-or-later
13 #include <linux/mmc/slot-gpio.h>
14 #include "sdhci-pltfm.h"
29 * 8bit-width enable bit of CSR SD hosts is 3, in sdhci_sirf_set_bus_width()
42 u32 val = readl(host->ioaddr + reg); in sdhci_sirf_readl_le()
45 (host->mmc->caps & MMC_CAP_UHS_SDR50))) { in sdhci_sirf_readl_le()
64 ret = readw(host->ioaddr + reg); in sdhci_sirf_readw_le()
67 ret = readw(host->ioaddr + SDHCI_HOST_VERSION); in sdhci_sirf_readw_le()
77 int phase; in sdhci_sirf_execute_tuning() local
80 int start = -1, end = 0, tuning_value = -1, range = 0; in sdhci_sirf_execute_tuning()
[all …]
H A Dmmci_stm32_sdmmc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
8 #include <linux/dma-mapping.h>
64 for_each_sg(data->sg, sg, data->sg_len - 1, i) { in sdmmc_idma_validate_data()
65 if (!IS_ALIGNED(sg->offset, sizeof(u32)) || in sdmmc_idma_validate_data()
66 !IS_ALIGNED(sg->length, SDMMC_IDMA_BURST)) { in sdmmc_idma_validate_data()
67 dev_err(mmc_dev(host->mmc), in sdmmc_idma_validate_data()
69 data->sg->offset, data->sg->length); in sdmmc_idma_validate_data()
70 return -EINVAL; in sdmmc_idma_validate_data()
74 if (!IS_ALIGNED(sg->offset, sizeof(u32))) { in sdmmc_idma_validate_data()
[all …]
H A Dsdhci-of-arasan.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu>
9 * Based on sdhci-of-esdhc.c
18 #include <linux/clk-provider.h>
25 #include <linux/firmware/xlnx-zynqmp.h>
28 #include "sdhci-cqhci.h"
29 #include "sdhci-pltfm.h"
56 * On some SoCs the syscon area has a feature where the upper 16-bits of
57 * each 32-bit register act as a write mask for the lower 16-bits. This allows
65 * struct sdhci_arasan_soc_ctl_field - Field used in sdhci_arasan_soc_ctl_map
[all …]
H A Dsdhci-msm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/mmc/host/sdhci-msm.c - Qualcomm SDHCI Platform driver
5 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
22 #include "sdhci-pltfm.h"
121 #define INVALID_TUNING_PHASE -1
135 /* Max load for eMMC Vdd-io supply */
139 msm_host->var_ops->msm_readl_relaxed(host, offset)
142 msm_host->var_ops->msm_writel_relaxed(val, host, offset)
263 struct clk *bus_clk; /* SDHC bus voter clock */
264 struct clk *xo_clk; /* TCXO clk needed for FLL feature of cm_dll*/
[all …]
H A Ddw_mmc-rockchip.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 #include <linux/clk.h>
11 #include <linux/mmc/slot-gpio.h>
17 #include "dw_mmc-pltfm.h"
22 struct clk *drv_clk;
23 struct clk *sample_clk;
33 struct dw_mci_rockchip_priv_data *priv = host->priv; in dw_mci_rk3288_set_ios()
38 if (ios->clock == 0) in dw_mci_rk3288_set_ios()
45 * ios->clock = (div == 0) ? bus_hz : (bus_hz / (2 * div)) in dw_mci_rk3288_set_ios()
48 * DDR52 8-bit mode. in dw_mci_rk3288_set_ios()
[all …]
/OK3568_Linux_fs/kernel/include/trace/events/
H A Dclk.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
6 #define TRACE_SYSTEM clk
15 DECLARE_EVENT_CLASS(clk,
22 __string( name, core->name )
26 __assign_str(name, core->name);
32 DEFINE_EVENT(clk, clk_enable,
39 DEFINE_EVENT(clk, clk_enable_complete,
46 DEFINE_EVENT(clk, clk_disable,
53 DEFINE_EVENT(clk, clk_disable_complete,
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/rockchip/
H A Dclk-mmc-phase.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
12 #include "clk.h"
41 * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to
54 /* Constant signal, no measurable phase shift */ in rockchip_mmc_get_phase()
58 raw_value = readl(mmc_clock->reg) >> (mmc_clock->shift); in rockchip_mmc_get_phase()
86 * MMC host to the card, which expects the phase clock inherits in rockchip_mmc_set_phase()
97 pr_err("%s: invalid clk rate\n", __func__); in rockchip_mmc_set_phase()
98 return -EINVAL; in rockchip_mmc_set_phase()
[all …]
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
6 obj-$(CONFIG_COMMON_CLK_ROCKCHIP) += clk-rockchip.o
7 obj-$(CONFIG_COMMON_CLK_ROCKCHIP_REGMAP) += regmap/
9 clk-rockchip-y += clk.o
10 clk-rockchip-y += clk-pll.o
11 clk-rockchip-y += clk-cpu.o
12 clk-rockchip-y += clk-half-divider.o
13 clk-rockchip-y += clk-mmc-phase.o
14 clk-rockchip-y += clk-muxgrf.o
15 clk-rockchip-$(CONFIG_ROCKCHIP_DDRCLK) += clk-ddr.o
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/hisilicon/
H A Dclk-hisi-phase.c1 // SPDX-License-Identifier: GPL-2.0
5 * Simple HiSilicon phase clock implementation.
14 #include "clk.h"
30 static int hisi_phase_regval_to_degrees(struct clk_hisi_phase *phase, in hisi_phase_regval_to_degrees() argument
35 for (i = 0; i < phase->phase_num; i++) in hisi_phase_regval_to_degrees()
36 if (phase->phase_regvals[i] == regval) in hisi_phase_regval_to_degrees()
37 return phase->phase_degrees[i]; in hisi_phase_regval_to_degrees()
39 return -EINVAL; in hisi_phase_regval_to_degrees()
44 struct clk_hisi_phase *phase = to_clk_hisi_phase(hw); in hisi_clk_get_phase() local
47 regval = readl(phase->reg); in hisi_clk_get_phase()
[all …]
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
6 obj-y += clk.o clkgate-separated.o clkdivider-hi6220.o clk-hisi-phase.o
8 obj-$(CONFIG_ARCH_HI3xxx) += clk-hi3620.o
9 obj-$(CONFIG_ARCH_HIP04) += clk-hip04.o
10 obj-$(CONFIG_ARCH_HIX5HD2) += clk-hix5hd2.o
11 obj-$(CONFIG_COMMON_CLK_HI3516CV300) += crg-hi3516cv300.o
12 obj-$(CONFIG_COMMON_CLK_HI3519) += clk-hi3519.o
13 obj-$(CONFIG_COMMON_CLK_HI3660) += clk-hi3660.o
14 obj-$(CONFIG_COMMON_CLK_HI3670) += clk-hi3670.o
15 obj-$(CONFIG_COMMON_CLK_HI3798CV200) += crg-hi3798cv200.o
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/
H A Daltr_socfpga.txt5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "altr,socfpga-pll-clock" - for a PLL clock
10 "altr,socfpga-perip-clock" - The peripheral clock divided from the
12 "altr,socfpga-gate-clk" - Clocks that directly feed peripherals and
15 - reg : shall be the control register offset from CLOCK_MANAGER's base for the clock.
16 - clocks : shall be the input parent clock phandle for the clock. This is
18 - #clock-cells : from common clock binding, shall be set to 0.
21 - fixed-divider : If clocks have a fixed divider value, use this property.
22 - clk-gate : For "socfpga-gate-clk", clk-gate contains the gating register
[all …]
/OK3568_Linux_fs/u-boot/drivers/mmc/
H A Drockchip_dw_mmc.c4 * SPDX-License-Identifier: GPL-2.0+
8 #include <clk.h>
10 #include <dt-structs.h>
32 struct clk clk; member
33 struct clk sample_clk;
48 if (!memcmp(dev->name, "dwmmc", strlen("dwmmc"))) in board_mmc_dm_reinit()
49 return clk_get_by_index(dev, 0, &priv->clk); in board_mmc_dm_reinit()
61 struct udevice *dev = host->priv; in rockchip_dwmmc_get_mmc_clk()
69 if (mmc_card_ddr52(host->mmc) && host->mmc->bus_width == 8) in rockchip_dwmmc_get_mmc_clk()
72 ret = clk_set_rate(&priv->clk, freq); in rockchip_dwmmc_get_mmc_clk()
[all …]
/OK3568_Linux_fs/u-boot/include/
H A Dclk-uclass.h6 * SPDX-License-Identifier: GPL-2.0+
12 /* See clk.h for background documentation. */
14 #include <clk.h>
19 * struct clk_ops - The functions that a clock driver must implement.
23 * of_xlate - Translate a client's device-tree (OF) clock specifier.
29 * default implementation, which assumes #clock-cells = <1>, and that
32 * At present, the clock API solely supports device-tree. If this
40 int (*of_xlate)(struct clk *clock,
43 * request - Request a translated clock.
55 int (*request)(struct clk *clock);
[all …]
H A Dclk.h6 * SPDX-License-Identifier: GPL-2.0+
35 * struct clk - A handle to (allowing control of) a single clock.
54 struct clk { struct
64 * struct clk_bulk - A handle to (allowing control of) a bulk of clocks.
76 struct clk *clks; argument
80 #if CONFIG_IS_ENABLED(OF_CONTROL) && CONFIG_IS_ENABLED(CLK)
83 struct phandle_1_arg *cells, struct clk *clk);
86 * clock_get_by_index - Get/request a clock by integer index.
91 * device clock indices to provider clocks may be via device-tree properties,
92 * board-provided mapping tables, or some other mechanism.
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/
H A Dclk.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
6 * Standard functionality for the common clock API. See Documentation/driver-api/clk.rst
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
11 #include <linux/clk/clk-conf.h>
25 #include "clk.h"
83 int phase; member
97 #include <trace/events/clk.h>
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-sunxi/
H A Ddram_sun4i.c6 * Based on sun4i Linux kernel sources mach-sunxi/pm/standby/dram*.c
7 * and earlier U-Boot Allwiner A10 SPL work
9 * (C) Copyright 2007-2012
14 * SPDX-License-Identifier: GPL-2.0+
69 writel(0, &timer->cpu_cfg); in mctl_ddr3_reset()
70 reg_val = readl(&timer->cpu_cfg); in mctl_ddr3_reset()
74 setbits_le32(&dram->mcr, DRAM_MCR_RESET); in mctl_ddr3_reset()
76 clrbits_le32(&dram->mcr, DRAM_MCR_RESET); in mctl_ddr3_reset()
80 clrbits_le32(&dram->mcr, DRAM_MCR_RESET); in mctl_ddr3_reset()
82 setbits_le32(&dram->mcr, DRAM_MCR_RESET); in mctl_ddr3_reset()
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_dccg.c36 (dccg_dcn->regs->reg)
40 dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name
43 dccg_dcn->base.ctx
45 dccg->ctx->logger
51 if (dccg->ref_dppclk && req_dppclk) { in dccg2_update_dpp_dto()
52 int ref_dppclk = dccg->ref_dppclk; in dccg2_update_dpp_dto()
53 int modulo, phase; in dccg2_update_dpp_dto() local
55 // phase / modulo = dpp pipe clk / dpp global clk in dccg2_update_dpp_dto()
57 phase = ((modulo * req_dppclk) + ref_dppclk - 1) / ref_dppclk; in dccg2_update_dpp_dto()
59 if (phase > 0xff) { in dccg2_update_dpp_dto()
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/spi/
H A Dspi-samsung.txt8 - compatible: should be one of the following.
9 - samsung,s3c2443-spi: for s3c2443, s3c2416 and s3c2450 platforms
10 - samsung,s3c6410-spi: for s3c6410 platforms
11 - samsung,s5pv210-spi: for s5pv210 and s5pc110 platforms
12 - samsung,exynos5433-spi: for exynos5433 compatible controllers
13 - samsung,exynos7-spi: for exynos7 platforms <DEPRECATED>
15 - reg: physical base address of the controller and length of memory mapped
18 - interrupts: The interrupt number to the cpu. The interrupt specifier format
21 - dmas : Two or more DMA channel specifiers following the convention outlined
24 - dma-names: Names for the dma channels. There must be at least one channel
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/iio/frequency/
H A Dadf4350.txt4 - compatible: Should be one of
7 - reg: SPI chip select numbert for the device
8 - spi-max-frequency: Max SPI frequency to use (< 20000000)
9 - clocks: From common clock binding. Clock is phandle to clock for
13 - gpios: GPIO Lock detect - If set with a valid phandle and GPIO number,
15 - adi,channel-spacing: Channel spacing in Hz (influences MODULUS).
16 - adi,power-up-frequency: If set in Hz the PLL tunes to
18 - adi,reference-div-factor: If set the driver skips dynamic calculation
20 - adi,reference-doubler-enable: Enables reference doubler.
21 - adi,reference-div2-enable: Enables reference divider.
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/sunxi-ng/
H A Dccu_phase.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 #include <linux/clk-provider.h>
15 struct ccu_phase *phase = hw_to_ccu_phase(hw); in ccu_phase_get_phase() local
22 reg = readl(phase->common.base + phase->common.reg); in ccu_phase_get_phase()
23 delay = (reg >> phase->shift); in ccu_phase_get_phase()
24 delay &= (1 << phase->width) - 1; in ccu_phase_get_phase()
32 return -EINVAL; in ccu_phase_get_phase()
37 return -EINVAL; in ccu_phase_get_phase()
42 return -EINVAL; in ccu_phase_get_phase()
[all …]
/OK3568_Linux_fs/kernel/include/linux/
H A Dclk.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/include/linux/clk.h
7 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
17 struct clk;
22 * DOC: clk notifier callback types
24 * PRE_RATE_CHANGE - called immediately before the clk rate is changed,
32 * the clk will be called with ABORT_RATE_CHANGE. Callbacks must
35 * POST_RATE_CHANGE - called after the clk rate change has successfully
44 * struct clk_notifier - associate a clk with a notifier
45 * @clk: struct clk * to associate the notifier with
[all …]
/OK3568_Linux_fs/kernel/drivers/scsi/
H A Dinitio.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 1994-1998 Initio Corporation
14 * This is the Linux low-level SCSI driver for Initio INI-9X00U/UW SCSI host
17 * 08/06/97 hc - v1.01h
18 * - Support inic-940 and inic-935
19 * 09/26/97 hc - v1.01i
20 * - Make correction from J.W. Schultz suggestion
21 * 10/13/97 hc - Support reset function
22 * 10/21/97 hc - v1.01j
23 * - Support 32 LUN (SCSI 3)
[all …]

1234567891011