xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/iio/frequency/adf4350.txt (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593SmuzhiyunAnalog Devices ADF4350/ADF4351 device driver
2*4882a593Smuzhiyun
3*4882a593SmuzhiyunRequired properties:
4*4882a593Smuzhiyun	- compatible: Should be one of
5*4882a593Smuzhiyun		* "adi,adf4350": When using the ADF4350 device
6*4882a593Smuzhiyun		* "adi,adf4351": When using the ADF4351 device
7*4882a593Smuzhiyun	- reg: SPI chip select numbert for the device
8*4882a593Smuzhiyun	- spi-max-frequency: Max SPI frequency to use (< 20000000)
9*4882a593Smuzhiyun	- clocks: From common clock binding. Clock is phandle to clock for
10*4882a593Smuzhiyun		ADF435x Reference Clock (CLKIN).
11*4882a593Smuzhiyun
12*4882a593SmuzhiyunOptional properties:
13*4882a593Smuzhiyun	- gpios:	 GPIO Lock detect - If set with a valid phandle and GPIO number,
14*4882a593Smuzhiyun			pll lock state is tested upon read.
15*4882a593Smuzhiyun	- adi,channel-spacing: Channel spacing in Hz (influences MODULUS).
16*4882a593Smuzhiyun	- adi,power-up-frequency:	If set in Hz the PLL tunes to
17*4882a593Smuzhiyun			the desired frequency on probe.
18*4882a593Smuzhiyun	- adi,reference-div-factor: If set the driver skips dynamic calculation
19*4882a593Smuzhiyun			and uses this default value instead.
20*4882a593Smuzhiyun	- adi,reference-doubler-enable: Enables reference doubler.
21*4882a593Smuzhiyun	- adi,reference-div2-enable: Enables reference divider.
22*4882a593Smuzhiyun	- adi,phase-detector-polarity-positive-enable: Enables positive phase
23*4882a593Smuzhiyun			detector polarity. Default = negative.
24*4882a593Smuzhiyun	- adi,lock-detect-precision-6ns-enable: Enables 6ns lock detect precision.
25*4882a593Smuzhiyun			Default = 10ns.
26*4882a593Smuzhiyun	- adi,lock-detect-function-integer-n-enable: Enables lock detect
27*4882a593Smuzhiyun			for integer-N mode. Default = factional-N mode.
28*4882a593Smuzhiyun	- adi,charge-pump-current: Charge pump current in mA.
29*4882a593Smuzhiyun			Default = 2500mA.
30*4882a593Smuzhiyun	- adi,muxout-select: On chip multiplexer output selection.
31*4882a593Smuzhiyun			Valid values for the multiplexer output are:
32*4882a593Smuzhiyun			0: Three-State Output (default)
33*4882a593Smuzhiyun			1: DVDD
34*4882a593Smuzhiyun			2: DGND
35*4882a593Smuzhiyun			3: R-Counter output
36*4882a593Smuzhiyun			4: N-Divider output
37*4882a593Smuzhiyun			5: Analog lock detect
38*4882a593Smuzhiyun			6: Digital lock detect
39*4882a593Smuzhiyun	- adi,low-spur-mode-enable: Enables low spur mode.
40*4882a593Smuzhiyun			Default = Low noise mode.
41*4882a593Smuzhiyun	- adi,cycle-slip-reduction-enable: Enables cycle slip reduction.
42*4882a593Smuzhiyun	- adi,charge-cancellation-enable: Enabled charge pump
43*4882a593Smuzhiyun			charge cancellation for integer-N modes.
44*4882a593Smuzhiyun	- adi,anti-backlash-3ns-enable: Enables 3ns antibacklash pulse width
45*4882a593Smuzhiyun			 for integer-N modes.
46*4882a593Smuzhiyun	- adi,band-select-clock-mode-high-enable: Enables faster band
47*4882a593Smuzhiyun			selection logic.
48*4882a593Smuzhiyun	- adi,12bit-clk-divider: Clock divider value used when
49*4882a593Smuzhiyun			adi,12bit-clkdiv-mode != 0
50*4882a593Smuzhiyun	- adi,clk-divider-mode:
51*4882a593Smuzhiyun			Valid values for the clkdiv mode are:
52*4882a593Smuzhiyun			0: Clock divider off (default)
53*4882a593Smuzhiyun			1: Fast lock enable
54*4882a593Smuzhiyun			2: Phase resync enable
55*4882a593Smuzhiyun	- adi,aux-output-enable: Enables auxiliary RF output.
56*4882a593Smuzhiyun	- adi,aux-output-fundamental-enable: Selects fundamental VCO output on
57*4882a593Smuzhiyun			the auxiliary RF output. Default = Output of RF dividers.
58*4882a593Smuzhiyun	- adi,mute-till-lock-enable: Enables Mute-Till-Lock-Detect function.
59*4882a593Smuzhiyun	- adi,output-power: Output power selection.
60*4882a593Smuzhiyun			Valid values for the power mode are:
61*4882a593Smuzhiyun			0: -4dBm (default)
62*4882a593Smuzhiyun			1: -1dBm
63*4882a593Smuzhiyun			2: +2dBm
64*4882a593Smuzhiyun			3: +5dBm
65*4882a593Smuzhiyun	- adi,aux-output-power: Auxiliary output power selection.
66*4882a593Smuzhiyun			Valid values for the power mode are:
67*4882a593Smuzhiyun			0: -4dBm (default)
68*4882a593Smuzhiyun			1: -1dBm
69*4882a593Smuzhiyun			2: +2dBm
70*4882a593Smuzhiyun			3: +5dBm
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun
73*4882a593SmuzhiyunExample:
74*4882a593Smuzhiyun		lo_pll0_rx_adf4351: adf4351-rx-lpc@4 {
75*4882a593Smuzhiyun			compatible = "adi,adf4351";
76*4882a593Smuzhiyun			reg = <4>;
77*4882a593Smuzhiyun			spi-max-frequency = <10000000>;
78*4882a593Smuzhiyun			clocks = <&clk0_ad9523 9>;
79*4882a593Smuzhiyun			clock-names = "clkin";
80*4882a593Smuzhiyun			adi,channel-spacing = <10000>;
81*4882a593Smuzhiyun			adi,power-up-frequency = <2400000000>;
82*4882a593Smuzhiyun			adi,phase-detector-polarity-positive-enable;
83*4882a593Smuzhiyun			adi,charge-pump-current = <2500>;
84*4882a593Smuzhiyun			adi,output-power = <3>;
85*4882a593Smuzhiyun			adi,mute-till-lock-enable;
86*4882a593Smuzhiyun		};
87