1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun# 3*4882a593Smuzhiyun# Hisilicon Clock specific Makefile 4*4882a593Smuzhiyun# 5*4882a593Smuzhiyun 6*4882a593Smuzhiyunobj-y += clk.o clkgate-separated.o clkdivider-hi6220.o clk-hisi-phase.o 7*4882a593Smuzhiyun 8*4882a593Smuzhiyunobj-$(CONFIG_ARCH_HI3xxx) += clk-hi3620.o 9*4882a593Smuzhiyunobj-$(CONFIG_ARCH_HIP04) += clk-hip04.o 10*4882a593Smuzhiyunobj-$(CONFIG_ARCH_HIX5HD2) += clk-hix5hd2.o 11*4882a593Smuzhiyunobj-$(CONFIG_COMMON_CLK_HI3516CV300) += crg-hi3516cv300.o 12*4882a593Smuzhiyunobj-$(CONFIG_COMMON_CLK_HI3519) += clk-hi3519.o 13*4882a593Smuzhiyunobj-$(CONFIG_COMMON_CLK_HI3660) += clk-hi3660.o 14*4882a593Smuzhiyunobj-$(CONFIG_COMMON_CLK_HI3670) += clk-hi3670.o 15*4882a593Smuzhiyunobj-$(CONFIG_COMMON_CLK_HI3798CV200) += crg-hi3798cv200.o 16*4882a593Smuzhiyunobj-$(CONFIG_COMMON_CLK_HI6220) += clk-hi6220.o 17*4882a593Smuzhiyunobj-$(CONFIG_RESET_HISI) += reset.o 18*4882a593Smuzhiyunobj-$(CONFIG_STUB_CLK_HI6220) += clk-hi6220-stub.o 19*4882a593Smuzhiyunobj-$(CONFIG_STUB_CLK_HI3660) += clk-hi3660-stub.o 20