1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun# 3*4882a593Smuzhiyun# Rockchip Clock specific Makefile 4*4882a593Smuzhiyun# 5*4882a593Smuzhiyun 6*4882a593Smuzhiyunobj-$(CONFIG_COMMON_CLK_ROCKCHIP) += clk-rockchip.o 7*4882a593Smuzhiyunobj-$(CONFIG_COMMON_CLK_ROCKCHIP_REGMAP) += regmap/ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunclk-rockchip-y += clk.o 10*4882a593Smuzhiyunclk-rockchip-y += clk-pll.o 11*4882a593Smuzhiyunclk-rockchip-y += clk-cpu.o 12*4882a593Smuzhiyunclk-rockchip-y += clk-half-divider.o 13*4882a593Smuzhiyunclk-rockchip-y += clk-mmc-phase.o 14*4882a593Smuzhiyunclk-rockchip-y += clk-muxgrf.o 15*4882a593Smuzhiyunclk-rockchip-$(CONFIG_ROCKCHIP_DDRCLK) += clk-ddr.o 16*4882a593Smuzhiyunclk-rockchip-$(CONFIG_ROCKCHIP_CLK_INV) += clk-inverter.o 17*4882a593Smuzhiyunclk-rockchip-$(CONFIG_ROCKCHIP_CLK_PVTM) += clk-pvtm.o 18*4882a593Smuzhiyunclk-rockchip-$(CONFIG_RESET_CONTROLLER) += softrst.o 19*4882a593Smuzhiyun 20*4882a593Smuzhiyunobj-$(CONFIG_ROCKCHIP_CLK_LINK) += clk-link.o 21*4882a593Smuzhiyunobj-$(CONFIG_ROCKCHIP_CLK_OUT) += clk-out.o 22*4882a593Smuzhiyun 23*4882a593Smuzhiyunobj-$(CONFIG_CLK_PX30) += clk-px30.o 24*4882a593Smuzhiyunobj-$(CONFIG_CLK_RV1106) += clk-rv1106.o 25*4882a593Smuzhiyunobj-$(CONFIG_CLK_RV1108) += clk-rv1108.o 26*4882a593Smuzhiyunobj-$(CONFIG_CLK_RV1126) += clk-rv1126.o 27*4882a593Smuzhiyunobj-$(CONFIG_CLK_RK1808) += clk-rk1808.o 28*4882a593Smuzhiyunobj-$(CONFIG_CLK_RK3036) += clk-rk3036.o 29*4882a593Smuzhiyunobj-$(CONFIG_CLK_RK312X) += clk-rk3128.o 30*4882a593Smuzhiyunobj-$(CONFIG_CLK_RK3188) += clk-rk3188.o 31*4882a593Smuzhiyunobj-$(CONFIG_CLK_RK322X) += clk-rk3228.o 32*4882a593Smuzhiyunobj-$(CONFIG_CLK_RK3288) += clk-rk3288.o 33*4882a593Smuzhiyunobj-$(CONFIG_CLK_RK3308) += clk-rk3308.o 34*4882a593Smuzhiyunobj-$(CONFIG_CLK_RK3328) += clk-rk3328.o 35*4882a593Smuzhiyunobj-$(CONFIG_CLK_RK3368) += clk-rk3368.o 36*4882a593Smuzhiyunobj-$(CONFIG_CLK_RK3399) += clk-rk3399.o 37*4882a593Smuzhiyunobj-$(CONFIG_CLK_RK3528) += clk-rk3528.o 38*4882a593Smuzhiyunobj-$(CONFIG_CLK_RK3562) += clk-rk3562.o 39*4882a593Smuzhiyunobj-$(CONFIG_CLK_RK3568) += clk-rk3568.o 40*4882a593Smuzhiyunobj-$(CONFIG_CLK_RK3588) += clk-rk3588.o 41