1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2017 HiSilicon Technologies Co., Ltd.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Simple HiSilicon phase clock implementation.
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/err.h>
9*4882a593Smuzhiyun #include <linux/io.h>
10*4882a593Smuzhiyun #include <linux/module.h>
11*4882a593Smuzhiyun #include <linux/platform_device.h>
12*4882a593Smuzhiyun #include <linux/slab.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #include "clk.h"
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun struct clk_hisi_phase {
17*4882a593Smuzhiyun struct clk_hw hw;
18*4882a593Smuzhiyun void __iomem *reg;
19*4882a593Smuzhiyun u32 *phase_degrees;
20*4882a593Smuzhiyun u32 *phase_regvals;
21*4882a593Smuzhiyun u8 phase_num;
22*4882a593Smuzhiyun u32 mask;
23*4882a593Smuzhiyun u8 shift;
24*4882a593Smuzhiyun u8 flags;
25*4882a593Smuzhiyun spinlock_t *lock;
26*4882a593Smuzhiyun };
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun #define to_clk_hisi_phase(_hw) container_of(_hw, struct clk_hisi_phase, hw)
29*4882a593Smuzhiyun
hisi_phase_regval_to_degrees(struct clk_hisi_phase * phase,u32 regval)30*4882a593Smuzhiyun static int hisi_phase_regval_to_degrees(struct clk_hisi_phase *phase,
31*4882a593Smuzhiyun u32 regval)
32*4882a593Smuzhiyun {
33*4882a593Smuzhiyun int i;
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun for (i = 0; i < phase->phase_num; i++)
36*4882a593Smuzhiyun if (phase->phase_regvals[i] == regval)
37*4882a593Smuzhiyun return phase->phase_degrees[i];
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun return -EINVAL;
40*4882a593Smuzhiyun }
41*4882a593Smuzhiyun
hisi_clk_get_phase(struct clk_hw * hw)42*4882a593Smuzhiyun static int hisi_clk_get_phase(struct clk_hw *hw)
43*4882a593Smuzhiyun {
44*4882a593Smuzhiyun struct clk_hisi_phase *phase = to_clk_hisi_phase(hw);
45*4882a593Smuzhiyun u32 regval;
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun regval = readl(phase->reg);
48*4882a593Smuzhiyun regval = (regval & phase->mask) >> phase->shift;
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun return hisi_phase_regval_to_degrees(phase, regval);
51*4882a593Smuzhiyun }
52*4882a593Smuzhiyun
hisi_phase_degrees_to_regval(struct clk_hisi_phase * phase,int degrees)53*4882a593Smuzhiyun static int hisi_phase_degrees_to_regval(struct clk_hisi_phase *phase,
54*4882a593Smuzhiyun int degrees)
55*4882a593Smuzhiyun {
56*4882a593Smuzhiyun int i;
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun for (i = 0; i < phase->phase_num; i++)
59*4882a593Smuzhiyun if (phase->phase_degrees[i] == degrees)
60*4882a593Smuzhiyun return phase->phase_regvals[i];
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun return -EINVAL;
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun
hisi_clk_set_phase(struct clk_hw * hw,int degrees)65*4882a593Smuzhiyun static int hisi_clk_set_phase(struct clk_hw *hw, int degrees)
66*4882a593Smuzhiyun {
67*4882a593Smuzhiyun struct clk_hisi_phase *phase = to_clk_hisi_phase(hw);
68*4882a593Smuzhiyun unsigned long flags = 0;
69*4882a593Smuzhiyun int regval;
70*4882a593Smuzhiyun u32 val;
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun regval = hisi_phase_degrees_to_regval(phase, degrees);
73*4882a593Smuzhiyun if (regval < 0)
74*4882a593Smuzhiyun return regval;
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun spin_lock_irqsave(phase->lock, flags);
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun val = readl(phase->reg);
79*4882a593Smuzhiyun val &= ~phase->mask;
80*4882a593Smuzhiyun val |= regval << phase->shift;
81*4882a593Smuzhiyun writel(val, phase->reg);
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun spin_unlock_irqrestore(phase->lock, flags);
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun return 0;
86*4882a593Smuzhiyun }
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun static const struct clk_ops clk_phase_ops = {
89*4882a593Smuzhiyun .get_phase = hisi_clk_get_phase,
90*4882a593Smuzhiyun .set_phase = hisi_clk_set_phase,
91*4882a593Smuzhiyun };
92*4882a593Smuzhiyun
clk_register_hisi_phase(struct device * dev,const struct hisi_phase_clock * clks,void __iomem * base,spinlock_t * lock)93*4882a593Smuzhiyun struct clk *clk_register_hisi_phase(struct device *dev,
94*4882a593Smuzhiyun const struct hisi_phase_clock *clks,
95*4882a593Smuzhiyun void __iomem *base, spinlock_t *lock)
96*4882a593Smuzhiyun {
97*4882a593Smuzhiyun struct clk_hisi_phase *phase;
98*4882a593Smuzhiyun struct clk_init_data init;
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun phase = devm_kzalloc(dev, sizeof(struct clk_hisi_phase), GFP_KERNEL);
101*4882a593Smuzhiyun if (!phase)
102*4882a593Smuzhiyun return ERR_PTR(-ENOMEM);
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun init.name = clks->name;
105*4882a593Smuzhiyun init.ops = &clk_phase_ops;
106*4882a593Smuzhiyun init.flags = clks->flags;
107*4882a593Smuzhiyun init.parent_names = clks->parent_names ? &clks->parent_names : NULL;
108*4882a593Smuzhiyun init.num_parents = clks->parent_names ? 1 : 0;
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun phase->reg = base + clks->offset;
111*4882a593Smuzhiyun phase->shift = clks->shift;
112*4882a593Smuzhiyun phase->mask = (BIT(clks->width) - 1) << clks->shift;
113*4882a593Smuzhiyun phase->lock = lock;
114*4882a593Smuzhiyun phase->phase_degrees = clks->phase_degrees;
115*4882a593Smuzhiyun phase->phase_regvals = clks->phase_regvals;
116*4882a593Smuzhiyun phase->phase_num = clks->phase_num;
117*4882a593Smuzhiyun phase->hw.init = &init;
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun return devm_clk_register(dev, &phase->hw);
120*4882a593Smuzhiyun }
121*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(clk_register_hisi_phase);
122