Lines Matching +full:clk +full:- +full:phase +full:-
1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/mmc/host/sdhci-msm.c - Qualcomm SDHCI Platform driver
5 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
22 #include "sdhci-pltfm.h"
121 #define INVALID_TUNING_PHASE -1
135 /* Max load for eMMC Vdd-io supply */
139 msm_host->var_ops->msm_readl_relaxed(host, offset)
142 msm_host->var_ops->msm_writel_relaxed(val, host, offset)
263 struct clk *bus_clk; /* SDHC bus voter clock */
264 struct clk *xo_clk; /* TCXO clk needed for FLL feature of cm_dll*/
298 return msm_host->offset; in sdhci_priv_msm_offset()
311 return readl_relaxed(msm_host->core_mem + offset); in sdhci_msm_mci_variant_readl_relaxed()
317 return readl_relaxed(host->ioaddr + offset); in sdhci_msm_v5_variant_readl_relaxed()
326 writel_relaxed(val, msm_host->core_mem + offset); in sdhci_msm_mci_variant_writel_relaxed()
332 writel_relaxed(val, host->ioaddr + offset); in sdhci_msm_v5_variant_writel_relaxed()
338 struct mmc_ios ios = host->mmc->ios; in msm_get_clock_rate_for_bus_mode()
348 host->flags & SDHCI_HS400_TUNING) in msm_get_clock_rate_for_bus_mode()
358 struct mmc_ios curr_ios = host->mmc->ios; in msm_set_clock_rate_for_bus_mode()
359 struct clk *core_clk = msm_host->bulk_clks[0].clk; in msm_set_clock_rate_for_bus_mode()
363 rc = dev_pm_opp_set_rate(mmc_dev(host->mmc), clock); in msm_set_clock_rate_for_bus_mode()
366 mmc_hostname(host->mmc), clock, in msm_set_clock_rate_for_bus_mode()
370 msm_host->clk_rate = clock; in msm_set_clock_rate_for_bus_mode()
372 mmc_hostname(host->mmc), clk_get_rate(core_clk), in msm_set_clock_rate_for_bus_mode()
381 struct mmc_host *mmc = host->mmc; in msm_dll_poll_ck_out_en()
386 ck_out_en = !!(readl_relaxed(host->ioaddr + in msm_dll_poll_ck_out_en()
387 msm_offset->core_dll_config) & CORE_CK_OUT_EN); in msm_dll_poll_ck_out_en()
390 if (--wait_cnt == 0) { in msm_dll_poll_ck_out_en()
393 return -ETIMEDOUT; in msm_dll_poll_ck_out_en()
397 ck_out_en = !!(readl_relaxed(host->ioaddr + in msm_dll_poll_ck_out_en()
398 msm_offset->core_dll_config) & CORE_CK_OUT_EN); in msm_dll_poll_ck_out_en()
404 static int msm_config_cm_dll_phase(struct sdhci_host *host, u8 phase) in msm_config_cm_dll_phase() argument
413 struct mmc_host *mmc = host->mmc; in msm_config_cm_dll_phase()
417 if (phase > 0xf) in msm_config_cm_dll_phase()
418 return -EINVAL; in msm_config_cm_dll_phase()
420 spin_lock_irqsave(&host->lock, flags); in msm_config_cm_dll_phase()
422 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config); in msm_config_cm_dll_phase()
425 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config); in msm_config_cm_dll_phase()
433 * Write the selected DLL clock output phase (0 ... 15) in msm_config_cm_dll_phase()
436 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config); in msm_config_cm_dll_phase()
438 config |= grey_coded_phase_table[phase] << CDR_SELEXT_SHIFT; in msm_config_cm_dll_phase()
439 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config); in msm_config_cm_dll_phase()
441 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config); in msm_config_cm_dll_phase()
443 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config); in msm_config_cm_dll_phase()
450 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config); in msm_config_cm_dll_phase()
453 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config); in msm_config_cm_dll_phase()
457 dev_err(mmc_dev(mmc), "%s: Failed to set DLL phase: %d\n", in msm_config_cm_dll_phase()
458 mmc_hostname(mmc), phase); in msm_config_cm_dll_phase()
460 spin_unlock_irqrestore(&host->lock, flags); in msm_config_cm_dll_phase()
467 * setting for SD3.0 UHS-I card read operation (in SDR104
471 * selected DLL clock output phase.
483 struct mmc_host *mmc = host->mmc; in msm_find_most_appropriate_phase()
488 return -EINVAL; in msm_find_most_appropriate_phase()
498 /* check if next phase in phase_table is consecutive or not */ in msm_find_most_appropriate_phase()
506 return -EINVAL; in msm_find_most_appropriate_phase()
508 /* Check if phase-0 is present in first valid window? */ in msm_find_most_appropriate_phase()
528 /* number of phases in raw where phase 0 is present */ in msm_find_most_appropriate_phase()
530 /* number of phases in raw where phase 15 is present */ in msm_find_most_appropriate_phase()
535 * If there are more than 1 phase windows then total in msm_find_most_appropriate_phase()
539 return -EINVAL; in msm_find_most_appropriate_phase()
563 i--; in msm_find_most_appropriate_phase()
568 ret = -EINVAL; in msm_find_most_appropriate_phase()
569 dev_err(mmc_dev(mmc), "%s: Invalid phase selected=%d\n", in msm_find_most_appropriate_phase()
583 if (host->clock <= 112000000) in msm_cm_dll_set_freq()
585 else if (host->clock <= 125000000) in msm_cm_dll_set_freq()
587 else if (host->clock <= 137000000) in msm_cm_dll_set_freq()
589 else if (host->clock <= 150000000) in msm_cm_dll_set_freq()
591 else if (host->clock <= 162000000) in msm_cm_dll_set_freq()
593 else if (host->clock <= 175000000) in msm_cm_dll_set_freq()
595 else if (host->clock <= 187000000) in msm_cm_dll_set_freq()
597 else if (host->clock <= 200000000) in msm_cm_dll_set_freq()
600 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config); in msm_cm_dll_set_freq()
603 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config); in msm_cm_dll_set_freq()
609 struct mmc_host *mmc = host->mmc; in msm_init_cm_dll()
616 msm_host->offset; in msm_init_cm_dll()
618 if (msm_host->use_14lpp_dll_reset && !IS_ERR_OR_NULL(msm_host->xo_clk)) in msm_init_cm_dll()
619 xo_clk = clk_get_rate(msm_host->xo_clk); in msm_init_cm_dll()
621 spin_lock_irqsave(&host->lock, flags); in msm_init_cm_dll()
628 config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec); in msm_init_cm_dll()
630 writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec); in msm_init_cm_dll()
632 if (msm_host->dll_config) in msm_init_cm_dll()
633 writel_relaxed(msm_host->dll_config, in msm_init_cm_dll()
634 host->ioaddr + msm_offset->core_dll_config); in msm_init_cm_dll()
636 if (msm_host->use_14lpp_dll_reset) { in msm_init_cm_dll()
637 config = readl_relaxed(host->ioaddr + in msm_init_cm_dll()
638 msm_offset->core_dll_config); in msm_init_cm_dll()
640 writel_relaxed(config, host->ioaddr + in msm_init_cm_dll()
641 msm_offset->core_dll_config); in msm_init_cm_dll()
643 config = readl_relaxed(host->ioaddr + in msm_init_cm_dll()
644 msm_offset->core_dll_config_2); in msm_init_cm_dll()
646 writel_relaxed(config, host->ioaddr + in msm_init_cm_dll()
647 msm_offset->core_dll_config_2); in msm_init_cm_dll()
650 config = readl_relaxed(host->ioaddr + in msm_init_cm_dll()
651 msm_offset->core_dll_config); in msm_init_cm_dll()
653 writel_relaxed(config, host->ioaddr + in msm_init_cm_dll()
654 msm_offset->core_dll_config); in msm_init_cm_dll()
656 config = readl_relaxed(host->ioaddr + in msm_init_cm_dll()
657 msm_offset->core_dll_config); in msm_init_cm_dll()
659 writel_relaxed(config, host->ioaddr + in msm_init_cm_dll()
660 msm_offset->core_dll_config); in msm_init_cm_dll()
662 if (!msm_host->dll_config) in msm_init_cm_dll()
665 if (msm_host->use_14lpp_dll_reset && in msm_init_cm_dll()
666 !IS_ERR_OR_NULL(msm_host->xo_clk)) { in msm_init_cm_dll()
669 config = readl_relaxed(host->ioaddr + in msm_init_cm_dll()
670 msm_offset->core_dll_config_2); in msm_init_cm_dll()
673 mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 8), in msm_init_cm_dll()
676 mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 4), in msm_init_cm_dll()
679 config = readl_relaxed(host->ioaddr + in msm_init_cm_dll()
680 msm_offset->core_dll_config_2); in msm_init_cm_dll()
684 writel_relaxed(config, host->ioaddr + in msm_init_cm_dll()
685 msm_offset->core_dll_config_2); in msm_init_cm_dll()
690 config = readl_relaxed(host->ioaddr + in msm_init_cm_dll()
691 msm_offset->core_dll_config); in msm_init_cm_dll()
693 writel_relaxed(config, host->ioaddr + in msm_init_cm_dll()
694 msm_offset->core_dll_config); in msm_init_cm_dll()
696 config = readl_relaxed(host->ioaddr + in msm_init_cm_dll()
697 msm_offset->core_dll_config); in msm_init_cm_dll()
699 writel_relaxed(config, host->ioaddr + in msm_init_cm_dll()
700 msm_offset->core_dll_config); in msm_init_cm_dll()
702 if (msm_host->use_14lpp_dll_reset) { in msm_init_cm_dll()
703 if (!msm_host->dll_config) in msm_init_cm_dll()
705 config = readl_relaxed(host->ioaddr + in msm_init_cm_dll()
706 msm_offset->core_dll_config_2); in msm_init_cm_dll()
708 writel_relaxed(config, host->ioaddr + in msm_init_cm_dll()
709 msm_offset->core_dll_config_2); in msm_init_cm_dll()
716 if (msm_host->uses_tassadar_dll) { in msm_init_cm_dll()
719 writel_relaxed(config, host->ioaddr + in msm_init_cm_dll()
720 msm_offset->core_dll_usr_ctl); in msm_init_cm_dll()
722 config = readl_relaxed(host->ioaddr + in msm_init_cm_dll()
723 msm_offset->core_dll_config_3); in msm_init_cm_dll()
725 if (msm_host->clk_rate < 150000000) in msm_init_cm_dll()
729 writel_relaxed(config, host->ioaddr + in msm_init_cm_dll()
730 msm_offset->core_dll_config_3); in msm_init_cm_dll()
733 config = readl_relaxed(host->ioaddr + in msm_init_cm_dll()
734 msm_offset->core_dll_config); in msm_init_cm_dll()
736 writel_relaxed(config, host->ioaddr + in msm_init_cm_dll()
737 msm_offset->core_dll_config); in msm_init_cm_dll()
739 config = readl_relaxed(host->ioaddr + in msm_init_cm_dll()
740 msm_offset->core_dll_config); in msm_init_cm_dll()
742 writel_relaxed(config, host->ioaddr + in msm_init_cm_dll()
743 msm_offset->core_dll_config); in msm_init_cm_dll()
746 while (!(readl_relaxed(host->ioaddr + msm_offset->core_dll_status) & in msm_init_cm_dll()
749 if (--wait_cnt == 0) { in msm_init_cm_dll()
752 spin_unlock_irqrestore(&host->lock, flags); in msm_init_cm_dll()
753 return -ETIMEDOUT; in msm_init_cm_dll()
758 spin_unlock_irqrestore(&host->lock, flags); in msm_init_cm_dll()
768 msm_host->offset; in msm_hc_select_default()
770 if (!msm_host->use_cdclp533) { in msm_hc_select_default()
771 config = readl_relaxed(host->ioaddr + in msm_hc_select_default()
772 msm_offset->core_vendor_spec3); in msm_hc_select_default()
774 writel_relaxed(config, host->ioaddr + in msm_hc_select_default()
775 msm_offset->core_vendor_spec3); in msm_hc_select_default()
778 config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec); in msm_hc_select_default()
781 writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec); in msm_hc_select_default()
790 config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec); in msm_hc_select_default()
793 writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec); in msm_hc_select_default()
806 struct mmc_ios ios = host->mmc->ios; in msm_hc_select_hs400()
810 msm_host->offset; in msm_hc_select_hs400()
813 config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec); in msm_hc_select_hs400()
817 writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec); in msm_hc_select_hs400()
822 if ((msm_host->tuning_done || ios.enhanced_strobe) && in msm_hc_select_hs400()
823 !msm_host->calibration_done) { in msm_hc_select_hs400()
824 config = readl_relaxed(host->ioaddr + in msm_hc_select_hs400()
825 msm_offset->core_vendor_spec); in msm_hc_select_hs400()
828 writel_relaxed(config, host->ioaddr + in msm_hc_select_hs400()
829 msm_offset->core_vendor_spec); in msm_hc_select_hs400()
831 if (!msm_host->clk_rate && !msm_host->use_cdclp533) { in msm_hc_select_hs400()
837 rc = readl_relaxed_poll_timeout(host->ioaddr + in msm_hc_select_hs400()
838 msm_offset->core_dll_status, in msm_hc_select_hs400()
844 if (rc == -ETIMEDOUT) in msm_hc_select_hs400()
846 mmc_hostname(host->mmc), dll_lock); in msm_hc_select_hs400()
856 * sdhci_msm_hc_select_mode :- In general all timing modes are
861 * HS200 - SDR104 (Since they both are equivalent in functionality)
862 * HS400 - This involves multiple configurations
863 * Initially SDR104 - when tuning is required as HS200
870 * HS400 - divided clock (free running MCLK/2)
871 * All other modes - default (free running MCLK)
875 struct mmc_ios ios = host->mmc->ios; in sdhci_msm_hc_select_mode()
878 host->flags & SDHCI_HS400_TUNING) in sdhci_msm_hc_select_mode()
891 msm_host->offset; in sdhci_msm_cdclp533_calibration()
893 pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__); in sdhci_msm_cdclp533_calibration()
897 * tuning block and restore the saved tuning phase. in sdhci_msm_cdclp533_calibration()
903 /* Set the selected phase in delay line hw block */ in sdhci_msm_cdclp533_calibration()
904 ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase); in sdhci_msm_cdclp533_calibration()
908 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config); in sdhci_msm_cdclp533_calibration()
910 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config); in sdhci_msm_cdclp533_calibration()
912 config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg); in sdhci_msm_cdclp533_calibration()
914 writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg); in sdhci_msm_cdclp533_calibration()
916 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG); in sdhci_msm_cdclp533_calibration()
918 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG); in sdhci_msm_cdclp533_calibration()
920 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG); in sdhci_msm_cdclp533_calibration()
922 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG); in sdhci_msm_cdclp533_calibration()
924 config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg); in sdhci_msm_cdclp533_calibration()
926 writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg); in sdhci_msm_cdclp533_calibration()
930 writel_relaxed(0x11800EC, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); in sdhci_msm_cdclp533_calibration()
931 writel_relaxed(0x3011111, host->ioaddr + CORE_CSR_CDC_CTLR_CFG1); in sdhci_msm_cdclp533_calibration()
932 writel_relaxed(0x1201000, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0); in sdhci_msm_cdclp533_calibration()
933 writel_relaxed(0x4, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG1); in sdhci_msm_cdclp533_calibration()
934 writel_relaxed(0xCB732020, host->ioaddr + CORE_CSR_CDC_REFCOUNT_CFG); in sdhci_msm_cdclp533_calibration()
935 writel_relaxed(0xB19, host->ioaddr + CORE_CSR_CDC_COARSE_CAL_CFG); in sdhci_msm_cdclp533_calibration()
936 writel_relaxed(0x4E2, host->ioaddr + CORE_CSR_CDC_DELAY_CFG); in sdhci_msm_cdclp533_calibration()
937 writel_relaxed(0x0, host->ioaddr + CORE_CDC_OFFSET_CFG); in sdhci_msm_cdclp533_calibration()
938 writel_relaxed(0x16334, host->ioaddr + CORE_CDC_SLAVE_DDA_CFG); in sdhci_msm_cdclp533_calibration()
942 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); in sdhci_msm_cdclp533_calibration()
944 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); in sdhci_msm_cdclp533_calibration()
946 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); in sdhci_msm_cdclp533_calibration()
948 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); in sdhci_msm_cdclp533_calibration()
950 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); in sdhci_msm_cdclp533_calibration()
952 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); in sdhci_msm_cdclp533_calibration()
954 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0); in sdhci_msm_cdclp533_calibration()
956 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0); in sdhci_msm_cdclp533_calibration()
958 ret = readl_relaxed_poll_timeout(host->ioaddr + CORE_CSR_CDC_STATUS0, in sdhci_msm_cdclp533_calibration()
963 if (ret == -ETIMEDOUT) { in sdhci_msm_cdclp533_calibration()
965 mmc_hostname(host->mmc), __func__); in sdhci_msm_cdclp533_calibration()
969 ret = readl_relaxed(host->ioaddr + CORE_CSR_CDC_STATUS0) in sdhci_msm_cdclp533_calibration()
973 mmc_hostname(host->mmc), __func__, ret); in sdhci_msm_cdclp533_calibration()
974 ret = -EINVAL; in sdhci_msm_cdclp533_calibration()
978 config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg); in sdhci_msm_cdclp533_calibration()
980 writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg); in sdhci_msm_cdclp533_calibration()
982 pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc), in sdhci_msm_cdclp533_calibration()
989 struct mmc_host *mmc = host->mmc; in sdhci_msm_cm_dll_sdc4_calibration()
997 pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__); in sdhci_msm_cm_dll_sdc4_calibration()
1006 if (msm_host->updated_ddr_cfg) in sdhci_msm_cm_dll_sdc4_calibration()
1007 ddr_cfg_offset = msm_offset->core_ddr_config; in sdhci_msm_cm_dll_sdc4_calibration()
1009 ddr_cfg_offset = msm_offset->core_ddr_config_old; in sdhci_msm_cm_dll_sdc4_calibration()
1010 writel_relaxed(msm_host->ddr_config, host->ioaddr + ddr_cfg_offset); in sdhci_msm_cm_dll_sdc4_calibration()
1012 if (mmc->ios.enhanced_strobe) { in sdhci_msm_cm_dll_sdc4_calibration()
1013 config = readl_relaxed(host->ioaddr + in sdhci_msm_cm_dll_sdc4_calibration()
1014 msm_offset->core_ddr_200_cfg); in sdhci_msm_cm_dll_sdc4_calibration()
1016 writel_relaxed(config, host->ioaddr + in sdhci_msm_cm_dll_sdc4_calibration()
1017 msm_offset->core_ddr_200_cfg); in sdhci_msm_cm_dll_sdc4_calibration()
1020 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config_2); in sdhci_msm_cm_dll_sdc4_calibration()
1022 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config_2); in sdhci_msm_cm_dll_sdc4_calibration()
1024 ret = readl_relaxed_poll_timeout(host->ioaddr + in sdhci_msm_cm_dll_sdc4_calibration()
1025 msm_offset->core_dll_status, in sdhci_msm_cm_dll_sdc4_calibration()
1030 if (ret == -ETIMEDOUT) { in sdhci_msm_cm_dll_sdc4_calibration()
1032 mmc_hostname(host->mmc), __func__); in sdhci_msm_cm_dll_sdc4_calibration()
1039 * and MCLK must be switched on for at-least 1us before DATA in sdhci_msm_cm_dll_sdc4_calibration()
1044 if (!msm_host->use_14lpp_dll_reset) { in sdhci_msm_cm_dll_sdc4_calibration()
1045 config = readl_relaxed(host->ioaddr + in sdhci_msm_cm_dll_sdc4_calibration()
1046 msm_offset->core_vendor_spec3); in sdhci_msm_cm_dll_sdc4_calibration()
1048 writel_relaxed(config, host->ioaddr + in sdhci_msm_cm_dll_sdc4_calibration()
1049 msm_offset->core_vendor_spec3); in sdhci_msm_cm_dll_sdc4_calibration()
1058 pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc), in sdhci_msm_cm_dll_sdc4_calibration()
1067 struct mmc_host *mmc = host->mmc; in sdhci_msm_hs400_dll_calibration()
1071 msm_host->offset; in sdhci_msm_hs400_dll_calibration()
1073 pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__); in sdhci_msm_hs400_dll_calibration()
1077 * tuning block and restore the saved tuning phase. in sdhci_msm_hs400_dll_calibration()
1083 if (!mmc->ios.enhanced_strobe) { in sdhci_msm_hs400_dll_calibration()
1084 /* Set the selected phase in delay line hw block */ in sdhci_msm_hs400_dll_calibration()
1086 msm_host->saved_tuning_phase); in sdhci_msm_hs400_dll_calibration()
1089 config = readl_relaxed(host->ioaddr + in sdhci_msm_hs400_dll_calibration()
1090 msm_offset->core_dll_config); in sdhci_msm_hs400_dll_calibration()
1092 writel_relaxed(config, host->ioaddr + in sdhci_msm_hs400_dll_calibration()
1093 msm_offset->core_dll_config); in sdhci_msm_hs400_dll_calibration()
1096 if (msm_host->use_cdclp533) in sdhci_msm_hs400_dll_calibration()
1101 pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc), in sdhci_msm_hs400_dll_calibration()
1108 struct mmc_ios *ios = &host->mmc->ios; in sdhci_msm_is_tuning_needed()
1114 if (host->clock <= CORE_FREQ_100MHZ || in sdhci_msm_is_tuning_needed()
1115 !(ios->timing == MMC_TIMING_MMC_HS400 || in sdhci_msm_is_tuning_needed()
1116 ios->timing == MMC_TIMING_MMC_HS200 || in sdhci_msm_is_tuning_needed()
1117 ios->timing == MMC_TIMING_UHS_SDR104) || in sdhci_msm_is_tuning_needed()
1118 ios->enhanced_strobe) in sdhci_msm_is_tuning_needed()
1143 ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase); in sdhci_msm_restore_sdr_dll_config()
1151 u32 config, oldconfig = readl_relaxed(host->ioaddr + in sdhci_msm_set_cdr()
1152 msm_offset->core_dll_config); in sdhci_msm_set_cdr()
1164 writel_relaxed(config, host->ioaddr + in sdhci_msm_set_cdr()
1165 msm_offset->core_dll_config); in sdhci_msm_set_cdr()
1173 u8 phase, tuned_phases[16], tuned_phase_cnt = 0; in sdhci_msm_execute_tuning() local
1175 struct mmc_ios ios = host->mmc->ios; in sdhci_msm_execute_tuning()
1180 msm_host->use_cdr = false; in sdhci_msm_execute_tuning()
1185 /* Clock-Data-Recovery used to dynamically adjust RX sampling point */ in sdhci_msm_execute_tuning()
1186 msm_host->use_cdr = true; in sdhci_msm_execute_tuning()
1192 msm_host->tuning_done = 0; in sdhci_msm_execute_tuning()
1196 * - select MCLK/2 in VENDOR_SPEC in sdhci_msm_execute_tuning()
1197 * - program MCLK to 400MHz (or nearest supported) in GCC in sdhci_msm_execute_tuning()
1199 if (host->flags & SDHCI_HS400_TUNING) { in sdhci_msm_execute_tuning()
1202 host->flags &= ~SDHCI_HS400_TUNING; in sdhci_msm_execute_tuning()
1211 phase = 0; in sdhci_msm_execute_tuning()
1213 /* Set the phase in delay line hw block */ in sdhci_msm_execute_tuning()
1214 rc = msm_config_cm_dll_phase(host, phase); in sdhci_msm_execute_tuning()
1221 tuned_phases[tuned_phase_cnt++] = phase; in sdhci_msm_execute_tuning()
1222 dev_dbg(mmc_dev(mmc), "%s: Found good phase = %d\n", in sdhci_msm_execute_tuning()
1223 mmc_hostname(mmc), phase); in sdhci_msm_execute_tuning()
1225 } while (++phase < ARRAY_SIZE(tuned_phases)); in sdhci_msm_execute_tuning()
1234 * we get a good phase. Better to try a few times. in sdhci_msm_execute_tuning()
1238 if (--tuning_seq_cnt) { in sdhci_msm_execute_tuning()
1249 phase = rc; in sdhci_msm_execute_tuning()
1252 * Finally set the selected phase in delay in sdhci_msm_execute_tuning()
1255 rc = msm_config_cm_dll_phase(host, phase); in sdhci_msm_execute_tuning()
1258 msm_host->saved_tuning_phase = phase; in sdhci_msm_execute_tuning()
1259 dev_dbg(mmc_dev(mmc), "%s: Setting the tuning phase to %d\n", in sdhci_msm_execute_tuning()
1260 mmc_hostname(mmc), phase); in sdhci_msm_execute_tuning()
1262 if (--tuning_seq_cnt) in sdhci_msm_execute_tuning()
1267 rc = -EIO; in sdhci_msm_execute_tuning()
1271 msm_host->tuning_done = true; in sdhci_msm_execute_tuning()
1276 * sdhci_msm_hs400 - Calibrate the DLL for HS400 bus speed mode operation.
1287 if (host->clock > CORE_FREQ_100MHZ && in sdhci_msm_hs400()
1288 (msm_host->tuning_done || ios->enhanced_strobe) && in sdhci_msm_hs400()
1289 !msm_host->calibration_done) { in sdhci_msm_hs400()
1292 msm_host->calibration_done = true; in sdhci_msm_hs400()
1295 mmc_hostname(host->mmc), ret); in sdhci_msm_hs400()
1302 struct mmc_host *mmc = host->mmc; in sdhci_msm_set_uhs_signaling()
1308 msm_host->offset; in sdhci_msm_set_uhs_signaling()
1340 if (host->clock <= CORE_FREQ_100MHZ) { in sdhci_msm_set_uhs_signaling()
1349 config = readl_relaxed(host->ioaddr + in sdhci_msm_set_uhs_signaling()
1350 msm_offset->core_dll_config); in sdhci_msm_set_uhs_signaling()
1352 writel_relaxed(config, host->ioaddr + in sdhci_msm_set_uhs_signaling()
1353 msm_offset->core_dll_config); in sdhci_msm_set_uhs_signaling()
1355 config = readl_relaxed(host->ioaddr + in sdhci_msm_set_uhs_signaling()
1356 msm_offset->core_dll_config); in sdhci_msm_set_uhs_signaling()
1358 writel_relaxed(config, host->ioaddr + in sdhci_msm_set_uhs_signaling()
1359 msm_offset->core_dll_config); in sdhci_msm_set_uhs_signaling()
1365 msm_host->calibration_done = false; in sdhci_msm_set_uhs_signaling()
1369 mmc_hostname(host->mmc), host->clock, uhs, ctrl_2); in sdhci_msm_set_uhs_signaling()
1372 if (mmc->ios.timing == MMC_TIMING_MMC_HS400) in sdhci_msm_set_uhs_signaling()
1373 sdhci_msm_hs400(host, &mmc->ios); in sdhci_msm_set_uhs_signaling()
1378 struct platform_device *pdev = msm_host->pdev; in sdhci_msm_set_pincfg()
1382 ret = pinctrl_pm_select_default_state(&pdev->dev); in sdhci_msm_set_pincfg()
1384 ret = pinctrl_pm_select_sleep_state(&pdev->dev); in sdhci_msm_set_pincfg()
1391 if (IS_ERR(mmc->supply.vmmc)) in sdhci_msm_set_vmmc()
1394 return mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, mmc->ios.vdd); in sdhci_msm_set_vmmc()
1403 if (msm_host->vqmmc_enabled == level) in msm_toggle_vqmmc()
1408 if (msm_host->caps_0 & CORE_3_0V_SUPPORT) in msm_toggle_vqmmc()
1410 else if (msm_host->caps_0 & CORE_1_8V_SUPPORT) in msm_toggle_vqmmc()
1413 if (msm_host->caps_0 & CORE_VOLT_SUPPORT) { in msm_toggle_vqmmc()
1421 ret = regulator_enable(mmc->supply.vqmmc); in msm_toggle_vqmmc()
1423 ret = regulator_disable(mmc->supply.vqmmc); in msm_toggle_vqmmc()
1430 msm_host->vqmmc_enabled = level; in msm_toggle_vqmmc()
1441 ret = regulator_set_load(mmc->supply.vqmmc, load); in msm_config_vqmmc_mode()
1454 if (IS_ERR(mmc->supply.vqmmc) || in sdhci_msm_set_vqmmc()
1455 (mmc->ios.power_mode == MMC_POWER_UNDEFINED)) in sdhci_msm_set_vqmmc()
1468 mmc->card && mmc_card_mmc(mmc->card); in sdhci_msm_set_vqmmc()
1480 init_waitqueue_head(&msm_host->pwr_irq_wait); in sdhci_msm_init_pwr_irq_wait()
1486 wake_up(&msm_host->pwr_irq_wait); in sdhci_msm_complete_pwr_irq_wait()
1505 msm_host->offset; in sdhci_msm_check_power_status()
1508 mmc_hostname(host->mmc), __func__, req_type, in sdhci_msm_check_power_status()
1509 msm_host->curr_pwr_state, msm_host->curr_io_level); in sdhci_msm_check_power_status()
1514 * Since sdhci-msm-v5, this bit has been removed and SW must consider in sdhci_msm_check_power_status()
1517 if (!msm_host->mci_removed) in sdhci_msm_check_power_status()
1519 msm_offset->core_generics); in sdhci_msm_check_power_status()
1526 * The IRQ for request type IO High/LOW will be generated when - in sdhci_msm_check_power_status()
1534 * for host->pwr to handle a case where IO voltage high request is in sdhci_msm_check_power_status()
1537 if ((req_type & REQ_IO_HIGH) && !host->pwr) { in sdhci_msm_check_power_status()
1539 mmc_hostname(host->mmc), req_type); in sdhci_msm_check_power_status()
1542 if ((req_type & msm_host->curr_pwr_state) || in sdhci_msm_check_power_status()
1543 (req_type & msm_host->curr_io_level)) in sdhci_msm_check_power_status()
1552 if (!wait_event_timeout(msm_host->pwr_irq_wait, in sdhci_msm_check_power_status()
1553 msm_host->pwr_irq_flag, in sdhci_msm_check_power_status()
1555 dev_warn(&msm_host->pdev->dev, in sdhci_msm_check_power_status()
1557 mmc_hostname(host->mmc), req_type); in sdhci_msm_check_power_status()
1559 pr_debug("%s: %s: request %d done\n", mmc_hostname(host->mmc), in sdhci_msm_check_power_status()
1568 msm_host->offset; in sdhci_msm_dump_pwr_ctrl_regs()
1571 mmc_hostname(host->mmc), in sdhci_msm_dump_pwr_ctrl_regs()
1572 msm_host_readl(msm_host, host, msm_offset->core_pwrctl_status), in sdhci_msm_dump_pwr_ctrl_regs()
1573 msm_host_readl(msm_host, host, msm_offset->core_pwrctl_mask), in sdhci_msm_dump_pwr_ctrl_regs()
1574 msm_host_readl(msm_host, host, msm_offset->core_pwrctl_ctl)); in sdhci_msm_dump_pwr_ctrl_regs()
1581 struct mmc_host *mmc = host->mmc; in sdhci_msm_handle_pwr_irq()
1586 const struct sdhci_msm_offset *msm_offset = msm_host->offset; in sdhci_msm_handle_pwr_irq()
1589 msm_offset->core_pwrctl_status); in sdhci_msm_handle_pwr_irq()
1593 msm_offset->core_pwrctl_clear); in sdhci_msm_handle_pwr_irq()
1603 msm_offset->core_pwrctl_status)) { in sdhci_msm_handle_pwr_irq()
1606 mmc_hostname(host->mmc), irq_status); in sdhci_msm_handle_pwr_irq()
1612 msm_offset->core_pwrctl_clear); in sdhci_msm_handle_pwr_irq()
1613 retry--; in sdhci_msm_handle_pwr_irq()
1651 if (io_level && !IS_ERR(mmc->supply.vqmmc) && !pwr_state) { in sdhci_msm_handle_pwr_irq()
1652 ret = mmc_regulator_set_vqmmc(mmc, &mmc->ios); in sdhci_msm_handle_pwr_irq()
1656 mmc->ios.signal_voltage, mmc->ios.vdd, in sdhci_msm_handle_pwr_irq()
1668 msm_offset->core_pwrctl_ctl); in sdhci_msm_handle_pwr_irq()
1674 if (msm_host->caps_0 & CORE_VOLT_SUPPORT) { in sdhci_msm_handle_pwr_irq()
1687 config = readl_relaxed(host->ioaddr + in sdhci_msm_handle_pwr_irq()
1688 msm_offset->core_vendor_spec); in sdhci_msm_handle_pwr_irq()
1692 (msm_host->caps_0 & CORE_3_0V_SUPPORT)) in sdhci_msm_handle_pwr_irq()
1695 (msm_host->caps_0 & CORE_1_8V_SUPPORT)) in sdhci_msm_handle_pwr_irq()
1699 writel_relaxed(new_config, host->ioaddr + in sdhci_msm_handle_pwr_irq()
1700 msm_offset->core_vendor_spec); in sdhci_msm_handle_pwr_irq()
1704 msm_host->curr_pwr_state = pwr_state; in sdhci_msm_handle_pwr_irq()
1706 msm_host->curr_io_level = io_level; in sdhci_msm_handle_pwr_irq()
1709 mmc_hostname(msm_host->mmc), __func__, irq, irq_status, in sdhci_msm_handle_pwr_irq()
1720 msm_host->pwr_irq_flag = 1; in sdhci_msm_pwr_irq()
1731 struct clk *core_clk = msm_host->bulk_clks[0].clk; in sdhci_msm_get_max_clock()
1742 * __sdhci_msm_set_clock - sdhci_msm clock control.
1751 u16 clk; in __sdhci_msm_set_clock() local
1753 * Keep actual_clock as zero - in __sdhci_msm_set_clock()
1754 * - since there is no divider used so no need of having actual_clock. in __sdhci_msm_set_clock()
1755 * - MSM controller uses SDCLK for data timeout calculation. If in __sdhci_msm_set_clock()
1756 * actual_clock is zero, host->clock is taken for calculation. in __sdhci_msm_set_clock()
1758 host->mmc->actual_clock = 0; in __sdhci_msm_set_clock()
1770 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); in __sdhci_msm_set_clock()
1771 sdhci_enable_clk(host, clk); in __sdhci_msm_set_clock()
1774 /* sdhci_msm_set_clock - Called with (host->lock) spinlock held. */
1781 msm_host->clk_rate = clock; in sdhci_msm_set_clock()
1817 writel((val), (host)->ice_mem + (reg))
1819 readl((host)->ice_mem + (reg))
1823 struct device *dev = mmc_dev(msm_host->mmc); in sdhci_msm_ice_supported()
1850 static inline struct clk *sdhci_msm_ice_get_clk(struct device *dev) in sdhci_msm_ice_get_clk()
1858 struct mmc_host *mmc = msm_host->mmc; in sdhci_msm_ice_init()
1866 res = platform_get_resource_byname(msm_host->pdev, IORESOURCE_MEM, in sdhci_msm_ice_init()
1878 msm_host->ice_mem = devm_ioremap_resource(dev, res); in sdhci_msm_ice_init()
1879 if (IS_ERR(msm_host->ice_mem)) { in sdhci_msm_ice_init()
1880 err = PTR_ERR(msm_host->ice_mem); in sdhci_msm_ice_init()
1888 mmc->caps2 |= MMC_CAP2_CRYPTO; in sdhci_msm_ice_init()
1903 * [0]-0, [1]-0, [2]-0, [3]-E, [4]-0, [5]-0, [6]-0, [7]-0 in sdhci_msm_ice_low_power_mode_enable()
1923 * Wait until the ICE BIST (built-in self-test) has completed.
1932 * the full storage stack anyway, and not relying on hardware-level self-tests.
1939 err = readl_poll_timeout(msm_host->ice_mem + QCOM_ICE_REG_BIST_STATUS, in sdhci_msm_ice_wait_bist_status()
1943 dev_err(mmc_dev(msm_host->mmc), in sdhci_msm_ice_wait_bist_status()
1944 "Timed out waiting for ICE self-test to complete\n"); in sdhci_msm_ice_wait_bist_status()
1950 if (!(msm_host->mmc->caps2 & MMC_CAP2_CRYPTO)) in sdhci_msm_ice_enable()
1959 if (!(msm_host->mmc->caps2 & MMC_CAP2_CRYPTO)) in sdhci_msm_ice_resume()
1966 * vendor-specific SCM calls for this; it doesn't support the standard way.
1972 struct device *dev = mmc_dev(cq_host->mmc); in sdhci_msm_program_key()
1981 if (!(cfg->config_enable & CQHCI_CRYPTO_CONFIGURATION_ENABLE)) in sdhci_msm_program_key()
1984 /* Only AES-256-XTS has been tested so far. */ in sdhci_msm_program_key()
1985 cap = cq_host->crypto_cap_array[cfg->crypto_cap_idx]; in sdhci_msm_program_key()
1991 return -EINVAL; in sdhci_msm_program_key()
1994 memcpy(key.bytes, cfg->crypto_key, AES_256_XTS_KEY_SIZE); in sdhci_msm_program_key()
1997 * The SCM call byte-swaps the 32-bit words of the key. So we have to in sdhci_msm_program_key()
2005 cfg->data_unit_size); in sdhci_msm_program_key()
2010 static inline struct clk *sdhci_msm_ice_get_clk(struct device *dev) in sdhci_msm_ice_get_clk()
2046 cqhci_irq(host->mmc, intmask, cmd_error, data_error); in sdhci_msm_cqe_irq()
2068 * on 16-byte descriptors in 64bit mode. in sdhci_msm_cqe_disable()
2070 if (host->flags & SDHCI_USE_64_BIT_DMA) in sdhci_msm_cqe_disable()
2071 host->desc_sz = 16; in sdhci_msm_cqe_disable()
2073 spin_lock_irqsave(&host->lock, flags); in sdhci_msm_cqe_disable()
2086 spin_unlock_irqrestore(&host->lock, flags); in sdhci_msm_cqe_disable()
2100 * using 4 * MCLK * 2^(count + 13). where MCLK = 1 / host->clock. in sdhci_msm_set_timeout()
2102 if (cmd && cmd->data && host->clock > 400000 && in sdhci_msm_set_timeout()
2103 host->clock <= 50000000 && in sdhci_msm_set_timeout()
2104 ((1 << (count + start)) > (10 * host->clock))) in sdhci_msm_set_timeout()
2105 host->data_timeout = 22LL * NSEC_PER_SEC; in sdhci_msm_set_timeout()
2130 if (host->caps & SDHCI_CAN_64BIT) in sdhci_msm_cqe_add_host()
2131 host->alloc_desc_sz = 16; in sdhci_msm_cqe_add_host()
2140 dev_err(&pdev->dev, "cqhci-pltfm init: failed: %d\n", ret); in sdhci_msm_cqe_add_host()
2144 msm_host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; in sdhci_msm_cqe_add_host()
2145 cq_host->ops = &sdhci_msm_cqhci_ops; in sdhci_msm_cqe_add_host()
2147 dma64 = host->flags & SDHCI_USE_64_BIT_DMA; in sdhci_msm_cqe_add_host()
2153 ret = cqhci_init(cq_host, host->mmc, dma64); in sdhci_msm_cqe_add_host()
2155 dev_err(&pdev->dev, "%s: CQE init: failed (%d)\n", in sdhci_msm_cqe_add_host()
2156 mmc_hostname(host->mmc), ret); in sdhci_msm_cqe_add_host()
2171 if (host->flags & SDHCI_USE_64_BIT_DMA) in sdhci_msm_cqe_add_host()
2172 host->desc_sz = 12; in sdhci_msm_cqe_add_host()
2178 dev_info(&pdev->dev, "%s: CQE init: success\n", in sdhci_msm_cqe_add_host()
2179 mmc_hostname(host->mmc)); in sdhci_msm_cqe_add_host()
2206 if (host->pwr && (val & SDHCI_RESET_ALL)) in __sdhci_msm_check_write()
2213 msm_host->transfer_mode = val; in __sdhci_msm_check_write()
2216 if (!msm_host->use_cdr) in __sdhci_msm_check_write()
2218 if ((msm_host->transfer_mode & SDHCI_TRNS_READ) && in __sdhci_msm_check_write()
2228 msm_host->pwr_irq_flag = 0; in __sdhci_msm_check_write()
2244 writew_relaxed(val, host->ioaddr + reg); in sdhci_msm_writew()
2257 writeb_relaxed(val, host->ioaddr + reg); in sdhci_msm_writeb()
2265 struct mmc_host *mmc = msm_host->mmc; in sdhci_msm_set_regulator_caps()
2266 struct regulator *supply = mmc->supply.vqmmc; in sdhci_msm_set_regulator_caps()
2269 const struct sdhci_msm_offset *msm_offset = msm_host->offset; in sdhci_msm_set_regulator_caps()
2271 if (!IS_ERR(mmc->supply.vqmmc)) { in sdhci_msm_set_regulator_caps()
2287 u32 io_level = msm_host->curr_io_level; in sdhci_msm_set_regulator_caps()
2289 config = readl_relaxed(host->ioaddr + in sdhci_msm_set_regulator_caps()
2290 msm_offset->core_vendor_spec); in sdhci_msm_set_regulator_caps()
2299 host->ioaddr + msm_offset->core_vendor_spec); in sdhci_msm_set_regulator_caps()
2301 msm_host->caps_0 |= caps; in sdhci_msm_set_regulator_caps()
2307 if ((host->mmc->caps2 & MMC_CAP2_CQE) && (mask & SDHCI_RESET_ALL)) in sdhci_msm_reset()
2308 cqhci_deactivate(host->mmc); in sdhci_msm_reset()
2316 ret = mmc_regulator_get_supply(msm_host->mmc); in sdhci_msm_register_vreg()
2335 if (host->version < SDHCI_SPEC_300) in sdhci_msm_start_signal_voltage_switch()
2340 switch (ios->signal_voltage) { in sdhci_msm_start_signal_voltage_switch()
2342 if (!(host->flags & SDHCI_SIGNALING_330)) in sdhci_msm_start_signal_voltage_switch()
2343 return -EINVAL; in sdhci_msm_start_signal_voltage_switch()
2349 if (!(host->flags & SDHCI_SIGNALING_180)) in sdhci_msm_start_signal_voltage_switch()
2350 return -EINVAL; in sdhci_msm_start_signal_voltage_switch()
2357 return -EINVAL; in sdhci_msm_start_signal_voltage_switch()
2374 return -EAGAIN; in sdhci_msm_start_signal_voltage_switch()
2379 pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
2385 const struct sdhci_msm_offset *msm_offset = msm_host->offset; in sdhci_msm_dump_vendor_regs()
2387 SDHCI_MSM_DUMP("----------- VENDOR REGISTER DUMP -----------\n"); in sdhci_msm_dump_vendor_regs()
2391 readl_relaxed(host->ioaddr + msm_offset->core_dll_status), in sdhci_msm_dump_vendor_regs()
2392 readl_relaxed(host->ioaddr + msm_offset->core_dll_config), in sdhci_msm_dump_vendor_regs()
2393 readl_relaxed(host->ioaddr + msm_offset->core_dll_config_2)); in sdhci_msm_dump_vendor_regs()
2396 readl_relaxed(host->ioaddr + msm_offset->core_dll_config_3), in sdhci_msm_dump_vendor_regs()
2397 readl_relaxed(host->ioaddr + msm_offset->core_dll_usr_ctl), in sdhci_msm_dump_vendor_regs()
2398 readl_relaxed(host->ioaddr + msm_offset->core_ddr_config)); in sdhci_msm_dump_vendor_regs()
2401 readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec), in sdhci_msm_dump_vendor_regs()
2402 readl_relaxed(host->ioaddr + in sdhci_msm_dump_vendor_regs()
2403 msm_offset->core_vendor_spec_func2), in sdhci_msm_dump_vendor_regs()
2404 readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec3)); in sdhci_msm_dump_vendor_regs()
2443 {.compatible = "qcom,sdhci-msm-v4", .data = &sdhci_msm_mci_var},
2444 {.compatible = "qcom,sdhci-msm-v5", .data = &sdhci_msm_v5_var},
2445 {.compatible = "qcom,sdm670-sdhci", .data = &sdm845_sdhci_var},
2446 {.compatible = "qcom,sdm845-sdhci", .data = &sdm845_sdhci_var},
2447 {.compatible = "qcom,sm8250-sdhci", .data = &sm8250_sdhci_var},
2448 {.compatible = "qcom,sc7180-sdhci", .data = &sdm845_sdhci_var},
2482 struct device_node *node = pdev->dev.of_node; in sdhci_msm_get_of_property()
2486 if (of_property_read_u32(node, "qcom,ddr-config", in sdhci_msm_get_of_property()
2487 &msm_host->ddr_config)) in sdhci_msm_get_of_property()
2488 msm_host->ddr_config = DDR_CONFIG_POR_VAL; in sdhci_msm_get_of_property()
2490 of_property_read_u32(node, "qcom,dll-config", &msm_host->dll_config); in sdhci_msm_get_of_property()
2514 * is at least 3-4 sleep clock (32.7KHz) cycles, which comes to in sdhci_msm_gcc_reset()
2536 struct clk *clk; in sdhci_msm_probe() local
2543 struct device_node *node = pdev->dev.of_node; in sdhci_msm_probe()
2549 host->sdma_boundary = 0; in sdhci_msm_probe()
2552 msm_host->mmc = host->mmc; in sdhci_msm_probe()
2553 msm_host->pdev = pdev; in sdhci_msm_probe()
2555 ret = mmc_of_parse(host->mmc); in sdhci_msm_probe()
2563 var_info = of_device_get_match_data(&pdev->dev); in sdhci_msm_probe()
2565 msm_host->mci_removed = var_info->mci_removed; in sdhci_msm_probe()
2566 msm_host->restore_dll_config = var_info->restore_dll_config; in sdhci_msm_probe()
2567 msm_host->var_ops = var_info->var_ops; in sdhci_msm_probe()
2568 msm_host->offset = var_info->offset; in sdhci_msm_probe()
2569 msm_host->uses_tassadar_dll = var_info->uses_tassadar_dll; in sdhci_msm_probe()
2571 msm_offset = msm_host->offset; in sdhci_msm_probe()
2576 msm_host->saved_tuning_phase = INVALID_TUNING_PHASE; in sdhci_msm_probe()
2578 ret = sdhci_msm_gcc_reset(&pdev->dev, host); in sdhci_msm_probe()
2583 msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus"); in sdhci_msm_probe()
2584 if (!IS_ERR(msm_host->bus_clk)) { in sdhci_msm_probe()
2585 /* Vote for max. clk rate for max. performance */ in sdhci_msm_probe()
2586 ret = clk_set_rate(msm_host->bus_clk, INT_MAX); in sdhci_msm_probe()
2589 ret = clk_prepare_enable(msm_host->bus_clk); in sdhci_msm_probe()
2595 clk = devm_clk_get(&pdev->dev, "iface"); in sdhci_msm_probe()
2596 if (IS_ERR(clk)) { in sdhci_msm_probe()
2597 ret = PTR_ERR(clk); in sdhci_msm_probe()
2598 dev_err(&pdev->dev, "Peripheral clk setup failed (%d)\n", ret); in sdhci_msm_probe()
2601 msm_host->bulk_clks[1].clk = clk; in sdhci_msm_probe()
2604 clk = devm_clk_get(&pdev->dev, "core"); in sdhci_msm_probe()
2605 if (IS_ERR(clk)) { in sdhci_msm_probe()
2606 ret = PTR_ERR(clk); in sdhci_msm_probe()
2607 dev_err(&pdev->dev, "SDC MMC clk setup failed (%d)\n", ret); in sdhci_msm_probe()
2610 msm_host->bulk_clks[0].clk = clk; in sdhci_msm_probe()
2613 ret = dev_pm_opp_of_find_icc_paths(&pdev->dev, NULL); in sdhci_msm_probe()
2617 msm_host->opp_table = dev_pm_opp_set_clkname(&pdev->dev, "core"); in sdhci_msm_probe()
2618 if (IS_ERR(msm_host->opp_table)) { in sdhci_msm_probe()
2619 ret = PTR_ERR(msm_host->opp_table); in sdhci_msm_probe()
2624 ret = dev_pm_opp_of_add_table(&pdev->dev); in sdhci_msm_probe()
2625 if (ret && ret != -ENODEV) { in sdhci_msm_probe()
2626 dev_err(&pdev->dev, "Invalid OPP table in Device tree\n"); in sdhci_msm_probe()
2631 ret = dev_pm_opp_set_rate(&pdev->dev, INT_MAX); in sdhci_msm_probe()
2633 dev_warn(&pdev->dev, "core clock boost failed\n"); in sdhci_msm_probe()
2635 clk = devm_clk_get(&pdev->dev, "cal"); in sdhci_msm_probe()
2636 if (IS_ERR(clk)) in sdhci_msm_probe()
2637 clk = NULL; in sdhci_msm_probe()
2638 msm_host->bulk_clks[2].clk = clk; in sdhci_msm_probe()
2640 clk = devm_clk_get(&pdev->dev, "sleep"); in sdhci_msm_probe()
2641 if (IS_ERR(clk)) in sdhci_msm_probe()
2642 clk = NULL; in sdhci_msm_probe()
2643 msm_host->bulk_clks[3].clk = clk; in sdhci_msm_probe()
2645 clk = sdhci_msm_ice_get_clk(&pdev->dev); in sdhci_msm_probe()
2646 if (IS_ERR(clk)) in sdhci_msm_probe()
2647 clk = NULL; in sdhci_msm_probe()
2648 msm_host->bulk_clks[4].clk = clk; in sdhci_msm_probe()
2650 ret = clk_bulk_prepare_enable(ARRAY_SIZE(msm_host->bulk_clks), in sdhci_msm_probe()
2651 msm_host->bulk_clks); in sdhci_msm_probe()
2659 msm_host->xo_clk = devm_clk_get(&pdev->dev, "xo"); in sdhci_msm_probe()
2660 if (IS_ERR(msm_host->xo_clk)) { in sdhci_msm_probe()
2661 ret = PTR_ERR(msm_host->xo_clk); in sdhci_msm_probe()
2662 dev_warn(&pdev->dev, "TCXO clk not present (%d)\n", ret); in sdhci_msm_probe()
2665 if (!msm_host->mci_removed) { in sdhci_msm_probe()
2666 msm_host->core_mem = devm_platform_ioremap_resource(pdev, 1); in sdhci_msm_probe()
2667 if (IS_ERR(msm_host->core_mem)) { in sdhci_msm_probe()
2668 ret = PTR_ERR(msm_host->core_mem); in sdhci_msm_probe()
2675 host->ioaddr + msm_offset->core_vendor_spec); in sdhci_msm_probe()
2677 if (!msm_host->mci_removed) { in sdhci_msm_probe()
2680 msm_offset->core_hc_mode); in sdhci_msm_probe()
2682 msm_offset->core_hc_mode); in sdhci_msm_probe()
2685 msm_offset->core_hc_mode); in sdhci_msm_probe()
2688 host_version = readw_relaxed((host->ioaddr + SDHCI_HOST_VERSION)); in sdhci_msm_probe()
2689 dev_dbg(&pdev->dev, "Host Version: 0x%x Vendor Version 0x%x\n", in sdhci_msm_probe()
2694 msm_offset->core_mci_version); in sdhci_msm_probe()
2698 dev_dbg(&pdev->dev, "MCI Version: 0x%08x, major: 0x%04x, minor: 0x%02x\n", in sdhci_msm_probe()
2702 msm_host->use_14lpp_dll_reset = true; in sdhci_msm_probe()
2709 msm_host->use_cdclp533 = true; in sdhci_msm_probe()
2716 config = readl_relaxed(host->ioaddr + SDHCI_CAPABILITIES); in sdhci_msm_probe()
2718 writel_relaxed(config, host->ioaddr + in sdhci_msm_probe()
2719 msm_offset->core_vendor_spec_capabilities0); in sdhci_msm_probe()
2723 msm_host->updated_ddr_cfg = true; in sdhci_msm_probe()
2745 msm_host->pwr_irq = platform_get_irq_byname(pdev, "pwr_irq"); in sdhci_msm_probe()
2746 if (msm_host->pwr_irq < 0) { in sdhci_msm_probe()
2747 ret = msm_host->pwr_irq; in sdhci_msm_probe()
2754 msm_offset->core_pwrctl_mask); in sdhci_msm_probe()
2756 ret = devm_request_threaded_irq(&pdev->dev, msm_host->pwr_irq, NULL, in sdhci_msm_probe()
2758 dev_name(&pdev->dev), host); in sdhci_msm_probe()
2760 dev_err(&pdev->dev, "Request IRQ failed (%d)\n", ret); in sdhci_msm_probe()
2764 msm_host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_NEED_RSP_BUSY; in sdhci_msm_probe()
2766 pm_runtime_get_noresume(&pdev->dev); in sdhci_msm_probe()
2767 pm_runtime_set_active(&pdev->dev); in sdhci_msm_probe()
2768 pm_runtime_enable(&pdev->dev); in sdhci_msm_probe()
2769 pm_runtime_set_autosuspend_delay(&pdev->dev, in sdhci_msm_probe()
2771 pm_runtime_use_autosuspend(&pdev->dev); in sdhci_msm_probe()
2773 host->mmc_host_ops.start_signal_voltage_switch = in sdhci_msm_probe()
2775 host->mmc_host_ops.execute_tuning = sdhci_msm_execute_tuning; in sdhci_msm_probe()
2776 if (of_property_read_bool(node, "supports-cqe")) in sdhci_msm_probe()
2783 pm_runtime_mark_last_busy(&pdev->dev); in sdhci_msm_probe()
2784 pm_runtime_put_autosuspend(&pdev->dev); in sdhci_msm_probe()
2789 pm_runtime_disable(&pdev->dev); in sdhci_msm_probe()
2790 pm_runtime_set_suspended(&pdev->dev); in sdhci_msm_probe()
2791 pm_runtime_put_noidle(&pdev->dev); in sdhci_msm_probe()
2793 clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks), in sdhci_msm_probe()
2794 msm_host->bulk_clks); in sdhci_msm_probe()
2796 dev_pm_opp_of_remove_table(&pdev->dev); in sdhci_msm_probe()
2798 dev_pm_opp_put_clkname(msm_host->opp_table); in sdhci_msm_probe()
2800 if (!IS_ERR(msm_host->bus_clk)) in sdhci_msm_probe()
2801 clk_disable_unprepare(msm_host->bus_clk); in sdhci_msm_probe()
2812 int dead = (readl_relaxed(host->ioaddr + SDHCI_INT_STATUS) == in sdhci_msm_remove()
2817 dev_pm_opp_of_remove_table(&pdev->dev); in sdhci_msm_remove()
2818 dev_pm_opp_put_clkname(msm_host->opp_table); in sdhci_msm_remove()
2819 pm_runtime_get_sync(&pdev->dev); in sdhci_msm_remove()
2820 pm_runtime_disable(&pdev->dev); in sdhci_msm_remove()
2821 pm_runtime_put_noidle(&pdev->dev); in sdhci_msm_remove()
2823 clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks), in sdhci_msm_remove()
2824 msm_host->bulk_clks); in sdhci_msm_remove()
2825 if (!IS_ERR(msm_host->bus_clk)) in sdhci_msm_remove()
2826 clk_disable_unprepare(msm_host->bus_clk); in sdhci_msm_remove()
2839 clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks), in sdhci_msm_runtime_suspend()
2840 msm_host->bulk_clks); in sdhci_msm_runtime_suspend()
2852 ret = clk_bulk_prepare_enable(ARRAY_SIZE(msm_host->bulk_clks), in sdhci_msm_runtime_resume()
2853 msm_host->bulk_clks); in sdhci_msm_runtime_resume()
2857 * Whenever core-clock is gated dynamically, it's needed to in sdhci_msm_runtime_resume()
2860 if (msm_host->restore_dll_config && msm_host->clk_rate) { in sdhci_msm_runtime_resume()
2866 dev_pm_opp_set_rate(dev, msm_host->clk_rate); in sdhci_msm_runtime_resume()