1*4882a593SmuzhiyunDevice Tree Clock bindings for Altera's SoCFPGA platform 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThis binding uses the common clock binding[1]. 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun[1] Documentation/devicetree/bindings/clock/clock-bindings.txt 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunRequired properties: 8*4882a593Smuzhiyun- compatible : shall be one of the following: 9*4882a593Smuzhiyun "altr,socfpga-pll-clock" - for a PLL clock 10*4882a593Smuzhiyun "altr,socfpga-perip-clock" - The peripheral clock divided from the 11*4882a593Smuzhiyun PLL clock. 12*4882a593Smuzhiyun "altr,socfpga-gate-clk" - Clocks that directly feed peripherals and 13*4882a593Smuzhiyun can get gated. 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun- reg : shall be the control register offset from CLOCK_MANAGER's base for the clock. 16*4882a593Smuzhiyun- clocks : shall be the input parent clock phandle for the clock. This is 17*4882a593Smuzhiyun either an oscillator or a pll output. 18*4882a593Smuzhiyun- #clock-cells : from common clock binding, shall be set to 0. 19*4882a593Smuzhiyun 20*4882a593SmuzhiyunOptional properties: 21*4882a593Smuzhiyun- fixed-divider : If clocks have a fixed divider value, use this property. 22*4882a593Smuzhiyun- clk-gate : For "socfpga-gate-clk", clk-gate contains the gating register 23*4882a593Smuzhiyun and the bit index. 24*4882a593Smuzhiyun- div-reg : For "socfpga-gate-clk" and "socfpga-periph-clock", div-reg contains 25*4882a593Smuzhiyun the divider register, bit shift, and width. 26*4882a593Smuzhiyun- clk-phase : For the sdmmc_clk, contains the value of the clock phase that controls 27*4882a593Smuzhiyun the SDMMC CIU clock. The first value is the clk_sample(smpsel), and the second 28*4882a593Smuzhiyun value is the cclk_in_drv(drvsel). The clk-phase is used to enable the correct 29*4882a593Smuzhiyun hold/delay times that is needed for the SD/MMC CIU clock. The values of both 30*4882a593Smuzhiyun can be 0-315 degrees, in 45 degree increments. 31