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/OK3568_Linux_fs/kernel/drivers/clk/imx/
H A Dclk-pllv1.c18 * PLL clock version 1, found on i.MX1/21/25/27/31/35
67 * frequency. PLLs with this register layout can be found on i.MX1, in clk_pllv1_recalc_rate()
85 * On all i.MXs except i.MX1 and i.MX21 mfn is a 10bit in clk_pllv1_recalc_rate()
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/
H A Dimx1-clock.yaml7 title: Clock bindings for Freescale i.MX1 CPUs
15 for the full list of i.MX1 clock IDs.
/OK3568_Linux_fs/kernel/arch/arm/mach-imx/
H A DKconfig73 bool "i.MX1 support"
78 This enables support for Freescale i.MX1 processor
H A Dmach-imx1.c35 DT_MACHINE_START(IMX1_DT, "Freescale i.MX1 (Device Tree Support)")
H A Dhardware.h40 * mx1:
/OK3568_Linux_fs/kernel/include/soc/imx/
H A Dtimer.h10 GPT_TYPE_IMX1, /* i.MX1 */
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/pwm/
H A Dimx-pwm.yaml15 Should be 2 for i.MX1 and 3 for i.MX27 and newer SoCs. See pwm.yaml
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dimx1-ads.dts10 model = "Freescale MX1 ADS";
H A Dimx1-pinfunc.h29 * 'pin' is an integer between 0 and 0xbf. i.MX1 has 4 ports with 32 configurable
/OK3568_Linux_fs/kernel/drivers/watchdog/
H A Dimx2_wdt.c11 * NOTE: MX1 has a slightly different Watchdog than MX2 and later:
13 * MX1: MX2+:
/OK3568_Linux_fs/kernel/drivers/clocksource/
H A Dtimer-imx-gpt.c23 * - MX1/MXL
34 /* MX1, MX21, MX27 */
/OK3568_Linux_fs/u-boot/drivers/mmc/
H A Dmxcmmc.c3 * SoCs. It is basically the same hardware as found on MX1 (imxmmc.c).
4 * Unlike the hardware found on MX1, this hardware just works and does
/OK3568_Linux_fs/kernel/drivers/pwm/
H A DKconfig222 tristate "i.MX1 PWM support"
225 Generic PWM framework driver for i.MX1 and i.MX21
/OK3568_Linux_fs/kernel/drivers/soc/imx/
H A Dsoc-imx.c57 soc_id = "i.MX1"; in imx_soc_device_init()
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/bus/
H A Dimx-weim.txt57 For i.MX1, i.MX21 ("fsl,imx1-weim") there are two
/OK3568_Linux_fs/kernel/drivers/gpio/
H A Dgpio-mxc.c28 IMX1_GPIO, /* runs on i.mx1 */
277 /* MX1 and MX3 has one interrupt *per* gpio port */
/OK3568_Linux_fs/kernel/drivers/pinctrl/freescale/
H A Dpinctrl-imx1.c3 // i.MX1 pinctrl driver based on imx pinmux core
H A Dpinctrl-imx1-core.c36 * MX1 register offsets
/OK3568_Linux_fs/kernel/drivers/bus/
H A Dimx-weim.c66 /* i.MX1/21 */
/OK3568_Linux_fs/kernel/drivers/mmc/host/
H A Dmxcmmc.c6 * SoCs. It is basically the same hardware as found on MX1 (imxmmc.c).
7 * Unlike the hardware found on MX1, this hardware just works and does
/OK3568_Linux_fs/kernel/drivers/tty/serial/
H A Dimx.c54 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
78 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
178 /* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */
2426 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later in imx_uart_probe()
/OK3568_Linux_fs/kernel/drivers/dma/
H A DKconfig267 Freescale i.MX1/21/27 chips.
/OK3568_Linux_fs/kernel/arch/arm/
H A DKconfig.debug382 bool "i.MX1 Debug UART"
386 on i.MX1.
/OK3568_Linux_fs/kernel/drivers/mfd/
H A Dsm501.c173 "M %ld.%ld (%ld), MX1 %ld.%ld (%ld)\n", in sm501_dump_clk()
182 "M %ld.%ld (%ld), MX1 %ld.%ld (%ld)\n", in sm501_dump_clk()
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/arm/
H A Dfsl.yaml18 - description: i.MX1 based Boards

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