1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/pwm/imx-pwm.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Freescale i.MX PWM controller 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Philipp Zabel <p.zabel@pengutronix.de> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyunproperties: 13*4882a593Smuzhiyun "#pwm-cells": 14*4882a593Smuzhiyun description: | 15*4882a593Smuzhiyun Should be 2 for i.MX1 and 3 for i.MX27 and newer SoCs. See pwm.yaml 16*4882a593Smuzhiyun in this directory for a description of the cells format. 17*4882a593Smuzhiyun enum: 18*4882a593Smuzhiyun - 2 19*4882a593Smuzhiyun - 3 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun compatible: 22*4882a593Smuzhiyun oneOf: 23*4882a593Smuzhiyun - enum: 24*4882a593Smuzhiyun - fsl,imx1-pwm 25*4882a593Smuzhiyun - fsl,imx27-pwm 26*4882a593Smuzhiyun - items: 27*4882a593Smuzhiyun - enum: 28*4882a593Smuzhiyun - fsl,imx25-pwm 29*4882a593Smuzhiyun - fsl,imx31-pwm 30*4882a593Smuzhiyun - fsl,imx50-pwm 31*4882a593Smuzhiyun - fsl,imx51-pwm 32*4882a593Smuzhiyun - fsl,imx53-pwm 33*4882a593Smuzhiyun - fsl,imx6q-pwm 34*4882a593Smuzhiyun - fsl,imx6sl-pwm 35*4882a593Smuzhiyun - fsl,imx6sll-pwm 36*4882a593Smuzhiyun - fsl,imx6sx-pwm 37*4882a593Smuzhiyun - fsl,imx6ul-pwm 38*4882a593Smuzhiyun - fsl,imx7d-pwm 39*4882a593Smuzhiyun - fsl,imx8mm-pwm 40*4882a593Smuzhiyun - fsl,imx8mn-pwm 41*4882a593Smuzhiyun - fsl,imx8mp-pwm 42*4882a593Smuzhiyun - fsl,imx8mq-pwm 43*4882a593Smuzhiyun - const: fsl,imx27-pwm 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun reg: 46*4882a593Smuzhiyun maxItems: 1 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun clocks: 49*4882a593Smuzhiyun items: 50*4882a593Smuzhiyun - description: SoC PWM ipg clock 51*4882a593Smuzhiyun - description: SoC PWM per clock 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun clock-names: 54*4882a593Smuzhiyun items: 55*4882a593Smuzhiyun - const: ipg 56*4882a593Smuzhiyun - const: per 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun interrupts: 59*4882a593Smuzhiyun maxItems: 1 60*4882a593Smuzhiyun 61*4882a593Smuzhiyunrequired: 62*4882a593Smuzhiyun - "#pwm-cells" 63*4882a593Smuzhiyun - compatible 64*4882a593Smuzhiyun - reg 65*4882a593Smuzhiyun - clocks 66*4882a593Smuzhiyun - clock-names 67*4882a593Smuzhiyun - interrupts 68*4882a593Smuzhiyun 69*4882a593SmuzhiyunadditionalProperties: false 70*4882a593Smuzhiyun 71*4882a593Smuzhiyunexamples: 72*4882a593Smuzhiyun - | 73*4882a593Smuzhiyun #include <dt-bindings/clock/imx5-clock.h> 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun pwm@53fb4000 { 76*4882a593Smuzhiyun #pwm-cells = <3>; 77*4882a593Smuzhiyun compatible = "fsl,imx27-pwm"; 78*4882a593Smuzhiyun reg = <0x53fb4000 0x4000>; 79*4882a593Smuzhiyun clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>, 80*4882a593Smuzhiyun <&clks IMX5_CLK_PWM1_HF_GATE>; 81*4882a593Smuzhiyun clock-names = "ipg", "per"; 82*4882a593Smuzhiyun interrupts = <61>; 83*4882a593Smuzhiyun }; 84