xref: /OK3568_Linux_fs/kernel/drivers/dma/Kconfig (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun#
3*4882a593Smuzhiyun# DMA engine configuration
4*4882a593Smuzhiyun#
5*4882a593Smuzhiyun
6*4882a593Smuzhiyunmenuconfig DMADEVICES
7*4882a593Smuzhiyun	bool "DMA Engine support"
8*4882a593Smuzhiyun	depends on HAS_DMA
9*4882a593Smuzhiyun	help
10*4882a593Smuzhiyun	  DMA engines can do asynchronous data transfers without
11*4882a593Smuzhiyun	  involving the host CPU.  Currently, this framework can be
12*4882a593Smuzhiyun	  used to offload memory copies in the network stack and
13*4882a593Smuzhiyun	  RAID operations in the MD driver.  This menu only presents
14*4882a593Smuzhiyun	  DMA Device drivers supported by the configured arch, it may
15*4882a593Smuzhiyun	  be empty in some cases.
16*4882a593Smuzhiyun
17*4882a593Smuzhiyunconfig DMADEVICES_DEBUG
18*4882a593Smuzhiyun	bool "DMA Engine debugging"
19*4882a593Smuzhiyun	depends on DMADEVICES != n
20*4882a593Smuzhiyun	help
21*4882a593Smuzhiyun	  This is an option for use by developers; most people should
22*4882a593Smuzhiyun	  say N here.  This enables DMA engine core and driver debugging.
23*4882a593Smuzhiyun
24*4882a593Smuzhiyunconfig DMADEVICES_VDEBUG
25*4882a593Smuzhiyun	bool "DMA Engine verbose debugging"
26*4882a593Smuzhiyun	depends on DMADEVICES_DEBUG != n
27*4882a593Smuzhiyun	help
28*4882a593Smuzhiyun	  This is an option for use by developers; most people should
29*4882a593Smuzhiyun	  say N here.  This enables deeper (more verbose) debugging of
30*4882a593Smuzhiyun	  the DMA engine core and drivers.
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun
33*4882a593Smuzhiyunif DMADEVICES
34*4882a593Smuzhiyun
35*4882a593Smuzhiyuncomment "DMA Devices"
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun#core
38*4882a593Smuzhiyunconfig ASYNC_TX_ENABLE_CHANNEL_SWITCH
39*4882a593Smuzhiyun	bool
40*4882a593Smuzhiyun
41*4882a593Smuzhiyunconfig ARCH_HAS_ASYNC_TX_FIND_CHANNEL
42*4882a593Smuzhiyun	bool
43*4882a593Smuzhiyun
44*4882a593Smuzhiyunconfig DMA_ENGINE
45*4882a593Smuzhiyun	bool
46*4882a593Smuzhiyun
47*4882a593Smuzhiyunconfig DMA_VIRTUAL_CHANNELS
48*4882a593Smuzhiyun	tristate
49*4882a593Smuzhiyun
50*4882a593Smuzhiyunconfig DMA_ACPI
51*4882a593Smuzhiyun	def_bool y
52*4882a593Smuzhiyun	depends on ACPI
53*4882a593Smuzhiyun
54*4882a593Smuzhiyunconfig DMA_OF
55*4882a593Smuzhiyun	def_bool y
56*4882a593Smuzhiyun	depends on OF
57*4882a593Smuzhiyun	select DMA_ENGINE
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun#devices
60*4882a593Smuzhiyunconfig ALTERA_MSGDMA
61*4882a593Smuzhiyun	tristate "Altera / Intel mSGDMA Engine"
62*4882a593Smuzhiyun	depends on HAS_IOMEM
63*4882a593Smuzhiyun	select DMA_ENGINE
64*4882a593Smuzhiyun	help
65*4882a593Smuzhiyun	  Enable support for Altera / Intel mSGDMA controller.
66*4882a593Smuzhiyun
67*4882a593Smuzhiyunconfig AMBA_PL08X
68*4882a593Smuzhiyun	bool "ARM PrimeCell PL080 or PL081 support"
69*4882a593Smuzhiyun	depends on ARM_AMBA
70*4882a593Smuzhiyun	select DMA_ENGINE
71*4882a593Smuzhiyun	select DMA_VIRTUAL_CHANNELS
72*4882a593Smuzhiyun	help
73*4882a593Smuzhiyun	  Say yes if your platform has a PL08x DMAC device which can
74*4882a593Smuzhiyun	  provide DMA engine support. This includes the original ARM
75*4882a593Smuzhiyun	  PL080 and PL081, Samsungs PL080 derivative and Faraday
76*4882a593Smuzhiyun	  Technology's FTDMAC020 PL080 derivative.
77*4882a593Smuzhiyun
78*4882a593Smuzhiyunconfig AMCC_PPC440SPE_ADMA
79*4882a593Smuzhiyun	tristate "AMCC PPC440SPe ADMA support"
80*4882a593Smuzhiyun	depends on 440SPe || 440SP
81*4882a593Smuzhiyun	select DMA_ENGINE
82*4882a593Smuzhiyun	select DMA_ENGINE_RAID
83*4882a593Smuzhiyun	select ARCH_HAS_ASYNC_TX_FIND_CHANNEL
84*4882a593Smuzhiyun	select ASYNC_TX_ENABLE_CHANNEL_SWITCH
85*4882a593Smuzhiyun	help
86*4882a593Smuzhiyun	  Enable support for the AMCC PPC440SPe RAID engines.
87*4882a593Smuzhiyun
88*4882a593Smuzhiyunconfig AT_HDMAC
89*4882a593Smuzhiyun	tristate "Atmel AHB DMA support"
90*4882a593Smuzhiyun	depends on ARCH_AT91
91*4882a593Smuzhiyun	select DMA_ENGINE
92*4882a593Smuzhiyun	help
93*4882a593Smuzhiyun	  Support the Atmel AHB DMA controller.
94*4882a593Smuzhiyun
95*4882a593Smuzhiyunconfig AT_XDMAC
96*4882a593Smuzhiyun	tristate "Atmel XDMA support"
97*4882a593Smuzhiyun	depends on ARCH_AT91
98*4882a593Smuzhiyun	select DMA_ENGINE
99*4882a593Smuzhiyun	help
100*4882a593Smuzhiyun	  Support the Atmel XDMA controller.
101*4882a593Smuzhiyun
102*4882a593Smuzhiyunconfig AXI_DMAC
103*4882a593Smuzhiyun	tristate "Analog Devices AXI-DMAC DMA support"
104*4882a593Smuzhiyun	depends on MICROBLAZE || NIOS2 || ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_SOCFPGA || COMPILE_TEST
105*4882a593Smuzhiyun	select DMA_ENGINE
106*4882a593Smuzhiyun	select DMA_VIRTUAL_CHANNELS
107*4882a593Smuzhiyun	select REGMAP_MMIO
108*4882a593Smuzhiyun	help
109*4882a593Smuzhiyun	  Enable support for the Analog Devices AXI-DMAC peripheral. This DMA
110*4882a593Smuzhiyun	  controller is often used in Analog Devices' reference designs for FPGA
111*4882a593Smuzhiyun	  platforms.
112*4882a593Smuzhiyun
113*4882a593Smuzhiyunconfig BCM_SBA_RAID
114*4882a593Smuzhiyun	tristate "Broadcom SBA RAID engine support"
115*4882a593Smuzhiyun	depends on ARM64 || COMPILE_TEST
116*4882a593Smuzhiyun	depends on MAILBOX && RAID6_PQ
117*4882a593Smuzhiyun	select DMA_ENGINE
118*4882a593Smuzhiyun	select DMA_ENGINE_RAID
119*4882a593Smuzhiyun	select ASYNC_TX_DISABLE_XOR_VAL_DMA
120*4882a593Smuzhiyun	select ASYNC_TX_DISABLE_PQ_VAL_DMA
121*4882a593Smuzhiyun	default m if ARCH_BCM_IPROC
122*4882a593Smuzhiyun	help
123*4882a593Smuzhiyun	  Enable support for Broadcom SBA RAID Engine. The SBA RAID
124*4882a593Smuzhiyun	  engine is available on most of the Broadcom iProc SoCs. It
125*4882a593Smuzhiyun	  has the capability to offload memcpy, xor and pq computation
126*4882a593Smuzhiyun	  for raid5/6.
127*4882a593Smuzhiyun
128*4882a593Smuzhiyunconfig COH901318
129*4882a593Smuzhiyun	bool "ST-Ericsson COH901318 DMA support"
130*4882a593Smuzhiyun	select DMA_ENGINE
131*4882a593Smuzhiyun	depends on ARCH_U300 || COMPILE_TEST
132*4882a593Smuzhiyun	help
133*4882a593Smuzhiyun	  Enable support for ST-Ericsson COH 901 318 DMA.
134*4882a593Smuzhiyun
135*4882a593Smuzhiyunconfig DMA_BCM2835
136*4882a593Smuzhiyun	tristate "BCM2835 DMA engine support"
137*4882a593Smuzhiyun	depends on ARCH_BCM2835
138*4882a593Smuzhiyun	select DMA_ENGINE
139*4882a593Smuzhiyun	select DMA_VIRTUAL_CHANNELS
140*4882a593Smuzhiyun
141*4882a593Smuzhiyunconfig DMA_JZ4780
142*4882a593Smuzhiyun	tristate "JZ4780 DMA support"
143*4882a593Smuzhiyun	depends on MIPS || COMPILE_TEST
144*4882a593Smuzhiyun	select DMA_ENGINE
145*4882a593Smuzhiyun	select DMA_VIRTUAL_CHANNELS
146*4882a593Smuzhiyun	help
147*4882a593Smuzhiyun	  This selects support for the DMA controller in Ingenic JZ4780 SoCs.
148*4882a593Smuzhiyun	  If you have a board based on such a SoC and wish to use DMA for
149*4882a593Smuzhiyun	  devices which can use the DMA controller, say Y or M here.
150*4882a593Smuzhiyun
151*4882a593Smuzhiyunconfig DMA_SA11X0
152*4882a593Smuzhiyun	tristate "SA-11x0 DMA support"
153*4882a593Smuzhiyun	depends on ARCH_SA1100 || COMPILE_TEST
154*4882a593Smuzhiyun	select DMA_ENGINE
155*4882a593Smuzhiyun	select DMA_VIRTUAL_CHANNELS
156*4882a593Smuzhiyun	help
157*4882a593Smuzhiyun	  Support the DMA engine found on Intel StrongARM SA-1100 and
158*4882a593Smuzhiyun	  SA-1110 SoCs.  This DMA engine can only be used with on-chip
159*4882a593Smuzhiyun	  devices.
160*4882a593Smuzhiyun
161*4882a593Smuzhiyunconfig DMA_SUN4I
162*4882a593Smuzhiyun	tristate "Allwinner A10 DMA SoCs support"
163*4882a593Smuzhiyun	depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
164*4882a593Smuzhiyun	default (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
165*4882a593Smuzhiyun	select DMA_ENGINE
166*4882a593Smuzhiyun	select DMA_VIRTUAL_CHANNELS
167*4882a593Smuzhiyun	help
168*4882a593Smuzhiyun	  Enable support for the DMA controller present in the sun4i,
169*4882a593Smuzhiyun	  sun5i and sun7i Allwinner ARM SoCs.
170*4882a593Smuzhiyun
171*4882a593Smuzhiyunconfig DMA_SUN6I
172*4882a593Smuzhiyun	tristate "Allwinner A31 SoCs DMA support"
173*4882a593Smuzhiyun	depends on MACH_SUN6I || MACH_SUN8I || (ARM64 && ARCH_SUNXI) || COMPILE_TEST
174*4882a593Smuzhiyun	depends on RESET_CONTROLLER
175*4882a593Smuzhiyun	select DMA_ENGINE
176*4882a593Smuzhiyun	select DMA_VIRTUAL_CHANNELS
177*4882a593Smuzhiyun	help
178*4882a593Smuzhiyun	  Support for the DMA engine first found in Allwinner A31 SoCs.
179*4882a593Smuzhiyun
180*4882a593Smuzhiyunconfig DW_AXI_DMAC
181*4882a593Smuzhiyun	tristate "Synopsys DesignWare AXI DMA support"
182*4882a593Smuzhiyun	depends on OF || COMPILE_TEST
183*4882a593Smuzhiyun	select DMA_ENGINE
184*4882a593Smuzhiyun	select DMA_VIRTUAL_CHANNELS
185*4882a593Smuzhiyun	help
186*4882a593Smuzhiyun	  Enable support for Synopsys DesignWare AXI DMA controller.
187*4882a593Smuzhiyun	  NOTE: This driver wasn't tested on 64 bit platform because
188*4882a593Smuzhiyun	  of lack 64 bit platform with Synopsys DW AXI DMAC.
189*4882a593Smuzhiyun
190*4882a593Smuzhiyunconfig EP93XX_DMA
191*4882a593Smuzhiyun	bool "Cirrus Logic EP93xx DMA support"
192*4882a593Smuzhiyun	depends on ARCH_EP93XX || COMPILE_TEST
193*4882a593Smuzhiyun	select DMA_ENGINE
194*4882a593Smuzhiyun	help
195*4882a593Smuzhiyun	  Enable support for the Cirrus Logic EP93xx M2P/M2M DMA controller.
196*4882a593Smuzhiyun
197*4882a593Smuzhiyunconfig FSL_DMA
198*4882a593Smuzhiyun	tristate "Freescale Elo series DMA support"
199*4882a593Smuzhiyun	depends on FSL_SOC
200*4882a593Smuzhiyun	select DMA_ENGINE
201*4882a593Smuzhiyun	select ASYNC_TX_ENABLE_CHANNEL_SWITCH
202*4882a593Smuzhiyun	help
203*4882a593Smuzhiyun	  Enable support for the Freescale Elo series DMA controllers.
204*4882a593Smuzhiyun	  The Elo is the DMA controller on some mpc82xx and mpc83xx parts, the
205*4882a593Smuzhiyun	  EloPlus is on mpc85xx and mpc86xx and Pxxx parts, and the Elo3 is on
206*4882a593Smuzhiyun	  some Txxx and Bxxx parts.
207*4882a593Smuzhiyun
208*4882a593Smuzhiyunconfig FSL_EDMA
209*4882a593Smuzhiyun	tristate "Freescale eDMA engine support"
210*4882a593Smuzhiyun	depends on OF
211*4882a593Smuzhiyun	select DMA_ENGINE
212*4882a593Smuzhiyun	select DMA_VIRTUAL_CHANNELS
213*4882a593Smuzhiyun	help
214*4882a593Smuzhiyun	  Support the Freescale eDMA engine with programmable channel
215*4882a593Smuzhiyun	  multiplexing capability for DMA request sources(slot).
216*4882a593Smuzhiyun	  This module can be found on Freescale Vybrid and LS-1 SoCs.
217*4882a593Smuzhiyun
218*4882a593Smuzhiyunconfig FSL_QDMA
219*4882a593Smuzhiyun	tristate "NXP Layerscape qDMA engine support"
220*4882a593Smuzhiyun	depends on ARM || ARM64
221*4882a593Smuzhiyun	select DMA_ENGINE
222*4882a593Smuzhiyun	select DMA_VIRTUAL_CHANNELS
223*4882a593Smuzhiyun	select DMA_ENGINE_RAID
224*4882a593Smuzhiyun	select ASYNC_TX_ENABLE_CHANNEL_SWITCH
225*4882a593Smuzhiyun	help
226*4882a593Smuzhiyun	 Support the NXP Layerscape qDMA engine with command queue and legacy mode.
227*4882a593Smuzhiyun	 Channel virtualization is supported through enqueuing of DMA jobs to,
228*4882a593Smuzhiyun	 or dequeuing DMA jobs from, different work queues.
229*4882a593Smuzhiyun	 This module can be found on NXP Layerscape SoCs.
230*4882a593Smuzhiyun	  The qdma driver only work on  SoCs with a DPAA hardware block.
231*4882a593Smuzhiyun
232*4882a593Smuzhiyunconfig FSL_RAID
233*4882a593Smuzhiyun	tristate "Freescale RAID engine Support"
234*4882a593Smuzhiyun	depends on FSL_SOC && !ASYNC_TX_ENABLE_CHANNEL_SWITCH
235*4882a593Smuzhiyun	select DMA_ENGINE
236*4882a593Smuzhiyun	select DMA_ENGINE_RAID
237*4882a593Smuzhiyun	help
238*4882a593Smuzhiyun	  Enable support for Freescale RAID Engine. RAID Engine is
239*4882a593Smuzhiyun	  available on some QorIQ SoCs (like P5020/P5040). It has
240*4882a593Smuzhiyun	  the capability to offload memcpy, xor and pq computation
241*4882a593Smuzhiyun	  for raid5/6.
242*4882a593Smuzhiyun
243*4882a593Smuzhiyunconfig HISI_DMA
244*4882a593Smuzhiyun	tristate "HiSilicon DMA Engine support"
245*4882a593Smuzhiyun	depends on ARM64 || COMPILE_TEST
246*4882a593Smuzhiyun	depends on PCI_MSI
247*4882a593Smuzhiyun	select DMA_ENGINE
248*4882a593Smuzhiyun	select DMA_VIRTUAL_CHANNELS
249*4882a593Smuzhiyun	help
250*4882a593Smuzhiyun	  Support HiSilicon Kunpeng DMA engine.
251*4882a593Smuzhiyun
252*4882a593Smuzhiyunconfig IMG_MDC_DMA
253*4882a593Smuzhiyun	tristate "IMG MDC support"
254*4882a593Smuzhiyun	depends on MIPS || COMPILE_TEST
255*4882a593Smuzhiyun	depends on MFD_SYSCON
256*4882a593Smuzhiyun	select DMA_ENGINE
257*4882a593Smuzhiyun	select DMA_VIRTUAL_CHANNELS
258*4882a593Smuzhiyun	help
259*4882a593Smuzhiyun	  Enable support for the IMG multi-threaded DMA controller (MDC).
260*4882a593Smuzhiyun
261*4882a593Smuzhiyunconfig IMX_DMA
262*4882a593Smuzhiyun	tristate "i.MX DMA support"
263*4882a593Smuzhiyun	depends on ARCH_MXC
264*4882a593Smuzhiyun	select DMA_ENGINE
265*4882a593Smuzhiyun	help
266*4882a593Smuzhiyun	  Support the i.MX DMA engine. This engine is integrated into
267*4882a593Smuzhiyun	  Freescale i.MX1/21/27 chips.
268*4882a593Smuzhiyun
269*4882a593Smuzhiyunconfig IMX_SDMA
270*4882a593Smuzhiyun	tristate "i.MX SDMA support"
271*4882a593Smuzhiyun	depends on ARCH_MXC
272*4882a593Smuzhiyun	select DMA_ENGINE
273*4882a593Smuzhiyun	select DMA_VIRTUAL_CHANNELS
274*4882a593Smuzhiyun	help
275*4882a593Smuzhiyun	  Support the i.MX SDMA engine. This engine is integrated into
276*4882a593Smuzhiyun	  Freescale i.MX25/31/35/51/53/6 chips.
277*4882a593Smuzhiyun
278*4882a593Smuzhiyunconfig INTEL_IDMA64
279*4882a593Smuzhiyun	tristate "Intel integrated DMA 64-bit support"
280*4882a593Smuzhiyun	select DMA_ENGINE
281*4882a593Smuzhiyun	select DMA_VIRTUAL_CHANNELS
282*4882a593Smuzhiyun	help
283*4882a593Smuzhiyun	  Enable DMA support for Intel Low Power Subsystem such as found on
284*4882a593Smuzhiyun	  Intel Skylake PCH.
285*4882a593Smuzhiyun
286*4882a593Smuzhiyunconfig INTEL_IDXD
287*4882a593Smuzhiyun	tristate "Intel Data Accelerators support"
288*4882a593Smuzhiyun	depends on PCI && X86_64 && !UML
289*4882a593Smuzhiyun	depends on PCI_MSI
290*4882a593Smuzhiyun	depends on SBITMAP
291*4882a593Smuzhiyun	select DMA_ENGINE
292*4882a593Smuzhiyun	help
293*4882a593Smuzhiyun	  Enable support for the Intel(R) data accelerators present
294*4882a593Smuzhiyun	  in Intel Xeon CPU.
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun	  Say Y if you have such a platform.
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun	  If unsure, say N.
299*4882a593Smuzhiyun
300*4882a593Smuzhiyunconfig INTEL_IOATDMA
301*4882a593Smuzhiyun	tristate "Intel I/OAT DMA support"
302*4882a593Smuzhiyun	depends on PCI && X86_64 && !UML
303*4882a593Smuzhiyun	select DMA_ENGINE
304*4882a593Smuzhiyun	select DMA_ENGINE_RAID
305*4882a593Smuzhiyun	select DCA
306*4882a593Smuzhiyun	help
307*4882a593Smuzhiyun	  Enable support for the Intel(R) I/OAT DMA engine present
308*4882a593Smuzhiyun	  in recent Intel Xeon chipsets.
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun	  Say Y here if you have such a chipset.
311*4882a593Smuzhiyun
312*4882a593Smuzhiyun	  If unsure, say N.
313*4882a593Smuzhiyun
314*4882a593Smuzhiyunconfig INTEL_IOP_ADMA
315*4882a593Smuzhiyun	tristate "Intel IOP32x ADMA support"
316*4882a593Smuzhiyun	depends on ARCH_IOP32X || COMPILE_TEST
317*4882a593Smuzhiyun	select DMA_ENGINE
318*4882a593Smuzhiyun	select ASYNC_TX_ENABLE_CHANNEL_SWITCH
319*4882a593Smuzhiyun	help
320*4882a593Smuzhiyun	  Enable support for the Intel(R) IOP Series RAID engines.
321*4882a593Smuzhiyun
322*4882a593Smuzhiyunconfig K3_DMA
323*4882a593Smuzhiyun	tristate "Hisilicon K3 DMA support"
324*4882a593Smuzhiyun	depends on ARCH_HI3xxx || ARCH_HISI || COMPILE_TEST
325*4882a593Smuzhiyun	select DMA_ENGINE
326*4882a593Smuzhiyun	select DMA_VIRTUAL_CHANNELS
327*4882a593Smuzhiyun	help
328*4882a593Smuzhiyun	  Support the DMA engine for Hisilicon K3 platform
329*4882a593Smuzhiyun	  devices.
330*4882a593Smuzhiyun
331*4882a593Smuzhiyunconfig LPC18XX_DMAMUX
332*4882a593Smuzhiyun	bool "NXP LPC18xx/43xx DMA MUX for PL080"
333*4882a593Smuzhiyun	depends on ARCH_LPC18XX || COMPILE_TEST
334*4882a593Smuzhiyun	depends on OF && AMBA_PL08X
335*4882a593Smuzhiyun	select MFD_SYSCON
336*4882a593Smuzhiyun	help
337*4882a593Smuzhiyun	  Enable support for DMA on NXP LPC18xx/43xx platforms
338*4882a593Smuzhiyun	  with PL080 and multiplexed DMA request lines.
339*4882a593Smuzhiyun
340*4882a593Smuzhiyunconfig MCF_EDMA
341*4882a593Smuzhiyun	tristate "Freescale eDMA engine support, ColdFire mcf5441x SoCs"
342*4882a593Smuzhiyun	depends on M5441x || COMPILE_TEST
343*4882a593Smuzhiyun	select DMA_ENGINE
344*4882a593Smuzhiyun	select DMA_VIRTUAL_CHANNELS
345*4882a593Smuzhiyun	help
346*4882a593Smuzhiyun	  Support the Freescale ColdFire eDMA engine, 64-channel
347*4882a593Smuzhiyun	  implementation that performs complex data transfers with
348*4882a593Smuzhiyun	  minimal intervention from a host processor.
349*4882a593Smuzhiyun	  This module can be found on Freescale ColdFire mcf5441x SoCs.
350*4882a593Smuzhiyun
351*4882a593Smuzhiyunconfig MILBEAUT_HDMAC
352*4882a593Smuzhiyun	tristate "Milbeaut AHB DMA support"
353*4882a593Smuzhiyun	depends on ARCH_MILBEAUT || COMPILE_TEST
354*4882a593Smuzhiyun	depends on OF
355*4882a593Smuzhiyun	select DMA_ENGINE
356*4882a593Smuzhiyun	select DMA_VIRTUAL_CHANNELS
357*4882a593Smuzhiyun	help
358*4882a593Smuzhiyun	  Say yes here to support the Socionext Milbeaut
359*4882a593Smuzhiyun	  HDMAC device.
360*4882a593Smuzhiyun
361*4882a593Smuzhiyunconfig MILBEAUT_XDMAC
362*4882a593Smuzhiyun	tristate "Milbeaut AXI DMA support"
363*4882a593Smuzhiyun	depends on ARCH_MILBEAUT || COMPILE_TEST
364*4882a593Smuzhiyun	depends on OF
365*4882a593Smuzhiyun	select DMA_ENGINE
366*4882a593Smuzhiyun	select DMA_VIRTUAL_CHANNELS
367*4882a593Smuzhiyun	help
368*4882a593Smuzhiyun	  Say yes here to support the Socionext Milbeaut
369*4882a593Smuzhiyun	  XDMAC device.
370*4882a593Smuzhiyun
371*4882a593Smuzhiyunconfig MMP_PDMA
372*4882a593Smuzhiyun	bool "MMP PDMA support"
373*4882a593Smuzhiyun	depends on ARCH_MMP || ARCH_PXA || COMPILE_TEST
374*4882a593Smuzhiyun	select DMA_ENGINE
375*4882a593Smuzhiyun	help
376*4882a593Smuzhiyun	  Support the MMP PDMA engine for PXA and MMP platform.
377*4882a593Smuzhiyun
378*4882a593Smuzhiyunconfig MMP_TDMA
379*4882a593Smuzhiyun	bool "MMP Two-Channel DMA support"
380*4882a593Smuzhiyun	depends on ARCH_MMP || COMPILE_TEST
381*4882a593Smuzhiyun	select DMA_ENGINE
382*4882a593Smuzhiyun	select GENERIC_ALLOCATOR
383*4882a593Smuzhiyun	help
384*4882a593Smuzhiyun	  Support the MMP Two-Channel DMA engine.
385*4882a593Smuzhiyun	  This engine used for MMP Audio DMA and pxa910 SQU.
386*4882a593Smuzhiyun
387*4882a593Smuzhiyunconfig MOXART_DMA
388*4882a593Smuzhiyun	tristate "MOXART DMA support"
389*4882a593Smuzhiyun	depends on ARCH_MOXART
390*4882a593Smuzhiyun	select DMA_ENGINE
391*4882a593Smuzhiyun	select DMA_VIRTUAL_CHANNELS
392*4882a593Smuzhiyun	help
393*4882a593Smuzhiyun	  Enable support for the MOXA ART SoC DMA controller.
394*4882a593Smuzhiyun
395*4882a593Smuzhiyun	  Say Y here if you enabled MMP ADMA, otherwise say N.
396*4882a593Smuzhiyun
397*4882a593Smuzhiyunconfig MPC512X_DMA
398*4882a593Smuzhiyun	tristate "Freescale MPC512x built-in DMA engine support"
399*4882a593Smuzhiyun	depends on PPC_MPC512x || PPC_MPC831x
400*4882a593Smuzhiyun	select DMA_ENGINE
401*4882a593Smuzhiyun	help
402*4882a593Smuzhiyun	  Enable support for the Freescale MPC512x built-in DMA engine.
403*4882a593Smuzhiyun
404*4882a593Smuzhiyunconfig MV_XOR
405*4882a593Smuzhiyun	bool "Marvell XOR engine support"
406*4882a593Smuzhiyun	depends on PLAT_ORION || ARCH_MVEBU || COMPILE_TEST
407*4882a593Smuzhiyun	select DMA_ENGINE
408*4882a593Smuzhiyun	select DMA_ENGINE_RAID
409*4882a593Smuzhiyun	select ASYNC_TX_ENABLE_CHANNEL_SWITCH
410*4882a593Smuzhiyun	help
411*4882a593Smuzhiyun	  Enable support for the Marvell XOR engine.
412*4882a593Smuzhiyun
413*4882a593Smuzhiyunconfig MV_XOR_V2
414*4882a593Smuzhiyun	bool "Marvell XOR engine version 2 support "
415*4882a593Smuzhiyun	depends on ARM64
416*4882a593Smuzhiyun	select DMA_ENGINE
417*4882a593Smuzhiyun	select DMA_ENGINE_RAID
418*4882a593Smuzhiyun	select ASYNC_TX_ENABLE_CHANNEL_SWITCH
419*4882a593Smuzhiyun	select GENERIC_MSI_IRQ_DOMAIN
420*4882a593Smuzhiyun	help
421*4882a593Smuzhiyun	  Enable support for the Marvell version 2 XOR engine.
422*4882a593Smuzhiyun
423*4882a593Smuzhiyun	  This engine provides acceleration for copy, XOR and RAID6
424*4882a593Smuzhiyun	  operations, and is available on Marvell Armada 7K and 8K
425*4882a593Smuzhiyun	  platforms.
426*4882a593Smuzhiyun
427*4882a593Smuzhiyunconfig MXS_DMA
428*4882a593Smuzhiyun	bool "MXS DMA support"
429*4882a593Smuzhiyun	depends on ARCH_MXS || ARCH_MXC || COMPILE_TEST
430*4882a593Smuzhiyun	select STMP_DEVICE
431*4882a593Smuzhiyun	select DMA_ENGINE
432*4882a593Smuzhiyun	help
433*4882a593Smuzhiyun	  Support the MXS DMA engine. This engine including APBH-DMA
434*4882a593Smuzhiyun	  and APBX-DMA is integrated into some Freescale chips.
435*4882a593Smuzhiyun
436*4882a593Smuzhiyunconfig MX3_IPU
437*4882a593Smuzhiyun	bool "MX3x Image Processing Unit support"
438*4882a593Smuzhiyun	depends on ARCH_MXC
439*4882a593Smuzhiyun	select DMA_ENGINE
440*4882a593Smuzhiyun	default y
441*4882a593Smuzhiyun	help
442*4882a593Smuzhiyun	  If you plan to use the Image Processing unit in the i.MX3x, say
443*4882a593Smuzhiyun	  Y here. If unsure, select Y.
444*4882a593Smuzhiyun
445*4882a593Smuzhiyunconfig MX3_IPU_IRQS
446*4882a593Smuzhiyun	int "Number of dynamically mapped interrupts for IPU"
447*4882a593Smuzhiyun	depends on MX3_IPU
448*4882a593Smuzhiyun	range 2 137
449*4882a593Smuzhiyun	default 4
450*4882a593Smuzhiyun	help
451*4882a593Smuzhiyun	  Out of 137 interrupt sources on i.MX31 IPU only very few are used.
452*4882a593Smuzhiyun	  To avoid bloating the irq_desc[] array we allocate a sufficient
453*4882a593Smuzhiyun	  number of IRQ slots and map them dynamically to specific sources.
454*4882a593Smuzhiyun
455*4882a593Smuzhiyunconfig NBPFAXI_DMA
456*4882a593Smuzhiyun	tristate "Renesas Type-AXI NBPF DMA support"
457*4882a593Smuzhiyun	select DMA_ENGINE
458*4882a593Smuzhiyun	depends on ARM || COMPILE_TEST
459*4882a593Smuzhiyun	help
460*4882a593Smuzhiyun	  Support for "Type-AXI" NBPF DMA IPs from Renesas
461*4882a593Smuzhiyun
462*4882a593Smuzhiyunconfig OWL_DMA
463*4882a593Smuzhiyun	tristate "Actions Semi Owl SoCs DMA support"
464*4882a593Smuzhiyun	depends on ARCH_ACTIONS
465*4882a593Smuzhiyun	select DMA_ENGINE
466*4882a593Smuzhiyun	select DMA_VIRTUAL_CHANNELS
467*4882a593Smuzhiyun	help
468*4882a593Smuzhiyun	  Enable support for the Actions Semi Owl SoCs DMA controller.
469*4882a593Smuzhiyun
470*4882a593Smuzhiyunconfig PCH_DMA
471*4882a593Smuzhiyun	tristate "Intel EG20T PCH / LAPIS Semicon IOH(ML7213/ML7223/ML7831) DMA"
472*4882a593Smuzhiyun	depends on PCI && (X86_32 || COMPILE_TEST)
473*4882a593Smuzhiyun	select DMA_ENGINE
474*4882a593Smuzhiyun	help
475*4882a593Smuzhiyun	  Enable support for Intel EG20T PCH DMA engine.
476*4882a593Smuzhiyun
477*4882a593Smuzhiyun	  This driver also can be used for LAPIS Semiconductor IOH(Input/
478*4882a593Smuzhiyun	  Output Hub), ML7213, ML7223 and ML7831.
479*4882a593Smuzhiyun	  ML7213 IOH is for IVI(In-Vehicle Infotainment) use, ML7223 IOH is
480*4882a593Smuzhiyun	  for MP(Media Phone) use and ML7831 IOH is for general purpose use.
481*4882a593Smuzhiyun	  ML7213/ML7223/ML7831 is companion chip for Intel Atom E6xx series.
482*4882a593Smuzhiyun	  ML7213/ML7223/ML7831 is completely compatible for Intel EG20T PCH.
483*4882a593Smuzhiyun
484*4882a593Smuzhiyunconfig PL330_DMA
485*4882a593Smuzhiyun	tristate "DMA API Driver for PL330"
486*4882a593Smuzhiyun	select DMA_ENGINE
487*4882a593Smuzhiyun	depends on ARM_AMBA
488*4882a593Smuzhiyun	help
489*4882a593Smuzhiyun	  Select if your platform has one or more PL330 DMACs.
490*4882a593Smuzhiyun	  You need to provide platform specific settings via
491*4882a593Smuzhiyun	  platform_data for a dma-pl330 device.
492*4882a593Smuzhiyun
493*4882a593Smuzhiyunconfig PXA_DMA
494*4882a593Smuzhiyun	bool "PXA DMA support"
495*4882a593Smuzhiyun	depends on (ARCH_MMP || ARCH_PXA)
496*4882a593Smuzhiyun	select DMA_ENGINE
497*4882a593Smuzhiyun	select DMA_VIRTUAL_CHANNELS
498*4882a593Smuzhiyun	help
499*4882a593Smuzhiyun	  Support the DMA engine for PXA. It is also compatible with MMP PDMA
500*4882a593Smuzhiyun	  platform. The internal DMA IP of all PXA variants is supported, with
501*4882a593Smuzhiyun	  16 to 32 channels for peripheral to memory or memory to memory
502*4882a593Smuzhiyun	  transfers.
503*4882a593Smuzhiyun
504*4882a593Smuzhiyunconfig PLX_DMA
505*4882a593Smuzhiyun	tristate "PLX ExpressLane PEX Switch DMA Engine Support"
506*4882a593Smuzhiyun	depends on PCI
507*4882a593Smuzhiyun	select DMA_ENGINE
508*4882a593Smuzhiyun	help
509*4882a593Smuzhiyun	  Some PLX ExpressLane PCI Switches support additional DMA engines.
510*4882a593Smuzhiyun	  These are exposed via extra functions on the switch's
511*4882a593Smuzhiyun	  upstream port. Each function exposes one DMA channel.
512*4882a593Smuzhiyun
513*4882a593Smuzhiyunconfig SIRF_DMA
514*4882a593Smuzhiyun	tristate "CSR SiRFprimaII/SiRFmarco DMA support"
515*4882a593Smuzhiyun	depends on ARCH_SIRF
516*4882a593Smuzhiyun	select DMA_ENGINE
517*4882a593Smuzhiyun	help
518*4882a593Smuzhiyun	  Enable support for the CSR SiRFprimaII DMA engine.
519*4882a593Smuzhiyun
520*4882a593Smuzhiyunconfig STE_DMA40
521*4882a593Smuzhiyun	bool "ST-Ericsson DMA40 support"
522*4882a593Smuzhiyun	depends on ARCH_U8500
523*4882a593Smuzhiyun	select DMA_ENGINE
524*4882a593Smuzhiyun	help
525*4882a593Smuzhiyun	  Support for ST-Ericsson DMA40 controller
526*4882a593Smuzhiyun
527*4882a593Smuzhiyunconfig ST_FDMA
528*4882a593Smuzhiyun	tristate "ST FDMA dmaengine support"
529*4882a593Smuzhiyun	depends on ARCH_STI
530*4882a593Smuzhiyun	depends on REMOTEPROC
531*4882a593Smuzhiyun	select ST_SLIM_REMOTEPROC
532*4882a593Smuzhiyun	select DMA_ENGINE
533*4882a593Smuzhiyun	select DMA_VIRTUAL_CHANNELS
534*4882a593Smuzhiyun	help
535*4882a593Smuzhiyun	  Enable support for ST FDMA controller.
536*4882a593Smuzhiyun	  It supports 16 independent DMA channels, accepts up to 32 DMA requests
537*4882a593Smuzhiyun
538*4882a593Smuzhiyun	  Say Y here if you have such a chipset.
539*4882a593Smuzhiyun	  If unsure, say N.
540*4882a593Smuzhiyun
541*4882a593Smuzhiyunconfig STM32_DMA
542*4882a593Smuzhiyun	bool "STMicroelectronics STM32 DMA support"
543*4882a593Smuzhiyun	depends on ARCH_STM32 || COMPILE_TEST
544*4882a593Smuzhiyun	select DMA_ENGINE
545*4882a593Smuzhiyun	select DMA_VIRTUAL_CHANNELS
546*4882a593Smuzhiyun	help
547*4882a593Smuzhiyun	  Enable support for the on-chip DMA controller on STMicroelectronics
548*4882a593Smuzhiyun	  STM32 MCUs.
549*4882a593Smuzhiyun	  If you have a board based on such a MCU and wish to use DMA say Y
550*4882a593Smuzhiyun	  here.
551*4882a593Smuzhiyun
552*4882a593Smuzhiyunconfig STM32_DMAMUX
553*4882a593Smuzhiyun	bool "STMicroelectronics STM32 dma multiplexer support"
554*4882a593Smuzhiyun	depends on STM32_DMA || COMPILE_TEST
555*4882a593Smuzhiyun	help
556*4882a593Smuzhiyun	  Enable support for the on-chip DMA multiplexer on STMicroelectronics
557*4882a593Smuzhiyun	  STM32 MCUs.
558*4882a593Smuzhiyun	  If you have a board based on such a MCU and wish to use DMAMUX say Y
559*4882a593Smuzhiyun	  here.
560*4882a593Smuzhiyun
561*4882a593Smuzhiyunconfig STM32_MDMA
562*4882a593Smuzhiyun	bool "STMicroelectronics STM32 master dma support"
563*4882a593Smuzhiyun	depends on ARCH_STM32 || COMPILE_TEST
564*4882a593Smuzhiyun	depends on OF
565*4882a593Smuzhiyun	select DMA_ENGINE
566*4882a593Smuzhiyun	select DMA_VIRTUAL_CHANNELS
567*4882a593Smuzhiyun	help
568*4882a593Smuzhiyun	  Enable support for the on-chip MDMA controller on STMicroelectronics
569*4882a593Smuzhiyun	  STM32 platforms.
570*4882a593Smuzhiyun	  If you have a board based on STM32 SoC and wish to use the master DMA
571*4882a593Smuzhiyun	  say Y here.
572*4882a593Smuzhiyun
573*4882a593Smuzhiyunconfig SPRD_DMA
574*4882a593Smuzhiyun	tristate "Spreadtrum DMA support"
575*4882a593Smuzhiyun	depends on ARCH_SPRD || COMPILE_TEST
576*4882a593Smuzhiyun	select DMA_ENGINE
577*4882a593Smuzhiyun	select DMA_VIRTUAL_CHANNELS
578*4882a593Smuzhiyun	help
579*4882a593Smuzhiyun	  Enable support for the on-chip DMA controller on Spreadtrum platform.
580*4882a593Smuzhiyun
581*4882a593Smuzhiyunconfig S3C24XX_DMAC
582*4882a593Smuzhiyun	bool "Samsung S3C24XX DMA support"
583*4882a593Smuzhiyun	depends on ARCH_S3C24XX || COMPILE_TEST
584*4882a593Smuzhiyun	select DMA_ENGINE
585*4882a593Smuzhiyun	select DMA_VIRTUAL_CHANNELS
586*4882a593Smuzhiyun	help
587*4882a593Smuzhiyun	  Support for the Samsung S3C24XX DMA controller driver. The
588*4882a593Smuzhiyun	  DMA controller is having multiple DMA channels which can be
589*4882a593Smuzhiyun	  configured for different peripherals like audio, UART, SPI.
590*4882a593Smuzhiyun	  The DMA controller can transfer data from memory to peripheral,
591*4882a593Smuzhiyun	  periphal to memory, periphal to periphal and memory to memory.
592*4882a593Smuzhiyun
593*4882a593Smuzhiyunconfig TXX9_DMAC
594*4882a593Smuzhiyun	tristate "Toshiba TXx9 SoC DMA support"
595*4882a593Smuzhiyun	depends on MACH_TX49XX || MACH_TX39XX
596*4882a593Smuzhiyun	select DMA_ENGINE
597*4882a593Smuzhiyun	help
598*4882a593Smuzhiyun	  Support the TXx9 SoC internal DMA controller.  This can be
599*4882a593Smuzhiyun	  integrated in chips such as the Toshiba TX4927/38/39.
600*4882a593Smuzhiyun
601*4882a593Smuzhiyunconfig TEGRA20_APB_DMA
602*4882a593Smuzhiyun	tristate "NVIDIA Tegra20 APB DMA support"
603*4882a593Smuzhiyun	depends on ARCH_TEGRA || COMPILE_TEST
604*4882a593Smuzhiyun	select DMA_ENGINE
605*4882a593Smuzhiyun	help
606*4882a593Smuzhiyun	  Support for the NVIDIA Tegra20 APB DMA controller driver. The
607*4882a593Smuzhiyun	  DMA controller is having multiple DMA channel which can be
608*4882a593Smuzhiyun	  configured for different peripherals like audio, UART, SPI,
609*4882a593Smuzhiyun	  I2C etc which is in APB bus.
610*4882a593Smuzhiyun	  This DMA controller transfers data from memory to peripheral fifo
611*4882a593Smuzhiyun	  or vice versa. It does not support memory to memory data transfer.
612*4882a593Smuzhiyun
613*4882a593Smuzhiyunconfig TEGRA210_ADMA
614*4882a593Smuzhiyun	tristate "NVIDIA Tegra210 ADMA support"
615*4882a593Smuzhiyun	depends on (ARCH_TEGRA_210_SOC || COMPILE_TEST)
616*4882a593Smuzhiyun	select DMA_ENGINE
617*4882a593Smuzhiyun	select DMA_VIRTUAL_CHANNELS
618*4882a593Smuzhiyun	help
619*4882a593Smuzhiyun	  Support for the NVIDIA Tegra210 ADMA controller driver. The
620*4882a593Smuzhiyun	  DMA controller has multiple DMA channels and is used to service
621*4882a593Smuzhiyun	  various audio clients in the Tegra210 audio processing engine
622*4882a593Smuzhiyun	  (APE). This DMA controller transfers data from memory to
623*4882a593Smuzhiyun	  peripheral and vice versa. It does not support memory to
624*4882a593Smuzhiyun	  memory data transfer.
625*4882a593Smuzhiyun
626*4882a593Smuzhiyunconfig TIMB_DMA
627*4882a593Smuzhiyun	tristate "Timberdale FPGA DMA support"
628*4882a593Smuzhiyun	depends on MFD_TIMBERDALE || COMPILE_TEST
629*4882a593Smuzhiyun	select DMA_ENGINE
630*4882a593Smuzhiyun	help
631*4882a593Smuzhiyun	  Enable support for the Timberdale FPGA DMA engine.
632*4882a593Smuzhiyun
633*4882a593Smuzhiyunconfig UNIPHIER_MDMAC
634*4882a593Smuzhiyun	tristate "UniPhier MIO DMAC"
635*4882a593Smuzhiyun	depends on ARCH_UNIPHIER || COMPILE_TEST
636*4882a593Smuzhiyun	depends on OF
637*4882a593Smuzhiyun	select DMA_ENGINE
638*4882a593Smuzhiyun	select DMA_VIRTUAL_CHANNELS
639*4882a593Smuzhiyun	help
640*4882a593Smuzhiyun	  Enable support for the MIO DMAC (Media I/O DMA controller) on the
641*4882a593Smuzhiyun	  UniPhier platform.  This DMA controller is used as the external
642*4882a593Smuzhiyun	  DMA engine of the SD/eMMC controllers of the LD4, Pro4, sLD8 SoCs.
643*4882a593Smuzhiyun
644*4882a593Smuzhiyunconfig UNIPHIER_XDMAC
645*4882a593Smuzhiyun	tristate "UniPhier XDMAC support"
646*4882a593Smuzhiyun	depends on ARCH_UNIPHIER || COMPILE_TEST
647*4882a593Smuzhiyun	depends on OF
648*4882a593Smuzhiyun	select DMA_ENGINE
649*4882a593Smuzhiyun	select DMA_VIRTUAL_CHANNELS
650*4882a593Smuzhiyun	help
651*4882a593Smuzhiyun	  Enable support for the XDMAC (external DMA controller) on the
652*4882a593Smuzhiyun	  UniPhier platform. This DMA controller can transfer data from
653*4882a593Smuzhiyun	  memory to memory, memory to peripheral and peripheral to memory.
654*4882a593Smuzhiyun
655*4882a593Smuzhiyunconfig XGENE_DMA
656*4882a593Smuzhiyun	tristate "APM X-Gene DMA support"
657*4882a593Smuzhiyun	depends on ARCH_XGENE || COMPILE_TEST
658*4882a593Smuzhiyun	select DMA_ENGINE
659*4882a593Smuzhiyun	select DMA_ENGINE_RAID
660*4882a593Smuzhiyun	select ASYNC_TX_ENABLE_CHANNEL_SWITCH
661*4882a593Smuzhiyun	help
662*4882a593Smuzhiyun	  Enable support for the APM X-Gene SoC DMA engine.
663*4882a593Smuzhiyun
664*4882a593Smuzhiyunconfig XILINX_DMA
665*4882a593Smuzhiyun	tristate "Xilinx AXI DMAS Engine"
666*4882a593Smuzhiyun	depends on (ARCH_ZYNQ || MICROBLAZE || ARM64)
667*4882a593Smuzhiyun	select DMA_ENGINE
668*4882a593Smuzhiyun	help
669*4882a593Smuzhiyun	  Enable support for Xilinx AXI VDMA Soft IP.
670*4882a593Smuzhiyun
671*4882a593Smuzhiyun	  AXI VDMA engine provides high-bandwidth direct memory access
672*4882a593Smuzhiyun	  between memory and AXI4-Stream video type target
673*4882a593Smuzhiyun	  peripherals including peripherals which support AXI4-
674*4882a593Smuzhiyun	  Stream Video Protocol.  It has two stream interfaces/
675*4882a593Smuzhiyun	  channels, Memory Mapped to Stream (MM2S) and Stream to
676*4882a593Smuzhiyun	  Memory Mapped (S2MM) for the data transfers.
677*4882a593Smuzhiyun	  AXI CDMA engine provides high-bandwidth direct memory access
678*4882a593Smuzhiyun	  between a memory-mapped source address and a memory-mapped
679*4882a593Smuzhiyun	  destination address.
680*4882a593Smuzhiyun	  AXI DMA engine provides high-bandwidth one dimensional direct
681*4882a593Smuzhiyun	  memory access between memory and AXI4-Stream target peripherals.
682*4882a593Smuzhiyun	  AXI MCDMA engine provides high-bandwidth direct memory access
683*4882a593Smuzhiyun	  between memory and AXI4-Stream target peripherals. It provides
684*4882a593Smuzhiyun	  the scatter gather interface with multiple channels independent
685*4882a593Smuzhiyun	  configuration support.
686*4882a593Smuzhiyun
687*4882a593Smuzhiyunconfig XILINX_ZYNQMP_DMA
688*4882a593Smuzhiyun	tristate "Xilinx ZynqMP DMA Engine"
689*4882a593Smuzhiyun	depends on (ARCH_ZYNQ || MICROBLAZE || ARM64)
690*4882a593Smuzhiyun	select DMA_ENGINE
691*4882a593Smuzhiyun	help
692*4882a593Smuzhiyun	  Enable support for Xilinx ZynqMP DMA controller.
693*4882a593Smuzhiyun
694*4882a593Smuzhiyunconfig XILINX_ZYNQMP_DPDMA
695*4882a593Smuzhiyun	tristate "Xilinx DPDMA Engine"
696*4882a593Smuzhiyun	depends on HAS_IOMEM && OF
697*4882a593Smuzhiyun	select DMA_ENGINE
698*4882a593Smuzhiyun	select DMA_VIRTUAL_CHANNELS
699*4882a593Smuzhiyun	help
700*4882a593Smuzhiyun	  Enable support for Xilinx ZynqMP DisplayPort DMA. Choose this option
701*4882a593Smuzhiyun	  if you have a Xilinx ZynqMP SoC with a DisplayPort subsystem. The
702*4882a593Smuzhiyun	  driver provides the dmaengine required by the DisplayPort subsystem
703*4882a593Smuzhiyun	  display driver.
704*4882a593Smuzhiyun
705*4882a593Smuzhiyunconfig ZX_DMA
706*4882a593Smuzhiyun	tristate "ZTE ZX DMA support"
707*4882a593Smuzhiyun	depends on ARCH_ZX || COMPILE_TEST
708*4882a593Smuzhiyun	select DMA_ENGINE
709*4882a593Smuzhiyun	select DMA_VIRTUAL_CHANNELS
710*4882a593Smuzhiyun	help
711*4882a593Smuzhiyun	  Support the DMA engine for ZTE ZX family platform devices.
712*4882a593Smuzhiyun
713*4882a593Smuzhiyun
714*4882a593Smuzhiyun# driver files
715*4882a593Smuzhiyunsource "drivers/dma/bestcomm/Kconfig"
716*4882a593Smuzhiyun
717*4882a593Smuzhiyunsource "drivers/dma/mediatek/Kconfig"
718*4882a593Smuzhiyun
719*4882a593Smuzhiyunsource "drivers/dma/qcom/Kconfig"
720*4882a593Smuzhiyun
721*4882a593Smuzhiyunsource "drivers/dma/dw/Kconfig"
722*4882a593Smuzhiyun
723*4882a593Smuzhiyunsource "drivers/dma/dw-edma/Kconfig"
724*4882a593Smuzhiyun
725*4882a593Smuzhiyunsource "drivers/dma/hsu/Kconfig"
726*4882a593Smuzhiyun
727*4882a593Smuzhiyunsource "drivers/dma/sf-pdma/Kconfig"
728*4882a593Smuzhiyun
729*4882a593Smuzhiyunsource "drivers/dma/sh/Kconfig"
730*4882a593Smuzhiyun
731*4882a593Smuzhiyunsource "drivers/dma/ti/Kconfig"
732*4882a593Smuzhiyun
733*4882a593Smuzhiyunsource "drivers/dma/fsl-dpaa2-qdma/Kconfig"
734*4882a593Smuzhiyun
735*4882a593Smuzhiyun# clients
736*4882a593Smuzhiyuncomment "DMA Clients"
737*4882a593Smuzhiyun	depends on DMA_ENGINE
738*4882a593Smuzhiyun
739*4882a593Smuzhiyunconfig ASYNC_TX_DMA
740*4882a593Smuzhiyun	bool "Async_tx: Offload support for the async_tx api"
741*4882a593Smuzhiyun	depends on DMA_ENGINE
742*4882a593Smuzhiyun	help
743*4882a593Smuzhiyun	  This allows the async_tx api to take advantage of offload engines for
744*4882a593Smuzhiyun	  memcpy, memset, xor, and raid6 p+q operations.  If your platform has
745*4882a593Smuzhiyun	  a dma engine that can perform raid operations and you have enabled
746*4882a593Smuzhiyun	  MD_RAID456 say Y.
747*4882a593Smuzhiyun
748*4882a593Smuzhiyun	  If unsure, say N.
749*4882a593Smuzhiyun
750*4882a593Smuzhiyunconfig DMATEST
751*4882a593Smuzhiyun	tristate "DMA Test client"
752*4882a593Smuzhiyun	depends on DMA_ENGINE
753*4882a593Smuzhiyun	select DMA_ENGINE_RAID
754*4882a593Smuzhiyun	help
755*4882a593Smuzhiyun	  Simple DMA test client. Say N unless you're debugging a
756*4882a593Smuzhiyun	  DMA Device driver.
757*4882a593Smuzhiyun
758*4882a593Smuzhiyunconfig DMA_ENGINE_RAID
759*4882a593Smuzhiyun	bool
760*4882a593Smuzhiyun
761*4882a593Smuzhiyunendif
762