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/OK3568_Linux_fs/kernel/arch/arm/mach-davinci/
H A Dsleep.S12 #include "ddr2.h"
34 * r0: contains virtual base for DDR2 controller
35 * r1: contains virtual base for DDR2 Power and Sleep controller (PSC)
36 * r2: contains PSC number for DDR2
37 * r3: contains virtual base DDR2 PLL controller
66 /* Disable DDR2 LPSC */
138 /* Start 2x clock to DDR2 */
146 /* Enable DDR2 LPSC */
168 * Disables or Enables DDR2 LPSC
171 * r1: contains virtual base for DDR2 Power and Sleep controller (PSC)
[all …]
/OK3568_Linux_fs/u-boot/board/atmel/sama5d3_xplained/
H A Dsama5d3_xplained.c124 static void ddr2_conf(struct atmel_mpddrc_config *ddr2) in ddr2_conf() argument
126 ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); in ddr2_conf()
128 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | in ddr2_conf()
137 * As the DDR2-SDRAm device requires a refresh time is 7.8125us in ddr2_conf()
140 ddr2->rtr = 0x411; in ddr2_conf()
142 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | in ddr2_conf()
151 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | in ddr2_conf()
156 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | in ddr2_conf()
165 struct atmel_mpddrc_config ddr2; in mem_init() local
167 ddr2_conf(&ddr2); in mem_init()
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/OK3568_Linux_fs/u-boot/board/atmel/at91sam9n12ek/
H A Dat91sam9n12ek.c237 static void ddr2_conf(struct atmel_mpddrc_config *ddr2) in ddr2_conf() argument
239 ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); in ddr2_conf()
241 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | in ddr2_conf()
247 ddr2->rtr = 0x411; in ddr2_conf()
249 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | in ddr2_conf()
258 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | in ddr2_conf()
263 ddr2->tpr2 = (2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | in ddr2_conf()
273 struct atmel_mpddrc_config ddr2; in mem_init() local
276 ddr2_conf(&ddr2); in mem_init()
278 /* enable DDR2 clock */ in mem_init()
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/OK3568_Linux_fs/u-boot/board/atmel/at91sam9x5ek/
H A Dat91sam9x5ek.c246 static void ddr2_conf(struct atmel_mpddrc_config *ddr2) in ddr2_conf() argument
248 ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); in ddr2_conf()
250 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | in ddr2_conf()
256 ddr2->rtr = 0x411; in ddr2_conf()
258 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | in ddr2_conf()
267 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | in ddr2_conf()
272 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | in ddr2_conf()
283 struct atmel_mpddrc_config ddr2; in mem_init() local
286 ddr2_conf(&ddr2); in mem_init()
288 /* enable DDR2 clock */ in mem_init()
[all …]
/OK3568_Linux_fs/u-boot/board/mini-box/picosam9g45/
H A Dpicosam9g45.c50 static void ddr2_conf(struct atmel_mpddrc_config *ddr2) in ddr2_conf() argument
52 ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); in ddr2_conf()
54 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | in ddr2_conf()
59 ddr2->rtr = 0x24b; in ddr2_conf()
61 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */ in ddr2_conf()
70 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */ in ddr2_conf()
75 ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | in ddr2_conf()
84 struct atmel_mpddrc_config ddr2; in mem_init() local
87 ddr2_conf(&ddr2); in mem_init()
91 /* Chip select 1 is for DDR2/SDRAM */ in mem_init()
[all …]
/OK3568_Linux_fs/u-boot/board/siemens/corvus/
H A Dboard.c137 static void ddr2_conf(struct atmel_mpddrc_config *ddr2) in ddr2_conf() argument
139 ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); in ddr2_conf()
141 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | in ddr2_conf()
146 ddr2->rtr = 0x24b; in ddr2_conf()
148 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */ in ddr2_conf()
157 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */ in ddr2_conf()
162 ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | in ddr2_conf()
170 struct atmel_mpddrc_config ddr2; in mem_init() local
172 ddr2_conf(&ddr2); in mem_init()
177 ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2); in mem_init()
/OK3568_Linux_fs/u-boot/board/atmel/sama5d3xek/
H A Dsama5d3xek.c285 static void ddr2_conf(struct atmel_mpddrc_config *ddr2) in ddr2_conf() argument
287 ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); in ddr2_conf()
289 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | in ddr2_conf()
298 * As the DDR2-SDRAm device requires a refresh time is 7.8125us in ddr2_conf()
301 ddr2->rtr = 0x411; in ddr2_conf()
303 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | in ddr2_conf()
312 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | in ddr2_conf()
317 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | in ddr2_conf()
326 struct atmel_mpddrc_config ddr2; in mem_init() local
328 ddr2_conf(&ddr2); in mem_init()
[all …]
/OK3568_Linux_fs/u-boot/board/atmel/sama5d4ek/
H A Dsama5d4ek.c225 static void ddr2_conf(struct atmel_mpddrc_config *ddr2) in ddr2_conf() argument
227 ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); in ddr2_conf()
229 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | in ddr2_conf()
236 ddr2->rtr = 0x2b0; in ddr2_conf()
238 ddr2->tpr0 = (8 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | in ddr2_conf()
247 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | in ddr2_conf()
252 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | in ddr2_conf()
261 struct atmel_mpddrc_config ddr2; in mem_init() local
265 ddr2_conf(&ddr2); in mem_init()
285 ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2); in mem_init()
/OK3568_Linux_fs/u-boot/board/atmel/at91sam9m10g45ek/
H A Dat91sam9m10g45ek.c95 static void ddr2_conf(struct atmel_mpddrc_config *ddr2) in ddr2_conf() argument
97 ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); in ddr2_conf()
99 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | in ddr2_conf()
104 ddr2->rtr = 0x24b; in ddr2_conf()
106 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */ in ddr2_conf()
115 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */ in ddr2_conf()
120 ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | in ddr2_conf()
128 struct atmel_mpddrc_config ddr2; in mem_init() local
130 ddr2_conf(&ddr2); in mem_init()
135 ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2); in mem_init()
/OK3568_Linux_fs/u-boot/board/atmel/sama5d4_xplained/
H A Dsama5d4_xplained.c229 static void ddr2_conf(struct atmel_mpddrc_config *ddr2) in ddr2_conf() argument
231 ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); in ddr2_conf()
233 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | in ddr2_conf()
241 ddr2->rtr = 0x2b0; in ddr2_conf()
243 ddr2->tpr0 = (8 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | in ddr2_conf()
252 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | in ddr2_conf()
257 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | in ddr2_conf()
266 struct atmel_mpddrc_config ddr2; in mem_init() local
268 ddr2_conf(&ddr2); in mem_init()
275 ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2); in mem_init()
/OK3568_Linux_fs/u-boot/board/xes/xpedite537x/
H A Dddr.c39 * Usually only needed with heavy load/very high speed (>DDR2-800)
41 * ====== XPedite5370 DDR2-600 read delay calculations ======
84 * ====== XPedite5370 DDR2-800 read delay calculations ======
144 * period at DDR2-600 or DDR2-800, so no additional delay is needed over
166 /* DDR2 600/667 */
174 /* DDR2 800 */
185 /* DDR2 600/667 */
193 /* DDR2 800 */
/OK3568_Linux_fs/u-boot/arch/arm/mach-at91/include/mach/
H A Dsama5d4.h184 #define H64MX_SLAVE_DDRC_PORT0 3 /* DDR2 Port0-AESOTF */
185 #define H64MX_SLAVE_DDRC_PORT1 4 /* DDR2 Port1 */
186 #define H64MX_SLAVE_DDRC_PORT2 5 /* DDR2 Port2 */
187 #define H64MX_SLAVE_DDRC_PORT3 6 /* DDR2 Port3 */
188 #define H64MX_SLAVE_DDRC_PORT4 7 /* DDR2 Port4 */
189 #define H64MX_SLAVE_DDRC_PORT5 8 /* DDR2 Port5 */
190 #define H64MX_SLAVE_DDRC_PORT6 9 /* DDR2 Port6 */
191 #define H64MX_SLAVE_DDRC_PORT7 10 /* DDR2 Port7 */
H A Dsama5d2.h188 #define H64MX_SLAVE_DDRC_PORT0 2 /* DDR2 Port0-AESOTF */
189 #define H64MX_SLAVE_DDRC_PORT1 3 /* DDR2 Port1 */
190 #define H64MX_SLAVE_DDRC_PORT2 4 /* DDR2 Port2 */
191 #define H64MX_SLAVE_DDRC_PORT3 5 /* DDR2 Port3 */
192 #define H64MX_SLAVE_DDRC_PORT4 6 /* DDR2 Port4 */
193 #define H64MX_SLAVE_DDRC_PORT5 7 /* DDR2 Port5 */
194 #define H64MX_SLAVE_DDRC_PORT6 8 /* DDR2 Port6 */
195 #define H64MX_SLAVE_DDRC_PORT7 9 /* DDR2 Port7 */
/OK3568_Linux_fs/u-boot/board/xes/xpedite517x/
H A Dddr.c38 * Usually only needed with heavy load/very high speed (>DDR2-800)
56 /* DDR2 600/667 */
64 /* DDR2 800 */
75 /* DDR2 600/667 */
83 /* DDR2 800 */
/OK3568_Linux_fs/kernel/arch/mips/ralink/
H A Drt3883.c68 u32 ddr2; in ralink_clk_init() local
73 ddr2 = syscfg0 & RT3883_SYSCFG0_DRAM_TYPE_DDR2; in ralink_clk_init()
78 sys_rate = (ddr2) ? 125000000 : 83000000; in ralink_clk_init()
82 sys_rate = (ddr2) ? 128000000 : 96000000; in ralink_clk_init()
86 sys_rate = (ddr2) ? 160000000 : 120000000; in ralink_clk_init()
90 sys_rate = (ddr2) ? 166000000 : 125000000; in ralink_clk_init()
/OK3568_Linux_fs/u-boot/board/aries/ma5d4evk/
H A Dma5d4evk.c388 static void ddr2_conf(struct atmel_mpddrc_config *ddr2) in ddr2_conf() argument
390 ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); in ddr2_conf()
392 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | in ddr2_conf()
399 ddr2->rtr = 0x2b0; in ddr2_conf()
401 ddr2->tpr0 = (8 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | in ddr2_conf()
410 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | in ddr2_conf()
415 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | in ddr2_conf()
425 struct atmel_mpddrc_config ddr2; in mem_init() local
427 ddr2_conf(&ddr2); in mem_init()
434 ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2); in mem_init()
/OK3568_Linux_fs/u-boot/cmd/
H A Di2c.c1154 enum { unknown, EDO, SDRAM, DDR, DDR2, DDR3, DDR4 } type; in do_sdram() enumerator
1256 type = DDR2; in do_sdram()
1257 puts ("DDR2\n"); in do_sdram()
1286 case DDR2: in do_sdram()
1296 case DDR2: in do_sdram()
1317 case DDR2: in do_sdram()
1328 case DDR2: in do_sdram()
1362 case DDR2: in do_sdram()
1375 case DDR2: in do_sdram()
1392 if (DDR2 != type) { in do_sdram()
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-davinci/
H A Dlowlevel_init.S97 * DDR2 PLL Initialization *
230 /* Shut down the DDR2 LPSC Module */
251 /* Check for DDR2 Controller Enable Completion */
260 * Program DDR2 MMRs for 162MHz Setting *
299 /* Issue a Dummy DDR2 read/write */
305 /* Shut down the DDR2 LPSC Module */
326 /* Check for DDR2 Controller Enable Completion */
335 * Turn DDR2 Controller Clocks On *
338 /* Enable the DDR2 LPSC Module */
357 /* Check for DDR2 Controller Enable Completion */
[all …]
/OK3568_Linux_fs/kernel/drivers/edac/
H A Dppc4xx_edac.c24 * associated with the IMB DDR2 ECC controller found in the AMCC/IBM
29 * - Support for registered- and non-registered DDR1 and DDR2 memory.
85 * - Denali DDR1/DDR2 (440EPX and 440GRX) "denali,sdram-4xx-ddr2"
139 * The ibm,sdram-4xx-ddr2 Device Control Registers (DCRs) are
193 .compatible = "ibm,sdram-4xx-ddr2"
657 * status registers that deal with ibm,sdram-4xx-ddr2 ECC errors.
685 * ibm,sdram-4xx-ddr2 ECC errors.
708 * This routine handles an ibm,sdram-4xx-ddr2 controller ECC
739 * This routine handles an ibm,sdram-4xx-ddr2 controller ECC
765 * associated with the ibm,sdram-4xx-ddr2 controller being
[all …]
/OK3568_Linux_fs/u-boot/drivers/ddr/fsl/
H A DKconfig68 Enable Freescale DDR2 controller.
74 Enable Freescale DDR2 controller for MPC86xx SoCs.
124 bool "Freescale DDR2 controller"
/OK3568_Linux_fs/u-boot/board/xes/xpedite520x/
H A Dddr.c18 * The SPD has an unspecified dimm type, but the DDR2 initialization in get_spd()
35 * - DDR1 vs. DDR2? in fsl_ddr_board_options()
47 * - ddr1 vs. ddr2 in fsl_ddr_board_options()
/OK3568_Linux_fs/u-boot/arch/arm/cpu/arm1136/mx35/
H A Dmx35_sdram.c66 /* Initialize MISC register for DDR2 */ in mx3_setup_sdram_bank()
74 * according to DDR2 specs, wait a while before in mx3_setup_sdram_bank()
79 /* Load DDR2 config and timing */ in mx3_setup_sdram_bank()
/OK3568_Linux_fs/u-boot/arch/mips/mach-pic32/
H A Dcpu.c103 /* Un-gate DDR2 modules (gated by default) */
112 /* initialize the DDR2 Controller and DDR2 PHY */
/OK3568_Linux_fs/u-boot/drivers/ddr/microchip/
H A Dddr2.c17 /* init DDR2 Phy */
64 /* DDR2 Controller initialization */
111 /* init DDR2 Controller */
121 /* PIC32 DDR2 controller always work in HALF_RATE */ in ddr2_ctrl_init()
267 printf("ddr2: phy calib failed\n"); in ddr2_ctrl_init()
/OK3568_Linux_fs/u-boot/board/sbc8548/
H A Dddr.c21 * - DDR1 vs. DDR2? in fsl_ddr_board_options()
33 * - ddr1 vs. ddr2 in fsl_ddr_board_options()
88 * Assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed.

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