1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2009 Extreme Engineering Solutions, Inc.
3*4882a593Smuzhiyun * Copyright 2007-2008 Freescale Semiconductor, Inc.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <common.h>
9*4882a593Smuzhiyun #include <i2c.h>
10*4882a593Smuzhiyun #include <fsl_ddr_sdram.h>
11*4882a593Smuzhiyun #include <fsl_ddr_dimm_params.h>
12*4882a593Smuzhiyun
get_spd(ddr2_spd_eeprom_t * spd,u8 i2c_address)13*4882a593Smuzhiyun void get_spd(ddr2_spd_eeprom_t *spd, u8 i2c_address)
14*4882a593Smuzhiyun {
15*4882a593Smuzhiyun i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd,
16*4882a593Smuzhiyun sizeof(ddr2_spd_eeprom_t));
17*4882a593Smuzhiyun }
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun /*
20*4882a593Smuzhiyun * There are four board-specific SDRAM timing parameters which must be
21*4882a593Smuzhiyun * calculated based on the particular PCB artwork. These are:
22*4882a593Smuzhiyun * 1.) CPO (Read Capture Delay)
23*4882a593Smuzhiyun * - TIMING_CFG_2 register
24*4882a593Smuzhiyun * Source: Calculation based on board trace lengths and
25*4882a593Smuzhiyun * chip-specific internal delays.
26*4882a593Smuzhiyun * 2.) WR_DATA_DELAY (Write Command to Data Strobe Delay)
27*4882a593Smuzhiyun * - TIMING_CFG_2 register
28*4882a593Smuzhiyun * Source: Calculation based on board trace lengths.
29*4882a593Smuzhiyun * Unless clock and DQ lanes are very different
30*4882a593Smuzhiyun * lengths (>2"), this should be set to the nominal value
31*4882a593Smuzhiyun * of 1/2 clock delay.
32*4882a593Smuzhiyun * 3.) CLK_ADJUST (Clock and Addr/Cmd alignment control)
33*4882a593Smuzhiyun * - DDR_SDRAM_CLK_CNTL register
34*4882a593Smuzhiyun * Source: Signal Integrity Simulations
35*4882a593Smuzhiyun * 4.) 2T Timing on Addr/Ctl
36*4882a593Smuzhiyun * - TIMING_CFG_2 register
37*4882a593Smuzhiyun * Source: Signal Integrity Simulations
38*4882a593Smuzhiyun * Usually only needed with heavy load/very high speed (>DDR2-800)
39*4882a593Smuzhiyun *
40*4882a593Smuzhiyun * PCB routing on the XPedite5170 is nearly identical to the XPedite5370
41*4882a593Smuzhiyun * so we use the XPedite5370 settings as a basis for the XPedite5170.
42*4882a593Smuzhiyun */
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun typedef struct board_memctl_options {
45*4882a593Smuzhiyun uint16_t datarate_mhz_low;
46*4882a593Smuzhiyun uint16_t datarate_mhz_high;
47*4882a593Smuzhiyun uint8_t clk_adjust;
48*4882a593Smuzhiyun uint8_t cpo_override;
49*4882a593Smuzhiyun uint8_t write_data_delay;
50*4882a593Smuzhiyun } board_memctl_options_t;
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun static struct board_memctl_options bopts_ctrl[][2] = {
53*4882a593Smuzhiyun {
54*4882a593Smuzhiyun /* Controller 0 */
55*4882a593Smuzhiyun {
56*4882a593Smuzhiyun /* DDR2 600/667 */
57*4882a593Smuzhiyun .datarate_mhz_low = 500,
58*4882a593Smuzhiyun .datarate_mhz_high = 750,
59*4882a593Smuzhiyun .clk_adjust = 5,
60*4882a593Smuzhiyun .cpo_override = 8,
61*4882a593Smuzhiyun .write_data_delay = 2,
62*4882a593Smuzhiyun },
63*4882a593Smuzhiyun {
64*4882a593Smuzhiyun /* DDR2 800 */
65*4882a593Smuzhiyun .datarate_mhz_low = 750,
66*4882a593Smuzhiyun .datarate_mhz_high = 850,
67*4882a593Smuzhiyun .clk_adjust = 5,
68*4882a593Smuzhiyun .cpo_override = 9,
69*4882a593Smuzhiyun .write_data_delay = 2,
70*4882a593Smuzhiyun },
71*4882a593Smuzhiyun },
72*4882a593Smuzhiyun {
73*4882a593Smuzhiyun /* Controller 1 */
74*4882a593Smuzhiyun {
75*4882a593Smuzhiyun /* DDR2 600/667 */
76*4882a593Smuzhiyun .datarate_mhz_low = 500,
77*4882a593Smuzhiyun .datarate_mhz_high = 750,
78*4882a593Smuzhiyun .clk_adjust = 5,
79*4882a593Smuzhiyun .cpo_override = 7,
80*4882a593Smuzhiyun .write_data_delay = 2,
81*4882a593Smuzhiyun },
82*4882a593Smuzhiyun {
83*4882a593Smuzhiyun /* DDR2 800 */
84*4882a593Smuzhiyun .datarate_mhz_low = 750,
85*4882a593Smuzhiyun .datarate_mhz_high = 850,
86*4882a593Smuzhiyun .clk_adjust = 5,
87*4882a593Smuzhiyun .cpo_override = 8,
88*4882a593Smuzhiyun .write_data_delay = 2,
89*4882a593Smuzhiyun },
90*4882a593Smuzhiyun },
91*4882a593Smuzhiyun };
92*4882a593Smuzhiyun
fsl_ddr_board_options(memctl_options_t * popts,dimm_params_t * pdimm,unsigned int ctrl_num)93*4882a593Smuzhiyun void fsl_ddr_board_options(memctl_options_t *popts,
94*4882a593Smuzhiyun dimm_params_t *pdimm,
95*4882a593Smuzhiyun unsigned int ctrl_num)
96*4882a593Smuzhiyun {
97*4882a593Smuzhiyun struct board_memctl_options *bopts = bopts_ctrl[ctrl_num];
98*4882a593Smuzhiyun sys_info_t sysinfo;
99*4882a593Smuzhiyun int i;
100*4882a593Smuzhiyun unsigned int datarate;
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun get_sys_info(&sysinfo);
103*4882a593Smuzhiyun datarate = get_ddr_freq(0) / 1000000;
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(bopts_ctrl[ctrl_num]); i++) {
106*4882a593Smuzhiyun if ((bopts[i].datarate_mhz_low <= datarate) &&
107*4882a593Smuzhiyun (bopts[i].datarate_mhz_high >= datarate)) {
108*4882a593Smuzhiyun debug("controller %d:\n", ctrl_num);
109*4882a593Smuzhiyun debug(" clk_adjust = %d\n", bopts[i].clk_adjust);
110*4882a593Smuzhiyun debug(" cpo = %d\n", bopts[i].cpo_override);
111*4882a593Smuzhiyun debug(" write_data_delay = %d\n",
112*4882a593Smuzhiyun bopts[i].write_data_delay);
113*4882a593Smuzhiyun popts->clk_adjust = bopts[i].clk_adjust;
114*4882a593Smuzhiyun popts->cpo_override = bopts[i].cpo_override;
115*4882a593Smuzhiyun popts->write_data_delay = bopts[i].write_data_delay;
116*4882a593Smuzhiyun }
117*4882a593Smuzhiyun }
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun /*
120*4882a593Smuzhiyun * Factors to consider for half-strength driver enable:
121*4882a593Smuzhiyun * - number of DIMMs installed
122*4882a593Smuzhiyun */
123*4882a593Smuzhiyun popts->half_strength_driver_enable = 0;
124*4882a593Smuzhiyun }
125