1 /*
2 * Copyright (C) 2015 Marek Vasut <marex@denx.de>
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 #include <common.h>
8 #include <asm/io.h>
9 #include <asm/arch/at91_common.h>
10 #include <asm/arch/at91_pmc.h>
11 #include <asm/arch/at91_rstc.h>
12 #include <asm/arch/atmel_mpddrc.h>
13 #include <asm/arch/atmel_usba_udc.h>
14 #include <asm/arch/gpio.h>
15 #include <asm/arch/clk.h>
16 #include <asm/arch/sama5d3_smc.h>
17 #include <asm/arch/sama5d4.h>
18 #include <atmel_hlcdc.h>
19 #include <atmel_mci.h>
20 #include <lcd.h>
21 #include <mmc.h>
22 #include <net.h>
23 #include <netdev.h>
24 #include <spi.h>
25 #include <spi_flash.h>
26 #include <spl.h>
27 #include <version.h>
28
29 DECLARE_GLOBAL_DATA_PTR;
30
31 static u8 boot_mode_sf;
32
33 #ifdef CONFIG_ATMEL_SPI
spi_cs_is_valid(unsigned int bus,unsigned int cs)34 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
35 {
36 return bus == 0 && cs == 0;
37 }
38
spi_cs_activate(struct spi_slave * slave)39 void spi_cs_activate(struct spi_slave *slave)
40 {
41 at91_set_pio_output(AT91_PIO_PORTC, 3, 0);
42 }
43
spi_cs_deactivate(struct spi_slave * slave)44 void spi_cs_deactivate(struct spi_slave *slave)
45 {
46 at91_set_pio_output(AT91_PIO_PORTC, 3, 1);
47 }
48
ma5d4evk_spi0_hw_init(void)49 static void ma5d4evk_spi0_hw_init(void)
50 {
51 at91_pio3_set_a_periph(AT91_PIO_PORTC, 0, 0); /* SPI0_MISO */
52 at91_pio3_set_a_periph(AT91_PIO_PORTC, 1, 0); /* SPI0_MOSI */
53 at91_pio3_set_a_periph(AT91_PIO_PORTC, 2, 0); /* SPI0_SPCK */
54
55 at91_set_pio_output(AT91_PIO_PORTC, 3, 1); /* SPI0_CS0 */
56
57 /* Enable clock */
58 at91_periph_clk_enable(ATMEL_ID_SPI0);
59 }
60 #endif /* CONFIG_ATMEL_SPI */
61
62 #ifdef CONFIG_CMD_USB
ma5d4evk_usb_hw_init(void)63 static void ma5d4evk_usb_hw_init(void)
64 {
65 at91_set_pio_output(AT91_PIO_PORTE, 11, 0);
66 at91_set_pio_output(AT91_PIO_PORTE, 14, 0);
67 }
68 #endif
69
70 #ifdef CONFIG_LCD
71 vidinfo_t panel_info = {
72 .vl_col = 800,
73 .vl_row = 480,
74 .vl_clk = 33500000,
75 .vl_bpix = LCD_BPP,
76 .vl_tft = 1,
77 .vl_hsync_len = 10,
78 .vl_left_margin = 89,
79 .vl_right_margin = 164,
80 .vl_vsync_len = 10,
81 .vl_upper_margin = 23,
82 .vl_lower_margin = 10,
83 .mmio = ATMEL_BASE_LCDC,
84 };
85
86 /* No power up/down pin for the LCD pannel */
lcd_enable(void)87 void lcd_enable(void) { /* Empty! */ }
lcd_disable(void)88 void lcd_disable(void) { /* Empty! */ }
89
has_lcdc(void)90 unsigned int has_lcdc(void)
91 {
92 return 1;
93 }
94
ma5d4evk_lcd_hw_init(void)95 static void ma5d4evk_lcd_hw_init(void)
96 {
97 at91_pio3_set_a_periph(AT91_PIO_PORTA, 24, 1); /* LCDPWM */
98 at91_pio3_set_a_periph(AT91_PIO_PORTA, 25, 0); /* LCDDISP */
99 at91_pio3_set_a_periph(AT91_PIO_PORTA, 26, 0); /* LCDVSYNC */
100 at91_pio3_set_a_periph(AT91_PIO_PORTA, 27, 0); /* LCDHSYNC */
101 at91_pio3_set_a_periph(AT91_PIO_PORTA, 28, 0); /* LCDDOTCK */
102 at91_pio3_set_a_periph(AT91_PIO_PORTA, 29, 1); /* LCDDEN */
103
104 at91_pio3_set_a_periph(AT91_PIO_PORTA, 0, 0); /* LCDD0 */
105 at91_pio3_set_a_periph(AT91_PIO_PORTA, 1, 0); /* LCDD1 */
106 at91_pio3_set_a_periph(AT91_PIO_PORTA, 2, 0); /* LCDD2 */
107 at91_pio3_set_a_periph(AT91_PIO_PORTA, 3, 0); /* LCDD3 */
108 at91_pio3_set_a_periph(AT91_PIO_PORTA, 4, 0); /* LCDD4 */
109 at91_pio3_set_a_periph(AT91_PIO_PORTA, 5, 0); /* LCDD5 */
110 at91_pio3_set_a_periph(AT91_PIO_PORTA, 6, 0); /* LCDD6 */
111 at91_pio3_set_a_periph(AT91_PIO_PORTA, 7, 0); /* LCDD7 */
112
113 at91_pio3_set_a_periph(AT91_PIO_PORTA, 8, 0); /* LCDD9 */
114 at91_pio3_set_a_periph(AT91_PIO_PORTA, 9, 0); /* LCDD8 */
115 at91_pio3_set_a_periph(AT91_PIO_PORTA, 10, 0); /* LCDD10 */
116 at91_pio3_set_a_periph(AT91_PIO_PORTA, 11, 0); /* LCDD11 */
117 at91_pio3_set_a_periph(AT91_PIO_PORTA, 12, 0); /* LCDD12 */
118 at91_pio3_set_a_periph(AT91_PIO_PORTA, 13, 0); /* LCDD13 */
119 at91_pio3_set_a_periph(AT91_PIO_PORTA, 14, 0); /* LCDD14 */
120 at91_pio3_set_a_periph(AT91_PIO_PORTA, 15, 0); /* LCDD15 */
121
122 at91_pio3_set_a_periph(AT91_PIO_PORTA, 16, 0); /* LCDD16 */
123 at91_pio3_set_a_periph(AT91_PIO_PORTA, 17, 0); /* LCDD17 */
124 at91_pio3_set_a_periph(AT91_PIO_PORTA, 18, 0); /* LCDD18 */
125 at91_pio3_set_a_periph(AT91_PIO_PORTA, 19, 0); /* LCDD19 */
126 at91_pio3_set_a_periph(AT91_PIO_PORTA, 20, 0); /* LCDD20 */
127 at91_pio3_set_a_periph(AT91_PIO_PORTA, 21, 0); /* LCDD21 */
128 at91_pio3_set_a_periph(AT91_PIO_PORTA, 22, 0); /* LCDD22 */
129 at91_pio3_set_a_periph(AT91_PIO_PORTA, 23, 0); /* LCDD23 */
130
131 /* Enable clock */
132 at91_periph_clk_enable(ATMEL_ID_LCDC);
133 }
134
135 #endif /* CONFIG_LCD */
136
137 #ifdef CONFIG_GENERIC_ATMEL_MCI
138 /* On-SoM eMMC */
ma5d4evk_mci0_hw_init(void)139 void ma5d4evk_mci0_hw_init(void)
140 {
141 at91_pio3_set_b_periph(AT91_PIO_PORTC, 5, 1); /* MCI1 CDA */
142 at91_pio3_set_b_periph(AT91_PIO_PORTC, 6, 1); /* MCI1 DA0 */
143 at91_pio3_set_b_periph(AT91_PIO_PORTC, 7, 1); /* MCI1 DA1 */
144 at91_pio3_set_b_periph(AT91_PIO_PORTC, 8, 1); /* MCI1 DA2 */
145 at91_pio3_set_b_periph(AT91_PIO_PORTC, 9, 1); /* MCI1 DA3 */
146 at91_pio3_set_b_periph(AT91_PIO_PORTC, 10, 1); /* MCI1 DA4 */
147 at91_pio3_set_b_periph(AT91_PIO_PORTC, 11, 1); /* MCI1 DA5 */
148 at91_pio3_set_b_periph(AT91_PIO_PORTC, 12, 1); /* MCI1 DA6 */
149 at91_pio3_set_b_periph(AT91_PIO_PORTC, 13, 1); /* MCI1 DA7 */
150 at91_pio3_set_b_periph(AT91_PIO_PORTC, 4, 0); /* MCI1 CLK */
151
152 /*
153 * As the mci io internal pull down is too strong, so if the io needs
154 * external pull up, the pull up resistor will be very small, if so
155 * the power consumption will increase, so disable the internal pull
156 * down to save the power.
157 */
158 at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 5, 0);
159 at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 6, 0);
160 at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 7, 0);
161 at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 8, 0);
162 at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 9, 0);
163 at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 10, 0);
164 at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 11, 0);
165 at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 12, 0);
166 at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 13, 0);
167 at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 4, 0);
168
169 /* Enable clock */
170 at91_periph_clk_enable(ATMEL_ID_MCI0);
171 }
172
173 /* On-board MicroSD slot */
ma5d4evk_mci1_hw_init(void)174 void ma5d4evk_mci1_hw_init(void)
175 {
176 at91_pio3_set_c_periph(AT91_PIO_PORTE, 19, 1); /* MCI1 CDA */
177 at91_pio3_set_c_periph(AT91_PIO_PORTE, 20, 1); /* MCI1 DA0 */
178 at91_pio3_set_c_periph(AT91_PIO_PORTE, 21, 1); /* MCI1 DA1 */
179 at91_pio3_set_c_periph(AT91_PIO_PORTE, 22, 1); /* MCI1 DA2 */
180 at91_pio3_set_c_periph(AT91_PIO_PORTE, 23, 1); /* MCI1 DA3 */
181 at91_pio3_set_c_periph(AT91_PIO_PORTE, 18, 0); /* MCI1 CLK */
182
183 /*
184 * As the mci io internal pull down is too strong, so if the io needs
185 * external pull up, the pull up resistor will be very small, if so
186 * the power consumption will increase, so disable the internal pull
187 * down to save the power.
188 */
189 at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 18, 0);
190 at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 19, 0);
191 at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 20, 0);
192 at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 21, 0);
193 at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 22, 0);
194 at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 23, 0);
195
196 /* Deal with WP pin on the microSD slot. */
197 at91_set_pio_output(AT91_PIO_PORTE, 16, 0);
198 at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 16, 1);
199
200 /* Enable clock */
201 at91_periph_clk_enable(ATMEL_ID_MCI1);
202 }
203
board_mmc_init(bd_t * bis)204 int board_mmc_init(bd_t *bis)
205 {
206 int ret;
207 void *mci0 = (void *)ATMEL_BASE_MCI0;
208 void *mci1 = (void *)ATMEL_BASE_MCI1;
209
210 /* De-assert reset on On-SoM eMMC */
211 at91_set_pio_output(AT91_PIO_PORTE, 15, 1);
212 at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 15, 0);
213
214 ret = atmel_mci_init(boot_mode_sf ? mci0 : mci1);
215 if (ret) /* eMMC init failed, skip it. */
216 at91_set_pio_output(AT91_PIO_PORTE, 15, 0);
217
218 /* Enable the power supply to On-board MicroSD */
219 at91_set_pio_output(AT91_PIO_PORTE, 17, 0);
220 ret = atmel_mci_init(boot_mode_sf ? mci1 : mci0);
221 if (ret) /* uSD init failed, power it down. */
222 at91_set_pio_output(AT91_PIO_PORTE, 17, 1);
223
224 return 0;
225 }
226 #endif /* CONFIG_GENERIC_ATMEL_MCI */
227
228 #ifdef CONFIG_MACB
ma5d4evk_macb0_hw_init(void)229 void ma5d4evk_macb0_hw_init(void)
230 {
231 at91_pio3_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ETXCK_EREFCK */
232 at91_pio3_set_a_periph(AT91_PIO_PORTB, 6, 0); /* ERXDV */
233 at91_pio3_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ERX0 */
234 at91_pio3_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ERX1 */
235 at91_pio3_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ERXER */
236 at91_pio3_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ETXEN */
237 at91_pio3_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX0 */
238 at91_pio3_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ETX1 */
239 at91_pio3_set_a_periph(AT91_PIO_PORTB, 17, 0); /* EMDIO */
240 at91_pio3_set_a_periph(AT91_PIO_PORTB, 16, 0); /* EMDC */
241
242 /* Enable clock */
243 at91_periph_clk_enable(ATMEL_ID_GMAC0);
244 }
245 #endif
246
ma5d4evk_serial_hw_init(void)247 static void ma5d4evk_serial_hw_init(void)
248 {
249 /* USART0 */
250 at91_pio3_set_a_periph(AT91_PIO_PORTD, 13, 1); /* TXD */
251 at91_pio3_set_a_periph(AT91_PIO_PORTD, 12, 0); /* RXD */
252 at91_pio3_set_a_periph(AT91_PIO_PORTD, 11, 0); /* RTS */
253 at91_pio3_set_a_periph(AT91_PIO_PORTD, 10, 0); /* CTS */
254 at91_periph_clk_enable(ATMEL_ID_USART0);
255
256 /* USART1 */
257 at91_pio3_set_a_periph(AT91_PIO_PORTD, 17, 1); /* TXD */
258 at91_pio3_set_a_periph(AT91_PIO_PORTD, 16, 0); /* RXD */
259 at91_pio3_set_a_periph(AT91_PIO_PORTD, 15, 0); /* RTS */
260 at91_pio3_set_a_periph(AT91_PIO_PORTD, 14, 0); /* CTS */
261 at91_periph_clk_enable(ATMEL_ID_USART1);
262 }
263
board_early_init_f(void)264 int board_early_init_f(void)
265 {
266 at91_periph_clk_enable(ATMEL_ID_PIOA);
267 at91_periph_clk_enable(ATMEL_ID_PIOB);
268 at91_periph_clk_enable(ATMEL_ID_PIOC);
269 at91_periph_clk_enable(ATMEL_ID_PIOD);
270 at91_periph_clk_enable(ATMEL_ID_PIOE);
271
272 /* Configure LEDs as OFF */
273 at91_set_pio_output(AT91_PIO_PORTD, 28, 0);
274 at91_set_pio_output(AT91_PIO_PORTD, 29, 0);
275 at91_set_pio_output(AT91_PIO_PORTD, 30, 0);
276
277 ma5d4evk_serial_hw_init();
278
279 return 0;
280 }
281
board_identify(void)282 static void board_identify(void)
283 {
284 struct spi_flash *sf;
285 sf = spi_flash_probe(CONFIG_SF_DEFAULT_BUS, CONFIG_SF_DEFAULT_CS,
286 CONFIG_SF_DEFAULT_SPEED, CONFIG_SF_DEFAULT_MODE);
287 boot_mode_sf = (sf != NULL);
288 }
289
board_init(void)290 int board_init(void)
291 {
292 /* adress of boot parameters */
293 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
294
295 #ifdef CONFIG_ATMEL_SPI
296 ma5d4evk_spi0_hw_init();
297 #endif
298 #ifdef CONFIG_GENERIC_ATMEL_MCI
299 ma5d4evk_mci0_hw_init();
300 ma5d4evk_mci1_hw_init();
301 #endif
302 #ifdef CONFIG_MACB
303 ma5d4evk_macb0_hw_init();
304 #endif
305 #ifdef CONFIG_LCD
306 ma5d4evk_lcd_hw_init();
307 #endif
308 #ifdef CONFIG_CMD_USB
309 ma5d4evk_usb_hw_init();
310 #endif
311 #ifdef CONFIG_USB_GADGET_ATMEL_USBA
312 at91_udp_hw_init();
313 #endif
314
315 board_identify();
316
317 /* Reset CAN controllers */
318 at91_set_pio_output(AT91_PIO_PORTB, 21, 0);
319 udelay(100);
320 at91_set_pio_output(AT91_PIO_PORTB, 21, 1);
321 at91_pio3_set_pio_pulldown(AT91_PIO_PORTB, 21, 0);
322
323 return 0;
324 }
325
board_late_init(void)326 int board_late_init(void)
327 {
328 env_set("bootmode", boot_mode_sf ? "sf" : "emmc");
329 return 0;
330 }
331
dram_init(void)332 int dram_init(void)
333 {
334 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
335 CONFIG_SYS_SDRAM_SIZE);
336 return 0;
337 }
338
board_eth_init(bd_t * bis)339 int board_eth_init(bd_t *bis)
340 {
341 int rc = 0;
342
343 #ifdef CONFIG_MACB
344 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC0, 0x00);
345 #endif
346
347 #ifdef CONFIG_USB_GADGET_ATMEL_USBA
348 usba_udc_probe(&pdata);
349 #ifdef CONFIG_USB_ETH_RNDIS
350 usb_eth_initialize(bis);
351 #endif
352 #endif
353
354 return rc;
355 }
356
357 /* SPL */
358 #ifdef CONFIG_SPL_BUILD
spl_board_init(void)359 void spl_board_init(void)
360 {
361 #ifdef CONFIG_ATMEL_SPI
362 ma5d4evk_spi0_hw_init();
363 #endif
364 #ifdef CONFIG_GENERIC_ATMEL_MCI
365 ma5d4evk_mci0_hw_init();
366 ma5d4evk_mci1_hw_init();
367 #endif
368 board_identify();
369 }
370
board_boot_order(u32 * spl_boot_list)371 void board_boot_order(u32 *spl_boot_list)
372 {
373 spl_boot_list[0] = spl_boot_device();
374
375 switch (spl_boot_list[0]) {
376 case BOOT_DEVICE_MMC1:
377 case BOOT_DEVICE_MMC2:
378 spl_boot_list[0] = BOOT_DEVICE_MMC1;
379 break;
380 case BOOT_DEVICE_SPI:
381 break;
382 case BOOT_DEVICE_USB:
383 spl_boot_list[0] = BOOT_DEVICE_MMC2;
384 break;
385 }
386 }
387
ddr2_conf(struct atmel_mpddrc_config * ddr2)388 static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
389 {
390 ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
391
392 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
393 ATMEL_MPDDRC_CR_NR_ROW_13 |
394 ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
395 ATMEL_MPDDRC_CR_NB_8BANKS |
396 ATMEL_MPDDRC_CR_NDQS_DISABLED |
397 ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
398
399 ddr2->rtr = 0x2b0;
400
401 ddr2->tpr0 = (8 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
402 3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
403 3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
404 10 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
405 3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
406 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
407 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
408 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
409
410 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
411 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
412 25 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
413 23 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
414
415 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
416 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
417 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
418 2 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
419 8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
420 }
421
mem_init(void)422 void mem_init(void)
423 {
424 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
425 struct atmel_mpddrc_config ddr2;
426
427 ddr2_conf(&ddr2);
428
429 /* enable MPDDR clock */
430 at91_periph_clk_enable(ATMEL_ID_MPDDRC);
431 writel(AT91_PMC_DDR, &pmc->scer);
432
433 /* DDRAM2 Controller initialize */
434 ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
435 }
436
at91_pmc_init(void)437 void at91_pmc_init(void)
438 {
439 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
440 u32 tmp;
441
442 tmp = AT91_PMC_PLLAR_29 |
443 AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
444 AT91_PMC_PLLXR_MUL(87) |
445 AT91_PMC_PLLXR_DIV(1);
446 at91_plla_init(tmp);
447
448 writel(0x0 << 8, &pmc->pllicpr);
449
450 tmp = AT91_PMC_MCKR_H32MXDIV |
451 AT91_PMC_MCKR_PLLADIV_2 |
452 AT91_PMC_MCKR_MDIV_3 |
453 AT91_PMC_MCKR_CSS_PLLA;
454 at91_mck_init(tmp);
455 }
456 #endif
457