1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2012, Stefano Babic <sbabic@denx.de>
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <asm/io.h>
8*4882a593Smuzhiyun #include <linux/errno.h>
9*4882a593Smuzhiyun #include <asm/arch/imx-regs.h>
10*4882a593Smuzhiyun #include <linux/types.h>
11*4882a593Smuzhiyun #include <asm/arch/sys_proto.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #define ESDCTL_DDR2_EMR2 0x04000000
14*4882a593Smuzhiyun #define ESDCTL_DDR2_EMR3 0x06000000
15*4882a593Smuzhiyun #define ESDCTL_PRECHARGE 0x00000400
16*4882a593Smuzhiyun #define ESDCTL_DDR2_EN_DLL 0x02000400
17*4882a593Smuzhiyun #define ESDCTL_DDR2_RESET_DLL 0x00000333
18*4882a593Smuzhiyun #define ESDCTL_DDR2_MR 0x00000233
19*4882a593Smuzhiyun #define ESDCTL_DDR2_OCD_DEFAULT 0x02000780
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun enum {
22*4882a593Smuzhiyun SMODE_NORMAL = 0,
23*4882a593Smuzhiyun SMODE_PRECHARGE,
24*4882a593Smuzhiyun SMODE_AUTO_REFRESH,
25*4882a593Smuzhiyun SMODE_LOAD_REG,
26*4882a593Smuzhiyun SMODE_MANUAL_REFRESH
27*4882a593Smuzhiyun };
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun #define set_mode(x, en, m) (x | (en << 31) | (m << 28))
30*4882a593Smuzhiyun
dram_wait(unsigned int count)31*4882a593Smuzhiyun static inline void dram_wait(unsigned int count)
32*4882a593Smuzhiyun {
33*4882a593Smuzhiyun volatile unsigned int wait = count;
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun while (wait--)
36*4882a593Smuzhiyun ;
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun }
39*4882a593Smuzhiyun
mx3_setup_sdram_bank(u32 start_address,u32 ddr2_config,u32 row,u32 col,u32 dsize,u32 refresh)40*4882a593Smuzhiyun void mx3_setup_sdram_bank(u32 start_address, u32 ddr2_config,
41*4882a593Smuzhiyun u32 row, u32 col, u32 dsize, u32 refresh)
42*4882a593Smuzhiyun {
43*4882a593Smuzhiyun struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
44*4882a593Smuzhiyun u32 *cfg_reg, *ctl_reg;
45*4882a593Smuzhiyun u32 val;
46*4882a593Smuzhiyun u32 ctlval;
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun switch (start_address) {
49*4882a593Smuzhiyun case CSD0_BASE_ADDR:
50*4882a593Smuzhiyun cfg_reg = &esdc->esdcfg0;
51*4882a593Smuzhiyun ctl_reg = &esdc->esdctl0;
52*4882a593Smuzhiyun break;
53*4882a593Smuzhiyun case CSD1_BASE_ADDR:
54*4882a593Smuzhiyun cfg_reg = &esdc->esdcfg1;
55*4882a593Smuzhiyun ctl_reg = &esdc->esdctl1;
56*4882a593Smuzhiyun break;
57*4882a593Smuzhiyun default:
58*4882a593Smuzhiyun return;
59*4882a593Smuzhiyun }
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun /* The MX35 supports 11 up to 14 rows */
62*4882a593Smuzhiyun if (row < 11 || row > 14 || col < 8 || col > 10)
63*4882a593Smuzhiyun return;
64*4882a593Smuzhiyun ctlval = (row - 11) << 24 | (col - 8) << 20 | (dsize << 16);
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun /* Initialize MISC register for DDR2 */
67*4882a593Smuzhiyun val = ESDC_MISC_RST | ESDC_MISC_MDDR_EN | ESDC_MISC_MDDR_DL_RST |
68*4882a593Smuzhiyun ESDC_MISC_DDR_EN | ESDC_MISC_DDR2_EN;
69*4882a593Smuzhiyun writel(val, &esdc->esdmisc);
70*4882a593Smuzhiyun val &= ~(ESDC_MISC_RST | ESDC_MISC_MDDR_DL_RST);
71*4882a593Smuzhiyun writel(val, &esdc->esdmisc);
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun /*
74*4882a593Smuzhiyun * according to DDR2 specs, wait a while before
75*4882a593Smuzhiyun * the PRECHARGE_ALL command
76*4882a593Smuzhiyun */
77*4882a593Smuzhiyun dram_wait(0x20000);
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun /* Load DDR2 config and timing */
80*4882a593Smuzhiyun writel(ddr2_config, cfg_reg);
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun /* Precharge ALL */
83*4882a593Smuzhiyun writel(set_mode(ctlval, 1, SMODE_PRECHARGE),
84*4882a593Smuzhiyun ctl_reg);
85*4882a593Smuzhiyun writel(0xda, start_address + ESDCTL_PRECHARGE);
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun /* Load mode */
88*4882a593Smuzhiyun writel(set_mode(ctlval, 1, SMODE_LOAD_REG),
89*4882a593Smuzhiyun ctl_reg);
90*4882a593Smuzhiyun writeb(0xda, start_address + ESDCTL_DDR2_EMR2); /* EMRS2 */
91*4882a593Smuzhiyun writeb(0xda, start_address + ESDCTL_DDR2_EMR3); /* EMRS3 */
92*4882a593Smuzhiyun writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
93*4882a593Smuzhiyun writeb(0xda, start_address + ESDCTL_DDR2_RESET_DLL); /* Reset DLL */
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun /* Precharge ALL */
96*4882a593Smuzhiyun writel(set_mode(ctlval, 1, SMODE_PRECHARGE),
97*4882a593Smuzhiyun ctl_reg);
98*4882a593Smuzhiyun writel(0xda, start_address + ESDCTL_PRECHARGE);
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun /* Set mode auto refresh : at least two refresh are required */
101*4882a593Smuzhiyun writel(set_mode(ctlval, 1, SMODE_AUTO_REFRESH),
102*4882a593Smuzhiyun ctl_reg);
103*4882a593Smuzhiyun writel(0xda, start_address);
104*4882a593Smuzhiyun writel(0xda, start_address);
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun writel(set_mode(ctlval, 1, SMODE_LOAD_REG),
107*4882a593Smuzhiyun ctl_reg);
108*4882a593Smuzhiyun writeb(0xda, start_address + ESDCTL_DDR2_MR);
109*4882a593Smuzhiyun writeb(0xda, start_address + ESDCTL_DDR2_OCD_DEFAULT);
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun /* OCD mode exit */
112*4882a593Smuzhiyun writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun /* Set normal mode */
115*4882a593Smuzhiyun writel(set_mode(ctlval, 1, SMODE_NORMAL) | refresh,
116*4882a593Smuzhiyun ctl_reg);
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun dram_wait(0x20000);
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun /* Do not set delay lines, only for MDDR */
121*4882a593Smuzhiyun }
122