1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2009
3*4882a593Smuzhiyun * Sergey Kubushyn, himself, ksi@koi8.net
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Changes for unified multibus/multiadapter I2C support.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * (C) Copyright 2001
8*4882a593Smuzhiyun * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com.
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
11*4882a593Smuzhiyun */
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun /*
14*4882a593Smuzhiyun * I2C Functions similar to the standard memory functions.
15*4882a593Smuzhiyun *
16*4882a593Smuzhiyun * There are several parameters in many of the commands that bear further
17*4882a593Smuzhiyun * explanations:
18*4882a593Smuzhiyun *
19*4882a593Smuzhiyun * {i2c_chip} is the I2C chip address (the first byte sent on the bus).
20*4882a593Smuzhiyun * Each I2C chip on the bus has a unique address. On the I2C data bus,
21*4882a593Smuzhiyun * the address is the upper seven bits and the LSB is the "read/write"
22*4882a593Smuzhiyun * bit. Note that the {i2c_chip} address specified on the command
23*4882a593Smuzhiyun * line is not shifted up: e.g. a typical EEPROM memory chip may have
24*4882a593Smuzhiyun * an I2C address of 0x50, but the data put on the bus will be 0xA0
25*4882a593Smuzhiyun * for write and 0xA1 for read. This "non shifted" address notation
26*4882a593Smuzhiyun * matches at least half of the data sheets :-/.
27*4882a593Smuzhiyun *
28*4882a593Smuzhiyun * {addr} is the address (or offset) within the chip. Small memory
29*4882a593Smuzhiyun * chips have 8 bit addresses. Large memory chips have 16 bit
30*4882a593Smuzhiyun * addresses. Other memory chips have 9, 10, or 11 bit addresses.
31*4882a593Smuzhiyun * Many non-memory chips have multiple registers and {addr} is used
32*4882a593Smuzhiyun * as the register index. Some non-memory chips have only one register
33*4882a593Smuzhiyun * and therefore don't need any {addr} parameter.
34*4882a593Smuzhiyun *
35*4882a593Smuzhiyun * The default {addr} parameter is one byte (.1) which works well for
36*4882a593Smuzhiyun * memories and registers with 8 bits of address space.
37*4882a593Smuzhiyun *
38*4882a593Smuzhiyun * You can specify the length of the {addr} field with the optional .0,
39*4882a593Smuzhiyun * .1, or .2 modifier (similar to the .b, .w, .l modifier). If you are
40*4882a593Smuzhiyun * manipulating a single register device which doesn't use an address
41*4882a593Smuzhiyun * field, use "0.0" for the address and the ".0" length field will
42*4882a593Smuzhiyun * suppress the address in the I2C data stream. This also works for
43*4882a593Smuzhiyun * successive reads using the I2C auto-incrementing memory pointer.
44*4882a593Smuzhiyun *
45*4882a593Smuzhiyun * If you are manipulating a large memory with 2-byte addresses, use
46*4882a593Smuzhiyun * the .2 address modifier, e.g. 210.2 addresses location 528 (decimal).
47*4882a593Smuzhiyun *
48*4882a593Smuzhiyun * Then there are the unfortunate memory chips that spill the most
49*4882a593Smuzhiyun * significant 1, 2, or 3 bits of address into the chip address byte.
50*4882a593Smuzhiyun * This effectively makes one chip (logically) look like 2, 4, or
51*4882a593Smuzhiyun * 8 chips. This is handled (awkwardly) by #defining
52*4882a593Smuzhiyun * CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW and using the .1 modifier on the
53*4882a593Smuzhiyun * {addr} field (since .1 is the default, it doesn't actually have to
54*4882a593Smuzhiyun * be specified). Examples: given a memory chip at I2C chip address
55*4882a593Smuzhiyun * 0x50, the following would happen...
56*4882a593Smuzhiyun * i2c md 50 0 10 display 16 bytes starting at 0x000
57*4882a593Smuzhiyun * On the bus: <S> A0 00 <E> <S> A1 <rd> ... <rd>
58*4882a593Smuzhiyun * i2c md 50 100 10 display 16 bytes starting at 0x100
59*4882a593Smuzhiyun * On the bus: <S> A2 00 <E> <S> A3 <rd> ... <rd>
60*4882a593Smuzhiyun * i2c md 50 210 10 display 16 bytes starting at 0x210
61*4882a593Smuzhiyun * On the bus: <S> A4 10 <E> <S> A5 <rd> ... <rd>
62*4882a593Smuzhiyun * This is awfully ugly. It would be nice if someone would think up
63*4882a593Smuzhiyun * a better way of handling this.
64*4882a593Smuzhiyun *
65*4882a593Smuzhiyun * Adapted from cmd_mem.c which is copyright Wolfgang Denk (wd@denx.de).
66*4882a593Smuzhiyun */
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun #include <common.h>
69*4882a593Smuzhiyun #include <bootretry.h>
70*4882a593Smuzhiyun #include <cli.h>
71*4882a593Smuzhiyun #include <command.h>
72*4882a593Smuzhiyun #include <console.h>
73*4882a593Smuzhiyun #include <dm.h>
74*4882a593Smuzhiyun #include <edid.h>
75*4882a593Smuzhiyun #include <environment.h>
76*4882a593Smuzhiyun #include <errno.h>
77*4882a593Smuzhiyun #include <i2c.h>
78*4882a593Smuzhiyun #include <malloc.h>
79*4882a593Smuzhiyun #include <asm/byteorder.h>
80*4882a593Smuzhiyun #include <linux/compiler.h>
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun /* Display values from last command.
85*4882a593Smuzhiyun * Memory modify remembered values are different from display memory.
86*4882a593Smuzhiyun */
87*4882a593Smuzhiyun static uint i2c_dp_last_chip;
88*4882a593Smuzhiyun static uint i2c_dp_last_addr;
89*4882a593Smuzhiyun static uint i2c_dp_last_alen;
90*4882a593Smuzhiyun static uint i2c_dp_last_length = 0x10;
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun static uint i2c_mm_last_chip;
93*4882a593Smuzhiyun static uint i2c_mm_last_addr;
94*4882a593Smuzhiyun static uint i2c_mm_last_alen;
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun /* If only one I2C bus is present, the list of devices to ignore when
97*4882a593Smuzhiyun * the probe command is issued is represented by a 1D array of addresses.
98*4882a593Smuzhiyun * When multiple buses are present, the list is an array of bus-address
99*4882a593Smuzhiyun * pairs. The following macros take care of this */
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun #if defined(CONFIG_SYS_I2C_NOPROBES)
102*4882a593Smuzhiyun #if defined(CONFIG_SYS_I2C) || defined(CONFIG_I2C_MULTI_BUS)
103*4882a593Smuzhiyun static struct
104*4882a593Smuzhiyun {
105*4882a593Smuzhiyun uchar bus;
106*4882a593Smuzhiyun uchar addr;
107*4882a593Smuzhiyun } i2c_no_probes[] = CONFIG_SYS_I2C_NOPROBES;
108*4882a593Smuzhiyun #define GET_BUS_NUM i2c_get_bus_num()
109*4882a593Smuzhiyun #define COMPARE_BUS(b,i) (i2c_no_probes[(i)].bus == (b))
110*4882a593Smuzhiyun #define COMPARE_ADDR(a,i) (i2c_no_probes[(i)].addr == (a))
111*4882a593Smuzhiyun #define NO_PROBE_ADDR(i) i2c_no_probes[(i)].addr
112*4882a593Smuzhiyun #else /* single bus */
113*4882a593Smuzhiyun static uchar i2c_no_probes[] = CONFIG_SYS_I2C_NOPROBES;
114*4882a593Smuzhiyun #define GET_BUS_NUM 0
115*4882a593Smuzhiyun #define COMPARE_BUS(b,i) ((b) == 0) /* Make compiler happy */
116*4882a593Smuzhiyun #define COMPARE_ADDR(a,i) (i2c_no_probes[(i)] == (a))
117*4882a593Smuzhiyun #define NO_PROBE_ADDR(i) i2c_no_probes[(i)]
118*4882a593Smuzhiyun #endif /* defined(CONFIG_SYS_I2C) */
119*4882a593Smuzhiyun #endif
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun #define DISP_LINE_LEN 16
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun /*
124*4882a593Smuzhiyun * Default for driver model is to use the chip's existing address length.
125*4882a593Smuzhiyun * For legacy code, this is not stored, so we need to use a suitable
126*4882a593Smuzhiyun * default.
127*4882a593Smuzhiyun */
128*4882a593Smuzhiyun #ifdef CONFIG_DM_I2C
129*4882a593Smuzhiyun #define DEFAULT_ADDR_LEN (-1)
130*4882a593Smuzhiyun #else
131*4882a593Smuzhiyun #define DEFAULT_ADDR_LEN 1
132*4882a593Smuzhiyun #endif
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun #ifdef CONFIG_DM_I2C
135*4882a593Smuzhiyun static struct udevice *i2c_cur_bus;
136*4882a593Smuzhiyun
cmd_i2c_set_bus_num(unsigned int busnum)137*4882a593Smuzhiyun static int cmd_i2c_set_bus_num(unsigned int busnum)
138*4882a593Smuzhiyun {
139*4882a593Smuzhiyun struct udevice *bus;
140*4882a593Smuzhiyun int ret;
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun ret = uclass_get_device_by_seq(UCLASS_I2C, busnum, &bus);
143*4882a593Smuzhiyun if (ret) {
144*4882a593Smuzhiyun debug("%s: No bus %d\n", __func__, busnum);
145*4882a593Smuzhiyun return ret;
146*4882a593Smuzhiyun }
147*4882a593Smuzhiyun i2c_cur_bus = bus;
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun return 0;
150*4882a593Smuzhiyun }
151*4882a593Smuzhiyun
i2c_get_cur_bus(struct udevice ** busp)152*4882a593Smuzhiyun static int i2c_get_cur_bus(struct udevice **busp)
153*4882a593Smuzhiyun {
154*4882a593Smuzhiyun #ifdef CONFIG_I2C_SET_DEFAULT_BUS_NUM
155*4882a593Smuzhiyun if (!i2c_cur_bus) {
156*4882a593Smuzhiyun if (cmd_i2c_set_bus_num(CONFIG_I2C_DEFAULT_BUS_NUMBER)) {
157*4882a593Smuzhiyun printf("Default I2C bus %d not found\n",
158*4882a593Smuzhiyun CONFIG_I2C_DEFAULT_BUS_NUMBER);
159*4882a593Smuzhiyun return -ENODEV;
160*4882a593Smuzhiyun }
161*4882a593Smuzhiyun }
162*4882a593Smuzhiyun #endif
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun if (!i2c_cur_bus) {
165*4882a593Smuzhiyun puts("No I2C bus selected\n");
166*4882a593Smuzhiyun return -ENODEV;
167*4882a593Smuzhiyun }
168*4882a593Smuzhiyun *busp = i2c_cur_bus;
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun return 0;
171*4882a593Smuzhiyun }
172*4882a593Smuzhiyun
i2c_get_cur_bus_chip(uint chip_addr,struct udevice ** devp)173*4882a593Smuzhiyun static int i2c_get_cur_bus_chip(uint chip_addr, struct udevice **devp)
174*4882a593Smuzhiyun {
175*4882a593Smuzhiyun struct udevice *bus;
176*4882a593Smuzhiyun int ret;
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun ret = i2c_get_cur_bus(&bus);
179*4882a593Smuzhiyun if (ret)
180*4882a593Smuzhiyun return ret;
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun return i2c_get_chip(bus, chip_addr, 1, devp);
183*4882a593Smuzhiyun }
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun #endif
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun /**
188*4882a593Smuzhiyun * i2c_init_board() - Board-specific I2C bus init
189*4882a593Smuzhiyun *
190*4882a593Smuzhiyun * This function is the default no-op implementation of I2C bus
191*4882a593Smuzhiyun * initialization. This function can be overridden by board-specific
192*4882a593Smuzhiyun * implementation if needed.
193*4882a593Smuzhiyun */
194*4882a593Smuzhiyun __weak
i2c_init_board(void)195*4882a593Smuzhiyun void i2c_init_board(void)
196*4882a593Smuzhiyun {
197*4882a593Smuzhiyun }
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun /* TODO: Implement architecture-specific get/set functions */
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun /**
202*4882a593Smuzhiyun * i2c_get_bus_speed() - Return I2C bus speed
203*4882a593Smuzhiyun *
204*4882a593Smuzhiyun * This function is the default implementation of function for retrieveing
205*4882a593Smuzhiyun * the current I2C bus speed in Hz.
206*4882a593Smuzhiyun *
207*4882a593Smuzhiyun * A driver implementing runtime switching of I2C bus speed must override
208*4882a593Smuzhiyun * this function to report the speed correctly. Simple or legacy drivers
209*4882a593Smuzhiyun * can use this fallback.
210*4882a593Smuzhiyun *
211*4882a593Smuzhiyun * Returns I2C bus speed in Hz.
212*4882a593Smuzhiyun */
213*4882a593Smuzhiyun #if !defined(CONFIG_SYS_I2C) && !defined(CONFIG_DM_I2C)
214*4882a593Smuzhiyun /*
215*4882a593Smuzhiyun * TODO: Implement architecture-specific get/set functions
216*4882a593Smuzhiyun * Should go away, if we switched completely to new multibus support
217*4882a593Smuzhiyun */
218*4882a593Smuzhiyun __weak
i2c_get_bus_speed(void)219*4882a593Smuzhiyun unsigned int i2c_get_bus_speed(void)
220*4882a593Smuzhiyun {
221*4882a593Smuzhiyun return CONFIG_SYS_I2C_SPEED;
222*4882a593Smuzhiyun }
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun /**
225*4882a593Smuzhiyun * i2c_set_bus_speed() - Configure I2C bus speed
226*4882a593Smuzhiyun * @speed: Newly set speed of the I2C bus in Hz
227*4882a593Smuzhiyun *
228*4882a593Smuzhiyun * This function is the default implementation of function for setting
229*4882a593Smuzhiyun * the I2C bus speed in Hz.
230*4882a593Smuzhiyun *
231*4882a593Smuzhiyun * A driver implementing runtime switching of I2C bus speed must override
232*4882a593Smuzhiyun * this function to report the speed correctly. Simple or legacy drivers
233*4882a593Smuzhiyun * can use this fallback.
234*4882a593Smuzhiyun *
235*4882a593Smuzhiyun * Returns zero on success, negative value on error.
236*4882a593Smuzhiyun */
237*4882a593Smuzhiyun __weak
i2c_set_bus_speed(unsigned int speed)238*4882a593Smuzhiyun int i2c_set_bus_speed(unsigned int speed)
239*4882a593Smuzhiyun {
240*4882a593Smuzhiyun if (speed != CONFIG_SYS_I2C_SPEED)
241*4882a593Smuzhiyun return -1;
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun return 0;
244*4882a593Smuzhiyun }
245*4882a593Smuzhiyun #endif
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun /**
248*4882a593Smuzhiyun * get_alen() - Small parser helper function to get address length
249*4882a593Smuzhiyun *
250*4882a593Smuzhiyun * Returns the address length.
251*4882a593Smuzhiyun */
get_alen(char * arg,int default_len)252*4882a593Smuzhiyun static uint get_alen(char *arg, int default_len)
253*4882a593Smuzhiyun {
254*4882a593Smuzhiyun int j;
255*4882a593Smuzhiyun int alen;
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun alen = default_len;
258*4882a593Smuzhiyun for (j = 0; j < 8; j++) {
259*4882a593Smuzhiyun if (arg[j] == '.') {
260*4882a593Smuzhiyun alen = arg[j+1] - '0';
261*4882a593Smuzhiyun break;
262*4882a593Smuzhiyun } else if (arg[j] == '\0')
263*4882a593Smuzhiyun break;
264*4882a593Smuzhiyun }
265*4882a593Smuzhiyun return alen;
266*4882a593Smuzhiyun }
267*4882a593Smuzhiyun
268*4882a593Smuzhiyun enum i2c_err_op {
269*4882a593Smuzhiyun I2C_ERR_READ,
270*4882a593Smuzhiyun I2C_ERR_WRITE,
271*4882a593Smuzhiyun };
272*4882a593Smuzhiyun
i2c_report_err(int ret,enum i2c_err_op op)273*4882a593Smuzhiyun static int i2c_report_err(int ret, enum i2c_err_op op)
274*4882a593Smuzhiyun {
275*4882a593Smuzhiyun printf("Error %s the chip: %d\n",
276*4882a593Smuzhiyun op == I2C_ERR_READ ? "reading" : "writing", ret);
277*4882a593Smuzhiyun
278*4882a593Smuzhiyun return CMD_RET_FAILURE;
279*4882a593Smuzhiyun }
280*4882a593Smuzhiyun
281*4882a593Smuzhiyun /**
282*4882a593Smuzhiyun * do_i2c_read() - Handle the "i2c read" command-line command
283*4882a593Smuzhiyun * @cmdtp: Command data struct pointer
284*4882a593Smuzhiyun * @flag: Command flag
285*4882a593Smuzhiyun * @argc: Command-line argument count
286*4882a593Smuzhiyun * @argv: Array of command-line arguments
287*4882a593Smuzhiyun *
288*4882a593Smuzhiyun * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
289*4882a593Smuzhiyun * on error.
290*4882a593Smuzhiyun *
291*4882a593Smuzhiyun * Syntax:
292*4882a593Smuzhiyun * i2c read {i2c_chip} {devaddr}{.0, .1, .2} {len} {memaddr}
293*4882a593Smuzhiyun */
do_i2c_read(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])294*4882a593Smuzhiyun static int do_i2c_read ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
295*4882a593Smuzhiyun {
296*4882a593Smuzhiyun uint chip;
297*4882a593Smuzhiyun uint devaddr, length;
298*4882a593Smuzhiyun int alen;
299*4882a593Smuzhiyun u_char *memaddr;
300*4882a593Smuzhiyun int ret;
301*4882a593Smuzhiyun #ifdef CONFIG_DM_I2C
302*4882a593Smuzhiyun struct udevice *dev;
303*4882a593Smuzhiyun #endif
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun if (argc != 5)
306*4882a593Smuzhiyun return CMD_RET_USAGE;
307*4882a593Smuzhiyun
308*4882a593Smuzhiyun /*
309*4882a593Smuzhiyun * I2C chip address
310*4882a593Smuzhiyun */
311*4882a593Smuzhiyun chip = simple_strtoul(argv[1], NULL, 16);
312*4882a593Smuzhiyun
313*4882a593Smuzhiyun /*
314*4882a593Smuzhiyun * I2C data address within the chip. This can be 1 or
315*4882a593Smuzhiyun * 2 bytes long. Some day it might be 3 bytes long :-).
316*4882a593Smuzhiyun */
317*4882a593Smuzhiyun devaddr = simple_strtoul(argv[2], NULL, 16);
318*4882a593Smuzhiyun alen = get_alen(argv[2], DEFAULT_ADDR_LEN);
319*4882a593Smuzhiyun if (alen > 3)
320*4882a593Smuzhiyun return CMD_RET_USAGE;
321*4882a593Smuzhiyun
322*4882a593Smuzhiyun /*
323*4882a593Smuzhiyun * Length is the number of objects, not number of bytes.
324*4882a593Smuzhiyun */
325*4882a593Smuzhiyun length = simple_strtoul(argv[3], NULL, 16);
326*4882a593Smuzhiyun
327*4882a593Smuzhiyun /*
328*4882a593Smuzhiyun * memaddr is the address where to store things in memory
329*4882a593Smuzhiyun */
330*4882a593Smuzhiyun memaddr = (u_char *)simple_strtoul(argv[4], NULL, 16);
331*4882a593Smuzhiyun
332*4882a593Smuzhiyun #ifdef CONFIG_DM_I2C
333*4882a593Smuzhiyun ret = i2c_get_cur_bus_chip(chip, &dev);
334*4882a593Smuzhiyun if (!ret && alen != -1)
335*4882a593Smuzhiyun ret = i2c_set_chip_offset_len(dev, alen);
336*4882a593Smuzhiyun if (!ret)
337*4882a593Smuzhiyun ret = dm_i2c_read(dev, devaddr, memaddr, length);
338*4882a593Smuzhiyun #else
339*4882a593Smuzhiyun ret = i2c_read(chip, devaddr, alen, memaddr, length);
340*4882a593Smuzhiyun #endif
341*4882a593Smuzhiyun if (ret)
342*4882a593Smuzhiyun return i2c_report_err(ret, I2C_ERR_READ);
343*4882a593Smuzhiyun
344*4882a593Smuzhiyun return 0;
345*4882a593Smuzhiyun }
346*4882a593Smuzhiyun
do_i2c_write(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])347*4882a593Smuzhiyun static int do_i2c_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
348*4882a593Smuzhiyun {
349*4882a593Smuzhiyun uint chip;
350*4882a593Smuzhiyun uint devaddr, length;
351*4882a593Smuzhiyun int alen;
352*4882a593Smuzhiyun u_char *memaddr;
353*4882a593Smuzhiyun int ret;
354*4882a593Smuzhiyun #ifdef CONFIG_DM_I2C
355*4882a593Smuzhiyun struct udevice *dev;
356*4882a593Smuzhiyun struct dm_i2c_chip *i2c_chip;
357*4882a593Smuzhiyun #endif
358*4882a593Smuzhiyun
359*4882a593Smuzhiyun if ((argc < 5) || (argc > 6))
360*4882a593Smuzhiyun return cmd_usage(cmdtp);
361*4882a593Smuzhiyun
362*4882a593Smuzhiyun /*
363*4882a593Smuzhiyun * memaddr is the address where to store things in memory
364*4882a593Smuzhiyun */
365*4882a593Smuzhiyun memaddr = (u_char *)simple_strtoul(argv[1], NULL, 16);
366*4882a593Smuzhiyun
367*4882a593Smuzhiyun /*
368*4882a593Smuzhiyun * I2C chip address
369*4882a593Smuzhiyun */
370*4882a593Smuzhiyun chip = simple_strtoul(argv[2], NULL, 16);
371*4882a593Smuzhiyun
372*4882a593Smuzhiyun /*
373*4882a593Smuzhiyun * I2C data address within the chip. This can be 1 or
374*4882a593Smuzhiyun * 2 bytes long. Some day it might be 3 bytes long :-).
375*4882a593Smuzhiyun */
376*4882a593Smuzhiyun devaddr = simple_strtoul(argv[3], NULL, 16);
377*4882a593Smuzhiyun alen = get_alen(argv[3], DEFAULT_ADDR_LEN);
378*4882a593Smuzhiyun if (alen > 3)
379*4882a593Smuzhiyun return cmd_usage(cmdtp);
380*4882a593Smuzhiyun
381*4882a593Smuzhiyun /*
382*4882a593Smuzhiyun * Length is the number of bytes.
383*4882a593Smuzhiyun */
384*4882a593Smuzhiyun length = simple_strtoul(argv[4], NULL, 16);
385*4882a593Smuzhiyun
386*4882a593Smuzhiyun #ifdef CONFIG_DM_I2C
387*4882a593Smuzhiyun ret = i2c_get_cur_bus_chip(chip, &dev);
388*4882a593Smuzhiyun if (!ret && alen != -1)
389*4882a593Smuzhiyun ret = i2c_set_chip_offset_len(dev, alen);
390*4882a593Smuzhiyun if (ret)
391*4882a593Smuzhiyun return i2c_report_err(ret, I2C_ERR_WRITE);
392*4882a593Smuzhiyun i2c_chip = dev_get_parent_platdata(dev);
393*4882a593Smuzhiyun if (!i2c_chip)
394*4882a593Smuzhiyun return i2c_report_err(ret, I2C_ERR_WRITE);
395*4882a593Smuzhiyun #endif
396*4882a593Smuzhiyun
397*4882a593Smuzhiyun if (argc == 6 && !strcmp(argv[5], "-s")) {
398*4882a593Smuzhiyun /*
399*4882a593Smuzhiyun * Write all bytes in a single I2C transaction. If the target
400*4882a593Smuzhiyun * device is an EEPROM, it is your responsibility to not cross
401*4882a593Smuzhiyun * a page boundary. No write delay upon completion, take this
402*4882a593Smuzhiyun * into account if linking commands.
403*4882a593Smuzhiyun */
404*4882a593Smuzhiyun #ifdef CONFIG_DM_I2C
405*4882a593Smuzhiyun i2c_chip->flags &= ~DM_I2C_CHIP_WR_ADDRESS;
406*4882a593Smuzhiyun ret = dm_i2c_write(dev, devaddr, memaddr, length);
407*4882a593Smuzhiyun #else
408*4882a593Smuzhiyun ret = i2c_write(chip, devaddr, alen, memaddr, length);
409*4882a593Smuzhiyun #endif
410*4882a593Smuzhiyun if (ret)
411*4882a593Smuzhiyun return i2c_report_err(ret, I2C_ERR_WRITE);
412*4882a593Smuzhiyun } else {
413*4882a593Smuzhiyun /*
414*4882a593Smuzhiyun * Repeated addressing - perform <length> separate
415*4882a593Smuzhiyun * write transactions of one byte each
416*4882a593Smuzhiyun */
417*4882a593Smuzhiyun while (length-- > 0) {
418*4882a593Smuzhiyun #ifdef CONFIG_DM_I2C
419*4882a593Smuzhiyun i2c_chip->flags |= DM_I2C_CHIP_WR_ADDRESS;
420*4882a593Smuzhiyun ret = dm_i2c_write(dev, devaddr++, memaddr++, 1);
421*4882a593Smuzhiyun #else
422*4882a593Smuzhiyun ret = i2c_write(chip, devaddr++, alen, memaddr++, 1);
423*4882a593Smuzhiyun #endif
424*4882a593Smuzhiyun if (ret)
425*4882a593Smuzhiyun return i2c_report_err(ret, I2C_ERR_WRITE);
426*4882a593Smuzhiyun /*
427*4882a593Smuzhiyun * No write delay with FRAM devices.
428*4882a593Smuzhiyun */
429*4882a593Smuzhiyun #if !defined(CONFIG_SYS_I2C_FRAM)
430*4882a593Smuzhiyun udelay(11000);
431*4882a593Smuzhiyun #endif
432*4882a593Smuzhiyun }
433*4882a593Smuzhiyun }
434*4882a593Smuzhiyun return 0;
435*4882a593Smuzhiyun }
436*4882a593Smuzhiyun
437*4882a593Smuzhiyun #ifdef CONFIG_DM_I2C
do_i2c_flags(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])438*4882a593Smuzhiyun static int do_i2c_flags(cmd_tbl_t *cmdtp, int flag, int argc,
439*4882a593Smuzhiyun char *const argv[])
440*4882a593Smuzhiyun {
441*4882a593Smuzhiyun struct udevice *dev;
442*4882a593Smuzhiyun uint flags;
443*4882a593Smuzhiyun int chip;
444*4882a593Smuzhiyun int ret;
445*4882a593Smuzhiyun
446*4882a593Smuzhiyun if (argc < 2)
447*4882a593Smuzhiyun return CMD_RET_USAGE;
448*4882a593Smuzhiyun
449*4882a593Smuzhiyun chip = simple_strtoul(argv[1], NULL, 16);
450*4882a593Smuzhiyun ret = i2c_get_cur_bus_chip(chip, &dev);
451*4882a593Smuzhiyun if (ret)
452*4882a593Smuzhiyun return i2c_report_err(ret, I2C_ERR_READ);
453*4882a593Smuzhiyun
454*4882a593Smuzhiyun if (argc > 2) {
455*4882a593Smuzhiyun flags = simple_strtoul(argv[2], NULL, 16);
456*4882a593Smuzhiyun ret = i2c_set_chip_flags(dev, flags);
457*4882a593Smuzhiyun } else {
458*4882a593Smuzhiyun ret = i2c_get_chip_flags(dev, &flags);
459*4882a593Smuzhiyun if (!ret)
460*4882a593Smuzhiyun printf("%x\n", flags);
461*4882a593Smuzhiyun }
462*4882a593Smuzhiyun if (ret)
463*4882a593Smuzhiyun return i2c_report_err(ret, I2C_ERR_READ);
464*4882a593Smuzhiyun
465*4882a593Smuzhiyun return 0;
466*4882a593Smuzhiyun }
467*4882a593Smuzhiyun
do_i2c_olen(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])468*4882a593Smuzhiyun static int do_i2c_olen(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
469*4882a593Smuzhiyun {
470*4882a593Smuzhiyun struct udevice *dev;
471*4882a593Smuzhiyun uint olen;
472*4882a593Smuzhiyun int chip;
473*4882a593Smuzhiyun int ret;
474*4882a593Smuzhiyun
475*4882a593Smuzhiyun if (argc < 2)
476*4882a593Smuzhiyun return CMD_RET_USAGE;
477*4882a593Smuzhiyun
478*4882a593Smuzhiyun chip = simple_strtoul(argv[1], NULL, 16);
479*4882a593Smuzhiyun ret = i2c_get_cur_bus_chip(chip, &dev);
480*4882a593Smuzhiyun if (ret)
481*4882a593Smuzhiyun return i2c_report_err(ret, I2C_ERR_READ);
482*4882a593Smuzhiyun
483*4882a593Smuzhiyun if (argc > 2) {
484*4882a593Smuzhiyun olen = simple_strtoul(argv[2], NULL, 16);
485*4882a593Smuzhiyun ret = i2c_set_chip_offset_len(dev, olen);
486*4882a593Smuzhiyun } else {
487*4882a593Smuzhiyun ret = i2c_get_chip_offset_len(dev);
488*4882a593Smuzhiyun if (ret >= 0) {
489*4882a593Smuzhiyun printf("%x\n", ret);
490*4882a593Smuzhiyun ret = 0;
491*4882a593Smuzhiyun }
492*4882a593Smuzhiyun }
493*4882a593Smuzhiyun if (ret)
494*4882a593Smuzhiyun return i2c_report_err(ret, I2C_ERR_READ);
495*4882a593Smuzhiyun
496*4882a593Smuzhiyun return 0;
497*4882a593Smuzhiyun }
498*4882a593Smuzhiyun #endif
499*4882a593Smuzhiyun
500*4882a593Smuzhiyun /**
501*4882a593Smuzhiyun * do_i2c_md() - Handle the "i2c md" command-line command
502*4882a593Smuzhiyun * @cmdtp: Command data struct pointer
503*4882a593Smuzhiyun * @flag: Command flag
504*4882a593Smuzhiyun * @argc: Command-line argument count
505*4882a593Smuzhiyun * @argv: Array of command-line arguments
506*4882a593Smuzhiyun *
507*4882a593Smuzhiyun * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
508*4882a593Smuzhiyun * on error.
509*4882a593Smuzhiyun *
510*4882a593Smuzhiyun * Syntax:
511*4882a593Smuzhiyun * i2c md {i2c_chip} {addr}{.0, .1, .2} {len}
512*4882a593Smuzhiyun */
do_i2c_md(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])513*4882a593Smuzhiyun static int do_i2c_md ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
514*4882a593Smuzhiyun {
515*4882a593Smuzhiyun uint chip;
516*4882a593Smuzhiyun uint addr, length;
517*4882a593Smuzhiyun int alen;
518*4882a593Smuzhiyun int j, nbytes, linebytes;
519*4882a593Smuzhiyun int ret;
520*4882a593Smuzhiyun #ifdef CONFIG_DM_I2C
521*4882a593Smuzhiyun struct udevice *dev;
522*4882a593Smuzhiyun #endif
523*4882a593Smuzhiyun
524*4882a593Smuzhiyun /* We use the last specified parameters, unless new ones are
525*4882a593Smuzhiyun * entered.
526*4882a593Smuzhiyun */
527*4882a593Smuzhiyun chip = i2c_dp_last_chip;
528*4882a593Smuzhiyun addr = i2c_dp_last_addr;
529*4882a593Smuzhiyun alen = i2c_dp_last_alen;
530*4882a593Smuzhiyun length = i2c_dp_last_length;
531*4882a593Smuzhiyun
532*4882a593Smuzhiyun if (argc < 3)
533*4882a593Smuzhiyun return CMD_RET_USAGE;
534*4882a593Smuzhiyun
535*4882a593Smuzhiyun if ((flag & CMD_FLAG_REPEAT) == 0) {
536*4882a593Smuzhiyun /*
537*4882a593Smuzhiyun * New command specified.
538*4882a593Smuzhiyun */
539*4882a593Smuzhiyun
540*4882a593Smuzhiyun /*
541*4882a593Smuzhiyun * I2C chip address
542*4882a593Smuzhiyun */
543*4882a593Smuzhiyun chip = simple_strtoul(argv[1], NULL, 16);
544*4882a593Smuzhiyun
545*4882a593Smuzhiyun /*
546*4882a593Smuzhiyun * I2C data address within the chip. This can be 1 or
547*4882a593Smuzhiyun * 2 bytes long. Some day it might be 3 bytes long :-).
548*4882a593Smuzhiyun */
549*4882a593Smuzhiyun addr = simple_strtoul(argv[2], NULL, 16);
550*4882a593Smuzhiyun alen = get_alen(argv[2], DEFAULT_ADDR_LEN);
551*4882a593Smuzhiyun if (alen > 3)
552*4882a593Smuzhiyun return CMD_RET_USAGE;
553*4882a593Smuzhiyun
554*4882a593Smuzhiyun /*
555*4882a593Smuzhiyun * If another parameter, it is the length to display.
556*4882a593Smuzhiyun * Length is the number of objects, not number of bytes.
557*4882a593Smuzhiyun */
558*4882a593Smuzhiyun if (argc > 3)
559*4882a593Smuzhiyun length = simple_strtoul(argv[3], NULL, 16);
560*4882a593Smuzhiyun }
561*4882a593Smuzhiyun
562*4882a593Smuzhiyun #ifdef CONFIG_DM_I2C
563*4882a593Smuzhiyun ret = i2c_get_cur_bus_chip(chip, &dev);
564*4882a593Smuzhiyun if (!ret && alen != -1)
565*4882a593Smuzhiyun ret = i2c_set_chip_offset_len(dev, alen);
566*4882a593Smuzhiyun if (ret)
567*4882a593Smuzhiyun return i2c_report_err(ret, I2C_ERR_READ);
568*4882a593Smuzhiyun #endif
569*4882a593Smuzhiyun
570*4882a593Smuzhiyun /*
571*4882a593Smuzhiyun * Print the lines.
572*4882a593Smuzhiyun *
573*4882a593Smuzhiyun * We buffer all read data, so we can make sure data is read only
574*4882a593Smuzhiyun * once.
575*4882a593Smuzhiyun */
576*4882a593Smuzhiyun nbytes = length;
577*4882a593Smuzhiyun do {
578*4882a593Smuzhiyun unsigned char linebuf[DISP_LINE_LEN];
579*4882a593Smuzhiyun unsigned char *cp;
580*4882a593Smuzhiyun
581*4882a593Smuzhiyun linebytes = (nbytes > DISP_LINE_LEN) ? DISP_LINE_LEN : nbytes;
582*4882a593Smuzhiyun
583*4882a593Smuzhiyun #ifdef CONFIG_DM_I2C
584*4882a593Smuzhiyun ret = dm_i2c_read(dev, addr, linebuf, linebytes);
585*4882a593Smuzhiyun #else
586*4882a593Smuzhiyun ret = i2c_read(chip, addr, alen, linebuf, linebytes);
587*4882a593Smuzhiyun #endif
588*4882a593Smuzhiyun if (ret)
589*4882a593Smuzhiyun return i2c_report_err(ret, I2C_ERR_READ);
590*4882a593Smuzhiyun else {
591*4882a593Smuzhiyun printf("%04x:", addr);
592*4882a593Smuzhiyun cp = linebuf;
593*4882a593Smuzhiyun for (j=0; j<linebytes; j++) {
594*4882a593Smuzhiyun printf(" %02x", *cp++);
595*4882a593Smuzhiyun addr++;
596*4882a593Smuzhiyun }
597*4882a593Smuzhiyun puts (" ");
598*4882a593Smuzhiyun cp = linebuf;
599*4882a593Smuzhiyun for (j=0; j<linebytes; j++) {
600*4882a593Smuzhiyun if ((*cp < 0x20) || (*cp > 0x7e))
601*4882a593Smuzhiyun puts (".");
602*4882a593Smuzhiyun else
603*4882a593Smuzhiyun printf("%c", *cp);
604*4882a593Smuzhiyun cp++;
605*4882a593Smuzhiyun }
606*4882a593Smuzhiyun putc ('\n');
607*4882a593Smuzhiyun }
608*4882a593Smuzhiyun nbytes -= linebytes;
609*4882a593Smuzhiyun } while (nbytes > 0);
610*4882a593Smuzhiyun
611*4882a593Smuzhiyun i2c_dp_last_chip = chip;
612*4882a593Smuzhiyun i2c_dp_last_addr = addr;
613*4882a593Smuzhiyun i2c_dp_last_alen = alen;
614*4882a593Smuzhiyun i2c_dp_last_length = length;
615*4882a593Smuzhiyun
616*4882a593Smuzhiyun return 0;
617*4882a593Smuzhiyun }
618*4882a593Smuzhiyun
619*4882a593Smuzhiyun /**
620*4882a593Smuzhiyun * do_i2c_mw() - Handle the "i2c mw" command-line command
621*4882a593Smuzhiyun * @cmdtp: Command data struct pointer
622*4882a593Smuzhiyun * @flag: Command flag
623*4882a593Smuzhiyun * @argc: Command-line argument count
624*4882a593Smuzhiyun * @argv: Array of command-line arguments
625*4882a593Smuzhiyun *
626*4882a593Smuzhiyun * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
627*4882a593Smuzhiyun * on error.
628*4882a593Smuzhiyun *
629*4882a593Smuzhiyun * Syntax:
630*4882a593Smuzhiyun * i2c mw {i2c_chip} {addr}{.0, .1, .2} {data} [{count}]
631*4882a593Smuzhiyun */
do_i2c_mw(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])632*4882a593Smuzhiyun static int do_i2c_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
633*4882a593Smuzhiyun {
634*4882a593Smuzhiyun uint chip;
635*4882a593Smuzhiyun ulong addr;
636*4882a593Smuzhiyun int alen;
637*4882a593Smuzhiyun uchar byte;
638*4882a593Smuzhiyun int count;
639*4882a593Smuzhiyun int ret;
640*4882a593Smuzhiyun #ifdef CONFIG_DM_I2C
641*4882a593Smuzhiyun struct udevice *dev;
642*4882a593Smuzhiyun #endif
643*4882a593Smuzhiyun
644*4882a593Smuzhiyun if ((argc < 4) || (argc > 5))
645*4882a593Smuzhiyun return CMD_RET_USAGE;
646*4882a593Smuzhiyun
647*4882a593Smuzhiyun /*
648*4882a593Smuzhiyun * Chip is always specified.
649*4882a593Smuzhiyun */
650*4882a593Smuzhiyun chip = simple_strtoul(argv[1], NULL, 16);
651*4882a593Smuzhiyun
652*4882a593Smuzhiyun /*
653*4882a593Smuzhiyun * Address is always specified.
654*4882a593Smuzhiyun */
655*4882a593Smuzhiyun addr = simple_strtoul(argv[2], NULL, 16);
656*4882a593Smuzhiyun alen = get_alen(argv[2], DEFAULT_ADDR_LEN);
657*4882a593Smuzhiyun if (alen > 3)
658*4882a593Smuzhiyun return CMD_RET_USAGE;
659*4882a593Smuzhiyun
660*4882a593Smuzhiyun #ifdef CONFIG_DM_I2C
661*4882a593Smuzhiyun ret = i2c_get_cur_bus_chip(chip, &dev);
662*4882a593Smuzhiyun if (!ret && alen != -1)
663*4882a593Smuzhiyun ret = i2c_set_chip_offset_len(dev, alen);
664*4882a593Smuzhiyun if (ret)
665*4882a593Smuzhiyun return i2c_report_err(ret, I2C_ERR_WRITE);
666*4882a593Smuzhiyun #endif
667*4882a593Smuzhiyun /*
668*4882a593Smuzhiyun * Value to write is always specified.
669*4882a593Smuzhiyun */
670*4882a593Smuzhiyun byte = simple_strtoul(argv[3], NULL, 16);
671*4882a593Smuzhiyun
672*4882a593Smuzhiyun /*
673*4882a593Smuzhiyun * Optional count
674*4882a593Smuzhiyun */
675*4882a593Smuzhiyun if (argc == 5)
676*4882a593Smuzhiyun count = simple_strtoul(argv[4], NULL, 16);
677*4882a593Smuzhiyun else
678*4882a593Smuzhiyun count = 1;
679*4882a593Smuzhiyun
680*4882a593Smuzhiyun while (count-- > 0) {
681*4882a593Smuzhiyun #ifdef CONFIG_DM_I2C
682*4882a593Smuzhiyun ret = dm_i2c_write(dev, addr++, &byte, 1);
683*4882a593Smuzhiyun #else
684*4882a593Smuzhiyun ret = i2c_write(chip, addr++, alen, &byte, 1);
685*4882a593Smuzhiyun #endif
686*4882a593Smuzhiyun if (ret)
687*4882a593Smuzhiyun return i2c_report_err(ret, I2C_ERR_WRITE);
688*4882a593Smuzhiyun /*
689*4882a593Smuzhiyun * Wait for the write to complete. The write can take
690*4882a593Smuzhiyun * up to 10mSec (we allow a little more time).
691*4882a593Smuzhiyun */
692*4882a593Smuzhiyun /*
693*4882a593Smuzhiyun * No write delay with FRAM devices.
694*4882a593Smuzhiyun */
695*4882a593Smuzhiyun #if !defined(CONFIG_SYS_I2C_FRAM)
696*4882a593Smuzhiyun udelay(11000);
697*4882a593Smuzhiyun #endif
698*4882a593Smuzhiyun }
699*4882a593Smuzhiyun
700*4882a593Smuzhiyun return 0;
701*4882a593Smuzhiyun }
702*4882a593Smuzhiyun
703*4882a593Smuzhiyun /**
704*4882a593Smuzhiyun * do_i2c_crc() - Handle the "i2c crc32" command-line command
705*4882a593Smuzhiyun * @cmdtp: Command data struct pointer
706*4882a593Smuzhiyun * @flag: Command flag
707*4882a593Smuzhiyun * @argc: Command-line argument count
708*4882a593Smuzhiyun * @argv: Array of command-line arguments
709*4882a593Smuzhiyun *
710*4882a593Smuzhiyun * Calculate a CRC on memory
711*4882a593Smuzhiyun *
712*4882a593Smuzhiyun * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
713*4882a593Smuzhiyun * on error.
714*4882a593Smuzhiyun *
715*4882a593Smuzhiyun * Syntax:
716*4882a593Smuzhiyun * i2c crc32 {i2c_chip} {addr}{.0, .1, .2} {count}
717*4882a593Smuzhiyun */
do_i2c_crc(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])718*4882a593Smuzhiyun static int do_i2c_crc (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
719*4882a593Smuzhiyun {
720*4882a593Smuzhiyun uint chip;
721*4882a593Smuzhiyun ulong addr;
722*4882a593Smuzhiyun int alen;
723*4882a593Smuzhiyun int count;
724*4882a593Smuzhiyun uchar byte;
725*4882a593Smuzhiyun ulong crc;
726*4882a593Smuzhiyun ulong err;
727*4882a593Smuzhiyun int ret = 0;
728*4882a593Smuzhiyun #ifdef CONFIG_DM_I2C
729*4882a593Smuzhiyun struct udevice *dev;
730*4882a593Smuzhiyun #endif
731*4882a593Smuzhiyun
732*4882a593Smuzhiyun if (argc < 4)
733*4882a593Smuzhiyun return CMD_RET_USAGE;
734*4882a593Smuzhiyun
735*4882a593Smuzhiyun /*
736*4882a593Smuzhiyun * Chip is always specified.
737*4882a593Smuzhiyun */
738*4882a593Smuzhiyun chip = simple_strtoul(argv[1], NULL, 16);
739*4882a593Smuzhiyun
740*4882a593Smuzhiyun /*
741*4882a593Smuzhiyun * Address is always specified.
742*4882a593Smuzhiyun */
743*4882a593Smuzhiyun addr = simple_strtoul(argv[2], NULL, 16);
744*4882a593Smuzhiyun alen = get_alen(argv[2], DEFAULT_ADDR_LEN);
745*4882a593Smuzhiyun if (alen > 3)
746*4882a593Smuzhiyun return CMD_RET_USAGE;
747*4882a593Smuzhiyun
748*4882a593Smuzhiyun #ifdef CONFIG_DM_I2C
749*4882a593Smuzhiyun ret = i2c_get_cur_bus_chip(chip, &dev);
750*4882a593Smuzhiyun if (!ret && alen != -1)
751*4882a593Smuzhiyun ret = i2c_set_chip_offset_len(dev, alen);
752*4882a593Smuzhiyun if (ret)
753*4882a593Smuzhiyun return i2c_report_err(ret, I2C_ERR_READ);
754*4882a593Smuzhiyun #endif
755*4882a593Smuzhiyun /*
756*4882a593Smuzhiyun * Count is always specified
757*4882a593Smuzhiyun */
758*4882a593Smuzhiyun count = simple_strtoul(argv[3], NULL, 16);
759*4882a593Smuzhiyun
760*4882a593Smuzhiyun printf ("CRC32 for %08lx ... %08lx ==> ", addr, addr + count - 1);
761*4882a593Smuzhiyun /*
762*4882a593Smuzhiyun * CRC a byte at a time. This is going to be slooow, but hey, the
763*4882a593Smuzhiyun * memories are small and slow too so hopefully nobody notices.
764*4882a593Smuzhiyun */
765*4882a593Smuzhiyun crc = 0;
766*4882a593Smuzhiyun err = 0;
767*4882a593Smuzhiyun while (count-- > 0) {
768*4882a593Smuzhiyun #ifdef CONFIG_DM_I2C
769*4882a593Smuzhiyun ret = dm_i2c_read(dev, addr, &byte, 1);
770*4882a593Smuzhiyun #else
771*4882a593Smuzhiyun ret = i2c_read(chip, addr, alen, &byte, 1);
772*4882a593Smuzhiyun #endif
773*4882a593Smuzhiyun if (ret)
774*4882a593Smuzhiyun err++;
775*4882a593Smuzhiyun crc = crc32 (crc, &byte, 1);
776*4882a593Smuzhiyun addr++;
777*4882a593Smuzhiyun }
778*4882a593Smuzhiyun if (err > 0)
779*4882a593Smuzhiyun i2c_report_err(ret, I2C_ERR_READ);
780*4882a593Smuzhiyun else
781*4882a593Smuzhiyun printf ("%08lx\n", crc);
782*4882a593Smuzhiyun
783*4882a593Smuzhiyun return 0;
784*4882a593Smuzhiyun }
785*4882a593Smuzhiyun
786*4882a593Smuzhiyun /**
787*4882a593Smuzhiyun * mod_i2c_mem() - Handle the "i2c mm" and "i2c nm" command-line command
788*4882a593Smuzhiyun * @cmdtp: Command data struct pointer
789*4882a593Smuzhiyun * @flag: Command flag
790*4882a593Smuzhiyun * @argc: Command-line argument count
791*4882a593Smuzhiyun * @argv: Array of command-line arguments
792*4882a593Smuzhiyun *
793*4882a593Smuzhiyun * Modify memory.
794*4882a593Smuzhiyun *
795*4882a593Smuzhiyun * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
796*4882a593Smuzhiyun * on error.
797*4882a593Smuzhiyun *
798*4882a593Smuzhiyun * Syntax:
799*4882a593Smuzhiyun * i2c mm{.b, .w, .l} {i2c_chip} {addr}{.0, .1, .2}
800*4882a593Smuzhiyun * i2c nm{.b, .w, .l} {i2c_chip} {addr}{.0, .1, .2}
801*4882a593Smuzhiyun */
802*4882a593Smuzhiyun static int
mod_i2c_mem(cmd_tbl_t * cmdtp,int incrflag,int flag,int argc,char * const argv[])803*4882a593Smuzhiyun mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char * const argv[])
804*4882a593Smuzhiyun {
805*4882a593Smuzhiyun uint chip;
806*4882a593Smuzhiyun ulong addr;
807*4882a593Smuzhiyun int alen;
808*4882a593Smuzhiyun ulong data;
809*4882a593Smuzhiyun int size = 1;
810*4882a593Smuzhiyun int nbytes;
811*4882a593Smuzhiyun int ret;
812*4882a593Smuzhiyun #ifdef CONFIG_DM_I2C
813*4882a593Smuzhiyun struct udevice *dev;
814*4882a593Smuzhiyun #endif
815*4882a593Smuzhiyun
816*4882a593Smuzhiyun if (argc != 3)
817*4882a593Smuzhiyun return CMD_RET_USAGE;
818*4882a593Smuzhiyun
819*4882a593Smuzhiyun bootretry_reset_cmd_timeout(); /* got a good command to get here */
820*4882a593Smuzhiyun /*
821*4882a593Smuzhiyun * We use the last specified parameters, unless new ones are
822*4882a593Smuzhiyun * entered.
823*4882a593Smuzhiyun */
824*4882a593Smuzhiyun chip = i2c_mm_last_chip;
825*4882a593Smuzhiyun addr = i2c_mm_last_addr;
826*4882a593Smuzhiyun alen = i2c_mm_last_alen;
827*4882a593Smuzhiyun
828*4882a593Smuzhiyun if ((flag & CMD_FLAG_REPEAT) == 0) {
829*4882a593Smuzhiyun /*
830*4882a593Smuzhiyun * New command specified. Check for a size specification.
831*4882a593Smuzhiyun * Defaults to byte if no or incorrect specification.
832*4882a593Smuzhiyun */
833*4882a593Smuzhiyun size = cmd_get_data_size(argv[0], 1);
834*4882a593Smuzhiyun
835*4882a593Smuzhiyun /*
836*4882a593Smuzhiyun * Chip is always specified.
837*4882a593Smuzhiyun */
838*4882a593Smuzhiyun chip = simple_strtoul(argv[1], NULL, 16);
839*4882a593Smuzhiyun
840*4882a593Smuzhiyun /*
841*4882a593Smuzhiyun * Address is always specified.
842*4882a593Smuzhiyun */
843*4882a593Smuzhiyun addr = simple_strtoul(argv[2], NULL, 16);
844*4882a593Smuzhiyun alen = get_alen(argv[2], DEFAULT_ADDR_LEN);
845*4882a593Smuzhiyun if (alen > 3)
846*4882a593Smuzhiyun return CMD_RET_USAGE;
847*4882a593Smuzhiyun }
848*4882a593Smuzhiyun
849*4882a593Smuzhiyun #ifdef CONFIG_DM_I2C
850*4882a593Smuzhiyun ret = i2c_get_cur_bus_chip(chip, &dev);
851*4882a593Smuzhiyun if (!ret && alen != -1)
852*4882a593Smuzhiyun ret = i2c_set_chip_offset_len(dev, alen);
853*4882a593Smuzhiyun if (ret)
854*4882a593Smuzhiyun return i2c_report_err(ret, I2C_ERR_WRITE);
855*4882a593Smuzhiyun #endif
856*4882a593Smuzhiyun
857*4882a593Smuzhiyun /*
858*4882a593Smuzhiyun * Print the address, followed by value. Then accept input for
859*4882a593Smuzhiyun * the next value. A non-converted value exits.
860*4882a593Smuzhiyun */
861*4882a593Smuzhiyun do {
862*4882a593Smuzhiyun printf("%08lx:", addr);
863*4882a593Smuzhiyun #ifdef CONFIG_DM_I2C
864*4882a593Smuzhiyun ret = dm_i2c_read(dev, addr, (uchar *)&data, size);
865*4882a593Smuzhiyun #else
866*4882a593Smuzhiyun ret = i2c_read(chip, addr, alen, (uchar *)&data, size);
867*4882a593Smuzhiyun #endif
868*4882a593Smuzhiyun if (ret)
869*4882a593Smuzhiyun return i2c_report_err(ret, I2C_ERR_READ);
870*4882a593Smuzhiyun
871*4882a593Smuzhiyun data = cpu_to_be32(data);
872*4882a593Smuzhiyun if (size == 1)
873*4882a593Smuzhiyun printf(" %02lx", (data >> 24) & 0x000000FF);
874*4882a593Smuzhiyun else if (size == 2)
875*4882a593Smuzhiyun printf(" %04lx", (data >> 16) & 0x0000FFFF);
876*4882a593Smuzhiyun else
877*4882a593Smuzhiyun printf(" %08lx", data);
878*4882a593Smuzhiyun
879*4882a593Smuzhiyun nbytes = cli_readline(" ? ");
880*4882a593Smuzhiyun if (nbytes == 0) {
881*4882a593Smuzhiyun /*
882*4882a593Smuzhiyun * <CR> pressed as only input, don't modify current
883*4882a593Smuzhiyun * location and move to next.
884*4882a593Smuzhiyun */
885*4882a593Smuzhiyun if (incrflag)
886*4882a593Smuzhiyun addr += size;
887*4882a593Smuzhiyun nbytes = size;
888*4882a593Smuzhiyun /* good enough to not time out */
889*4882a593Smuzhiyun bootretry_reset_cmd_timeout();
890*4882a593Smuzhiyun }
891*4882a593Smuzhiyun #ifdef CONFIG_BOOT_RETRY_TIME
892*4882a593Smuzhiyun else if (nbytes == -2)
893*4882a593Smuzhiyun break; /* timed out, exit the command */
894*4882a593Smuzhiyun #endif
895*4882a593Smuzhiyun else {
896*4882a593Smuzhiyun char *endp;
897*4882a593Smuzhiyun
898*4882a593Smuzhiyun data = simple_strtoul(console_buffer, &endp, 16);
899*4882a593Smuzhiyun if (size == 1)
900*4882a593Smuzhiyun data = data << 24;
901*4882a593Smuzhiyun else if (size == 2)
902*4882a593Smuzhiyun data = data << 16;
903*4882a593Smuzhiyun data = be32_to_cpu(data);
904*4882a593Smuzhiyun nbytes = endp - console_buffer;
905*4882a593Smuzhiyun if (nbytes) {
906*4882a593Smuzhiyun /*
907*4882a593Smuzhiyun * good enough to not time out
908*4882a593Smuzhiyun */
909*4882a593Smuzhiyun bootretry_reset_cmd_timeout();
910*4882a593Smuzhiyun #ifdef CONFIG_DM_I2C
911*4882a593Smuzhiyun ret = dm_i2c_write(dev, addr, (uchar *)&data,
912*4882a593Smuzhiyun size);
913*4882a593Smuzhiyun #else
914*4882a593Smuzhiyun ret = i2c_write(chip, addr, alen,
915*4882a593Smuzhiyun (uchar *)&data, size);
916*4882a593Smuzhiyun #endif
917*4882a593Smuzhiyun if (ret)
918*4882a593Smuzhiyun return i2c_report_err(ret,
919*4882a593Smuzhiyun I2C_ERR_WRITE);
920*4882a593Smuzhiyun #ifdef CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS
921*4882a593Smuzhiyun udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
922*4882a593Smuzhiyun #endif
923*4882a593Smuzhiyun if (incrflag)
924*4882a593Smuzhiyun addr += size;
925*4882a593Smuzhiyun }
926*4882a593Smuzhiyun }
927*4882a593Smuzhiyun } while (nbytes);
928*4882a593Smuzhiyun
929*4882a593Smuzhiyun i2c_mm_last_chip = chip;
930*4882a593Smuzhiyun i2c_mm_last_addr = addr;
931*4882a593Smuzhiyun i2c_mm_last_alen = alen;
932*4882a593Smuzhiyun
933*4882a593Smuzhiyun return 0;
934*4882a593Smuzhiyun }
935*4882a593Smuzhiyun
936*4882a593Smuzhiyun /**
937*4882a593Smuzhiyun * do_i2c_probe() - Handle the "i2c probe" command-line command
938*4882a593Smuzhiyun * @cmdtp: Command data struct pointer
939*4882a593Smuzhiyun * @flag: Command flag
940*4882a593Smuzhiyun * @argc: Command-line argument count
941*4882a593Smuzhiyun * @argv: Array of command-line arguments
942*4882a593Smuzhiyun *
943*4882a593Smuzhiyun * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
944*4882a593Smuzhiyun * on error.
945*4882a593Smuzhiyun *
946*4882a593Smuzhiyun * Syntax:
947*4882a593Smuzhiyun * i2c probe {addr}
948*4882a593Smuzhiyun *
949*4882a593Smuzhiyun * Returns zero (success) if one or more I2C devices was found
950*4882a593Smuzhiyun */
do_i2c_probe(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])951*4882a593Smuzhiyun static int do_i2c_probe (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
952*4882a593Smuzhiyun {
953*4882a593Smuzhiyun int j;
954*4882a593Smuzhiyun int addr = -1;
955*4882a593Smuzhiyun int found = 0;
956*4882a593Smuzhiyun #if defined(CONFIG_SYS_I2C_NOPROBES)
957*4882a593Smuzhiyun int k, skip;
958*4882a593Smuzhiyun unsigned int bus = GET_BUS_NUM;
959*4882a593Smuzhiyun #endif /* NOPROBES */
960*4882a593Smuzhiyun int ret;
961*4882a593Smuzhiyun #ifdef CONFIG_DM_I2C
962*4882a593Smuzhiyun struct udevice *bus, *dev;
963*4882a593Smuzhiyun
964*4882a593Smuzhiyun if (i2c_get_cur_bus(&bus))
965*4882a593Smuzhiyun return CMD_RET_FAILURE;
966*4882a593Smuzhiyun #endif
967*4882a593Smuzhiyun
968*4882a593Smuzhiyun if (argc == 2)
969*4882a593Smuzhiyun addr = simple_strtol(argv[1], 0, 16);
970*4882a593Smuzhiyun
971*4882a593Smuzhiyun puts ("Valid chip addresses:");
972*4882a593Smuzhiyun for (j = 0; j < 128; j++) {
973*4882a593Smuzhiyun if ((0 <= addr) && (j != addr))
974*4882a593Smuzhiyun continue;
975*4882a593Smuzhiyun
976*4882a593Smuzhiyun #if defined(CONFIG_SYS_I2C_NOPROBES)
977*4882a593Smuzhiyun skip = 0;
978*4882a593Smuzhiyun for (k = 0; k < ARRAY_SIZE(i2c_no_probes); k++) {
979*4882a593Smuzhiyun if (COMPARE_BUS(bus, k) && COMPARE_ADDR(j, k)) {
980*4882a593Smuzhiyun skip = 1;
981*4882a593Smuzhiyun break;
982*4882a593Smuzhiyun }
983*4882a593Smuzhiyun }
984*4882a593Smuzhiyun if (skip)
985*4882a593Smuzhiyun continue;
986*4882a593Smuzhiyun #endif
987*4882a593Smuzhiyun #ifdef CONFIG_DM_I2C
988*4882a593Smuzhiyun ret = dm_i2c_probe(bus, j, 0, &dev);
989*4882a593Smuzhiyun #else
990*4882a593Smuzhiyun ret = i2c_probe(j);
991*4882a593Smuzhiyun #endif
992*4882a593Smuzhiyun if (ret == 0) {
993*4882a593Smuzhiyun printf(" %02X", j);
994*4882a593Smuzhiyun found++;
995*4882a593Smuzhiyun }
996*4882a593Smuzhiyun }
997*4882a593Smuzhiyun putc ('\n');
998*4882a593Smuzhiyun
999*4882a593Smuzhiyun #if defined(CONFIG_SYS_I2C_NOPROBES)
1000*4882a593Smuzhiyun puts ("Excluded chip addresses:");
1001*4882a593Smuzhiyun for (k = 0; k < ARRAY_SIZE(i2c_no_probes); k++) {
1002*4882a593Smuzhiyun if (COMPARE_BUS(bus,k))
1003*4882a593Smuzhiyun printf(" %02X", NO_PROBE_ADDR(k));
1004*4882a593Smuzhiyun }
1005*4882a593Smuzhiyun putc ('\n');
1006*4882a593Smuzhiyun #endif
1007*4882a593Smuzhiyun
1008*4882a593Smuzhiyun return (0 == found);
1009*4882a593Smuzhiyun }
1010*4882a593Smuzhiyun
1011*4882a593Smuzhiyun /**
1012*4882a593Smuzhiyun * do_i2c_loop() - Handle the "i2c loop" command-line command
1013*4882a593Smuzhiyun * @cmdtp: Command data struct pointer
1014*4882a593Smuzhiyun * @flag: Command flag
1015*4882a593Smuzhiyun * @argc: Command-line argument count
1016*4882a593Smuzhiyun * @argv: Array of command-line arguments
1017*4882a593Smuzhiyun *
1018*4882a593Smuzhiyun * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
1019*4882a593Smuzhiyun * on error.
1020*4882a593Smuzhiyun *
1021*4882a593Smuzhiyun * Syntax:
1022*4882a593Smuzhiyun * i2c loop {i2c_chip} {addr}{.0, .1, .2} [{length}] [{delay}]
1023*4882a593Smuzhiyun * {length} - Number of bytes to read
1024*4882a593Smuzhiyun * {delay} - A DECIMAL number and defaults to 1000 uSec
1025*4882a593Smuzhiyun */
do_i2c_loop(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])1026*4882a593Smuzhiyun static int do_i2c_loop(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
1027*4882a593Smuzhiyun {
1028*4882a593Smuzhiyun uint chip;
1029*4882a593Smuzhiyun int alen;
1030*4882a593Smuzhiyun uint addr;
1031*4882a593Smuzhiyun uint length;
1032*4882a593Smuzhiyun u_char bytes[16];
1033*4882a593Smuzhiyun int delay;
1034*4882a593Smuzhiyun int ret;
1035*4882a593Smuzhiyun #ifdef CONFIG_DM_I2C
1036*4882a593Smuzhiyun struct udevice *dev;
1037*4882a593Smuzhiyun #endif
1038*4882a593Smuzhiyun
1039*4882a593Smuzhiyun if (argc < 3)
1040*4882a593Smuzhiyun return CMD_RET_USAGE;
1041*4882a593Smuzhiyun
1042*4882a593Smuzhiyun /*
1043*4882a593Smuzhiyun * Chip is always specified.
1044*4882a593Smuzhiyun */
1045*4882a593Smuzhiyun chip = simple_strtoul(argv[1], NULL, 16);
1046*4882a593Smuzhiyun
1047*4882a593Smuzhiyun /*
1048*4882a593Smuzhiyun * Address is always specified.
1049*4882a593Smuzhiyun */
1050*4882a593Smuzhiyun addr = simple_strtoul(argv[2], NULL, 16);
1051*4882a593Smuzhiyun alen = get_alen(argv[2], DEFAULT_ADDR_LEN);
1052*4882a593Smuzhiyun if (alen > 3)
1053*4882a593Smuzhiyun return CMD_RET_USAGE;
1054*4882a593Smuzhiyun #ifdef CONFIG_DM_I2C
1055*4882a593Smuzhiyun ret = i2c_get_cur_bus_chip(chip, &dev);
1056*4882a593Smuzhiyun if (!ret && alen != -1)
1057*4882a593Smuzhiyun ret = i2c_set_chip_offset_len(dev, alen);
1058*4882a593Smuzhiyun if (ret)
1059*4882a593Smuzhiyun return i2c_report_err(ret, I2C_ERR_WRITE);
1060*4882a593Smuzhiyun #endif
1061*4882a593Smuzhiyun
1062*4882a593Smuzhiyun /*
1063*4882a593Smuzhiyun * Length is the number of objects, not number of bytes.
1064*4882a593Smuzhiyun */
1065*4882a593Smuzhiyun length = 1;
1066*4882a593Smuzhiyun length = simple_strtoul(argv[3], NULL, 16);
1067*4882a593Smuzhiyun if (length > sizeof(bytes))
1068*4882a593Smuzhiyun length = sizeof(bytes);
1069*4882a593Smuzhiyun
1070*4882a593Smuzhiyun /*
1071*4882a593Smuzhiyun * The delay time (uSec) is optional.
1072*4882a593Smuzhiyun */
1073*4882a593Smuzhiyun delay = 1000;
1074*4882a593Smuzhiyun if (argc > 3)
1075*4882a593Smuzhiyun delay = simple_strtoul(argv[4], NULL, 10);
1076*4882a593Smuzhiyun /*
1077*4882a593Smuzhiyun * Run the loop...
1078*4882a593Smuzhiyun */
1079*4882a593Smuzhiyun while (1) {
1080*4882a593Smuzhiyun #ifdef CONFIG_DM_I2C
1081*4882a593Smuzhiyun ret = dm_i2c_read(dev, addr, bytes, length);
1082*4882a593Smuzhiyun #else
1083*4882a593Smuzhiyun ret = i2c_read(chip, addr, alen, bytes, length);
1084*4882a593Smuzhiyun #endif
1085*4882a593Smuzhiyun if (ret)
1086*4882a593Smuzhiyun i2c_report_err(ret, I2C_ERR_READ);
1087*4882a593Smuzhiyun udelay(delay);
1088*4882a593Smuzhiyun }
1089*4882a593Smuzhiyun
1090*4882a593Smuzhiyun /* NOTREACHED */
1091*4882a593Smuzhiyun return 0;
1092*4882a593Smuzhiyun }
1093*4882a593Smuzhiyun
1094*4882a593Smuzhiyun /*
1095*4882a593Smuzhiyun * The SDRAM command is separately configured because many
1096*4882a593Smuzhiyun * (most?) embedded boards don't use SDRAM DIMMs.
1097*4882a593Smuzhiyun *
1098*4882a593Smuzhiyun * FIXME: Document and probably move elsewhere!
1099*4882a593Smuzhiyun */
1100*4882a593Smuzhiyun #if defined(CONFIG_CMD_SDRAM)
print_ddr2_tcyc(u_char const b)1101*4882a593Smuzhiyun static void print_ddr2_tcyc (u_char const b)
1102*4882a593Smuzhiyun {
1103*4882a593Smuzhiyun printf ("%d.", (b >> 4) & 0x0F);
1104*4882a593Smuzhiyun switch (b & 0x0F) {
1105*4882a593Smuzhiyun case 0x0:
1106*4882a593Smuzhiyun case 0x1:
1107*4882a593Smuzhiyun case 0x2:
1108*4882a593Smuzhiyun case 0x3:
1109*4882a593Smuzhiyun case 0x4:
1110*4882a593Smuzhiyun case 0x5:
1111*4882a593Smuzhiyun case 0x6:
1112*4882a593Smuzhiyun case 0x7:
1113*4882a593Smuzhiyun case 0x8:
1114*4882a593Smuzhiyun case 0x9:
1115*4882a593Smuzhiyun printf ("%d ns\n", b & 0x0F);
1116*4882a593Smuzhiyun break;
1117*4882a593Smuzhiyun case 0xA:
1118*4882a593Smuzhiyun puts ("25 ns\n");
1119*4882a593Smuzhiyun break;
1120*4882a593Smuzhiyun case 0xB:
1121*4882a593Smuzhiyun puts ("33 ns\n");
1122*4882a593Smuzhiyun break;
1123*4882a593Smuzhiyun case 0xC:
1124*4882a593Smuzhiyun puts ("66 ns\n");
1125*4882a593Smuzhiyun break;
1126*4882a593Smuzhiyun case 0xD:
1127*4882a593Smuzhiyun puts ("75 ns\n");
1128*4882a593Smuzhiyun break;
1129*4882a593Smuzhiyun default:
1130*4882a593Smuzhiyun puts ("?? ns\n");
1131*4882a593Smuzhiyun break;
1132*4882a593Smuzhiyun }
1133*4882a593Smuzhiyun }
1134*4882a593Smuzhiyun
decode_bits(u_char const b,char const * str[],int const do_once)1135*4882a593Smuzhiyun static void decode_bits (u_char const b, char const *str[], int const do_once)
1136*4882a593Smuzhiyun {
1137*4882a593Smuzhiyun u_char mask;
1138*4882a593Smuzhiyun
1139*4882a593Smuzhiyun for (mask = 0x80; mask != 0x00; mask >>= 1, ++str) {
1140*4882a593Smuzhiyun if (b & mask) {
1141*4882a593Smuzhiyun puts (*str);
1142*4882a593Smuzhiyun if (do_once)
1143*4882a593Smuzhiyun return;
1144*4882a593Smuzhiyun }
1145*4882a593Smuzhiyun }
1146*4882a593Smuzhiyun }
1147*4882a593Smuzhiyun
1148*4882a593Smuzhiyun /*
1149*4882a593Smuzhiyun * Syntax:
1150*4882a593Smuzhiyun * i2c sdram {i2c_chip}
1151*4882a593Smuzhiyun */
do_sdram(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])1152*4882a593Smuzhiyun static int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
1153*4882a593Smuzhiyun {
1154*4882a593Smuzhiyun enum { unknown, EDO, SDRAM, DDR, DDR2, DDR3, DDR4 } type;
1155*4882a593Smuzhiyun
1156*4882a593Smuzhiyun uint chip;
1157*4882a593Smuzhiyun u_char data[128];
1158*4882a593Smuzhiyun u_char cksum;
1159*4882a593Smuzhiyun int j, ret;
1160*4882a593Smuzhiyun #ifdef CONFIG_DM_I2C
1161*4882a593Smuzhiyun struct udevice *dev;
1162*4882a593Smuzhiyun #endif
1163*4882a593Smuzhiyun
1164*4882a593Smuzhiyun static const char *decode_CAS_DDR2[] = {
1165*4882a593Smuzhiyun " TBD", " 6", " 5", " 4", " 3", " 2", " TBD", " TBD"
1166*4882a593Smuzhiyun };
1167*4882a593Smuzhiyun
1168*4882a593Smuzhiyun static const char *decode_CAS_default[] = {
1169*4882a593Smuzhiyun " TBD", " 7", " 6", " 5", " 4", " 3", " 2", " 1"
1170*4882a593Smuzhiyun };
1171*4882a593Smuzhiyun
1172*4882a593Smuzhiyun static const char *decode_CS_WE_default[] = {
1173*4882a593Smuzhiyun " TBD", " 6", " 5", " 4", " 3", " 2", " 1", " 0"
1174*4882a593Smuzhiyun };
1175*4882a593Smuzhiyun
1176*4882a593Smuzhiyun static const char *decode_byte21_default[] = {
1177*4882a593Smuzhiyun " TBD (bit 7)\n",
1178*4882a593Smuzhiyun " Redundant row address\n",
1179*4882a593Smuzhiyun " Differential clock input\n",
1180*4882a593Smuzhiyun " Registerd DQMB inputs\n",
1181*4882a593Smuzhiyun " Buffered DQMB inputs\n",
1182*4882a593Smuzhiyun " On-card PLL\n",
1183*4882a593Smuzhiyun " Registered address/control lines\n",
1184*4882a593Smuzhiyun " Buffered address/control lines\n"
1185*4882a593Smuzhiyun };
1186*4882a593Smuzhiyun
1187*4882a593Smuzhiyun static const char *decode_byte22_DDR2[] = {
1188*4882a593Smuzhiyun " TBD (bit 7)\n",
1189*4882a593Smuzhiyun " TBD (bit 6)\n",
1190*4882a593Smuzhiyun " TBD (bit 5)\n",
1191*4882a593Smuzhiyun " TBD (bit 4)\n",
1192*4882a593Smuzhiyun " TBD (bit 3)\n",
1193*4882a593Smuzhiyun " Supports partial array self refresh\n",
1194*4882a593Smuzhiyun " Supports 50 ohm ODT\n",
1195*4882a593Smuzhiyun " Supports weak driver\n"
1196*4882a593Smuzhiyun };
1197*4882a593Smuzhiyun
1198*4882a593Smuzhiyun static const char *decode_row_density_DDR2[] = {
1199*4882a593Smuzhiyun "512 MiB", "256 MiB", "128 MiB", "16 GiB",
1200*4882a593Smuzhiyun "8 GiB", "4 GiB", "2 GiB", "1 GiB"
1201*4882a593Smuzhiyun };
1202*4882a593Smuzhiyun
1203*4882a593Smuzhiyun static const char *decode_row_density_default[] = {
1204*4882a593Smuzhiyun "512 MiB", "256 MiB", "128 MiB", "64 MiB",
1205*4882a593Smuzhiyun "32 MiB", "16 MiB", "8 MiB", "4 MiB"
1206*4882a593Smuzhiyun };
1207*4882a593Smuzhiyun
1208*4882a593Smuzhiyun if (argc < 2)
1209*4882a593Smuzhiyun return CMD_RET_USAGE;
1210*4882a593Smuzhiyun
1211*4882a593Smuzhiyun /*
1212*4882a593Smuzhiyun * Chip is always specified.
1213*4882a593Smuzhiyun */
1214*4882a593Smuzhiyun chip = simple_strtoul (argv[1], NULL, 16);
1215*4882a593Smuzhiyun
1216*4882a593Smuzhiyun #ifdef CONFIG_DM_I2C
1217*4882a593Smuzhiyun ret = i2c_get_cur_bus_chip(chip, &dev);
1218*4882a593Smuzhiyun if (!ret)
1219*4882a593Smuzhiyun ret = dm_i2c_read(dev, 0, data, sizeof(data));
1220*4882a593Smuzhiyun #else
1221*4882a593Smuzhiyun ret = i2c_read(chip, 0, 1, data, sizeof(data));
1222*4882a593Smuzhiyun #endif
1223*4882a593Smuzhiyun if (ret) {
1224*4882a593Smuzhiyun puts ("No SDRAM Serial Presence Detect found.\n");
1225*4882a593Smuzhiyun return 1;
1226*4882a593Smuzhiyun }
1227*4882a593Smuzhiyun
1228*4882a593Smuzhiyun cksum = 0;
1229*4882a593Smuzhiyun for (j = 0; j < 63; j++) {
1230*4882a593Smuzhiyun cksum += data[j];
1231*4882a593Smuzhiyun }
1232*4882a593Smuzhiyun if (cksum != data[63]) {
1233*4882a593Smuzhiyun printf ("WARNING: Configuration data checksum failure:\n"
1234*4882a593Smuzhiyun " is 0x%02x, calculated 0x%02x\n", data[63], cksum);
1235*4882a593Smuzhiyun }
1236*4882a593Smuzhiyun printf ("SPD data revision %d.%d\n",
1237*4882a593Smuzhiyun (data[62] >> 4) & 0x0F, data[62] & 0x0F);
1238*4882a593Smuzhiyun printf ("Bytes used 0x%02X\n", data[0]);
1239*4882a593Smuzhiyun printf ("Serial memory size 0x%02X\n", 1 << data[1]);
1240*4882a593Smuzhiyun
1241*4882a593Smuzhiyun puts ("Memory type ");
1242*4882a593Smuzhiyun switch (data[2]) {
1243*4882a593Smuzhiyun case 2:
1244*4882a593Smuzhiyun type = EDO;
1245*4882a593Smuzhiyun puts ("EDO\n");
1246*4882a593Smuzhiyun break;
1247*4882a593Smuzhiyun case 4:
1248*4882a593Smuzhiyun type = SDRAM;
1249*4882a593Smuzhiyun puts ("SDRAM\n");
1250*4882a593Smuzhiyun break;
1251*4882a593Smuzhiyun case 7:
1252*4882a593Smuzhiyun type = DDR;
1253*4882a593Smuzhiyun puts("DDR\n");
1254*4882a593Smuzhiyun break;
1255*4882a593Smuzhiyun case 8:
1256*4882a593Smuzhiyun type = DDR2;
1257*4882a593Smuzhiyun puts ("DDR2\n");
1258*4882a593Smuzhiyun break;
1259*4882a593Smuzhiyun case 11:
1260*4882a593Smuzhiyun type = DDR3;
1261*4882a593Smuzhiyun puts("DDR3\n");
1262*4882a593Smuzhiyun break;
1263*4882a593Smuzhiyun case 12:
1264*4882a593Smuzhiyun type = DDR4;
1265*4882a593Smuzhiyun puts("DDR4\n");
1266*4882a593Smuzhiyun break;
1267*4882a593Smuzhiyun default:
1268*4882a593Smuzhiyun type = unknown;
1269*4882a593Smuzhiyun puts ("unknown\n");
1270*4882a593Smuzhiyun break;
1271*4882a593Smuzhiyun }
1272*4882a593Smuzhiyun
1273*4882a593Smuzhiyun puts ("Row address bits ");
1274*4882a593Smuzhiyun if ((data[3] & 0x00F0) == 0)
1275*4882a593Smuzhiyun printf ("%d\n", data[3] & 0x0F);
1276*4882a593Smuzhiyun else
1277*4882a593Smuzhiyun printf ("%d/%d\n", data[3] & 0x0F, (data[3] >> 4) & 0x0F);
1278*4882a593Smuzhiyun
1279*4882a593Smuzhiyun puts ("Column address bits ");
1280*4882a593Smuzhiyun if ((data[4] & 0x00F0) == 0)
1281*4882a593Smuzhiyun printf ("%d\n", data[4] & 0x0F);
1282*4882a593Smuzhiyun else
1283*4882a593Smuzhiyun printf ("%d/%d\n", data[4] & 0x0F, (data[4] >> 4) & 0x0F);
1284*4882a593Smuzhiyun
1285*4882a593Smuzhiyun switch (type) {
1286*4882a593Smuzhiyun case DDR2:
1287*4882a593Smuzhiyun printf ("Number of ranks %d\n",
1288*4882a593Smuzhiyun (data[5] & 0x07) + 1);
1289*4882a593Smuzhiyun break;
1290*4882a593Smuzhiyun default:
1291*4882a593Smuzhiyun printf ("Module rows %d\n", data[5]);
1292*4882a593Smuzhiyun break;
1293*4882a593Smuzhiyun }
1294*4882a593Smuzhiyun
1295*4882a593Smuzhiyun switch (type) {
1296*4882a593Smuzhiyun case DDR2:
1297*4882a593Smuzhiyun printf ("Module data width %d bits\n", data[6]);
1298*4882a593Smuzhiyun break;
1299*4882a593Smuzhiyun default:
1300*4882a593Smuzhiyun printf ("Module data width %d bits\n",
1301*4882a593Smuzhiyun (data[7] << 8) | data[6]);
1302*4882a593Smuzhiyun break;
1303*4882a593Smuzhiyun }
1304*4882a593Smuzhiyun
1305*4882a593Smuzhiyun puts ("Interface signal levels ");
1306*4882a593Smuzhiyun switch(data[8]) {
1307*4882a593Smuzhiyun case 0: puts ("TTL 5.0 V\n"); break;
1308*4882a593Smuzhiyun case 1: puts ("LVTTL\n"); break;
1309*4882a593Smuzhiyun case 2: puts ("HSTL 1.5 V\n"); break;
1310*4882a593Smuzhiyun case 3: puts ("SSTL 3.3 V\n"); break;
1311*4882a593Smuzhiyun case 4: puts ("SSTL 2.5 V\n"); break;
1312*4882a593Smuzhiyun case 5: puts ("SSTL 1.8 V\n"); break;
1313*4882a593Smuzhiyun default: puts ("unknown\n"); break;
1314*4882a593Smuzhiyun }
1315*4882a593Smuzhiyun
1316*4882a593Smuzhiyun switch (type) {
1317*4882a593Smuzhiyun case DDR2:
1318*4882a593Smuzhiyun printf ("SDRAM cycle time ");
1319*4882a593Smuzhiyun print_ddr2_tcyc (data[9]);
1320*4882a593Smuzhiyun break;
1321*4882a593Smuzhiyun default:
1322*4882a593Smuzhiyun printf ("SDRAM cycle time %d.%d ns\n",
1323*4882a593Smuzhiyun (data[9] >> 4) & 0x0F, data[9] & 0x0F);
1324*4882a593Smuzhiyun break;
1325*4882a593Smuzhiyun }
1326*4882a593Smuzhiyun
1327*4882a593Smuzhiyun switch (type) {
1328*4882a593Smuzhiyun case DDR2:
1329*4882a593Smuzhiyun printf ("SDRAM access time 0.%d%d ns\n",
1330*4882a593Smuzhiyun (data[10] >> 4) & 0x0F, data[10] & 0x0F);
1331*4882a593Smuzhiyun break;
1332*4882a593Smuzhiyun default:
1333*4882a593Smuzhiyun printf ("SDRAM access time %d.%d ns\n",
1334*4882a593Smuzhiyun (data[10] >> 4) & 0x0F, data[10] & 0x0F);
1335*4882a593Smuzhiyun break;
1336*4882a593Smuzhiyun }
1337*4882a593Smuzhiyun
1338*4882a593Smuzhiyun puts ("EDC configuration ");
1339*4882a593Smuzhiyun switch (data[11]) {
1340*4882a593Smuzhiyun case 0: puts ("None\n"); break;
1341*4882a593Smuzhiyun case 1: puts ("Parity\n"); break;
1342*4882a593Smuzhiyun case 2: puts ("ECC\n"); break;
1343*4882a593Smuzhiyun default: puts ("unknown\n"); break;
1344*4882a593Smuzhiyun }
1345*4882a593Smuzhiyun
1346*4882a593Smuzhiyun if ((data[12] & 0x80) == 0)
1347*4882a593Smuzhiyun puts ("No self refresh, rate ");
1348*4882a593Smuzhiyun else
1349*4882a593Smuzhiyun puts ("Self refresh, rate ");
1350*4882a593Smuzhiyun
1351*4882a593Smuzhiyun switch(data[12] & 0x7F) {
1352*4882a593Smuzhiyun case 0: puts ("15.625 us\n"); break;
1353*4882a593Smuzhiyun case 1: puts ("3.9 us\n"); break;
1354*4882a593Smuzhiyun case 2: puts ("7.8 us\n"); break;
1355*4882a593Smuzhiyun case 3: puts ("31.3 us\n"); break;
1356*4882a593Smuzhiyun case 4: puts ("62.5 us\n"); break;
1357*4882a593Smuzhiyun case 5: puts ("125 us\n"); break;
1358*4882a593Smuzhiyun default: puts ("unknown\n"); break;
1359*4882a593Smuzhiyun }
1360*4882a593Smuzhiyun
1361*4882a593Smuzhiyun switch (type) {
1362*4882a593Smuzhiyun case DDR2:
1363*4882a593Smuzhiyun printf ("SDRAM width (primary) %d\n", data[13]);
1364*4882a593Smuzhiyun break;
1365*4882a593Smuzhiyun default:
1366*4882a593Smuzhiyun printf ("SDRAM width (primary) %d\n", data[13] & 0x7F);
1367*4882a593Smuzhiyun if ((data[13] & 0x80) != 0) {
1368*4882a593Smuzhiyun printf (" (second bank) %d\n",
1369*4882a593Smuzhiyun 2 * (data[13] & 0x7F));
1370*4882a593Smuzhiyun }
1371*4882a593Smuzhiyun break;
1372*4882a593Smuzhiyun }
1373*4882a593Smuzhiyun
1374*4882a593Smuzhiyun switch (type) {
1375*4882a593Smuzhiyun case DDR2:
1376*4882a593Smuzhiyun if (data[14] != 0)
1377*4882a593Smuzhiyun printf ("EDC width %d\n", data[14]);
1378*4882a593Smuzhiyun break;
1379*4882a593Smuzhiyun default:
1380*4882a593Smuzhiyun if (data[14] != 0) {
1381*4882a593Smuzhiyun printf ("EDC width %d\n",
1382*4882a593Smuzhiyun data[14] & 0x7F);
1383*4882a593Smuzhiyun
1384*4882a593Smuzhiyun if ((data[14] & 0x80) != 0) {
1385*4882a593Smuzhiyun printf (" (second bank) %d\n",
1386*4882a593Smuzhiyun 2 * (data[14] & 0x7F));
1387*4882a593Smuzhiyun }
1388*4882a593Smuzhiyun }
1389*4882a593Smuzhiyun break;
1390*4882a593Smuzhiyun }
1391*4882a593Smuzhiyun
1392*4882a593Smuzhiyun if (DDR2 != type) {
1393*4882a593Smuzhiyun printf ("Min clock delay, back-to-back random column addresses "
1394*4882a593Smuzhiyun "%d\n", data[15]);
1395*4882a593Smuzhiyun }
1396*4882a593Smuzhiyun
1397*4882a593Smuzhiyun puts ("Burst length(s) ");
1398*4882a593Smuzhiyun if (data[16] & 0x80) puts (" Page");
1399*4882a593Smuzhiyun if (data[16] & 0x08) puts (" 8");
1400*4882a593Smuzhiyun if (data[16] & 0x04) puts (" 4");
1401*4882a593Smuzhiyun if (data[16] & 0x02) puts (" 2");
1402*4882a593Smuzhiyun if (data[16] & 0x01) puts (" 1");
1403*4882a593Smuzhiyun putc ('\n');
1404*4882a593Smuzhiyun printf ("Number of banks %d\n", data[17]);
1405*4882a593Smuzhiyun
1406*4882a593Smuzhiyun switch (type) {
1407*4882a593Smuzhiyun case DDR2:
1408*4882a593Smuzhiyun puts ("CAS latency(s) ");
1409*4882a593Smuzhiyun decode_bits (data[18], decode_CAS_DDR2, 0);
1410*4882a593Smuzhiyun putc ('\n');
1411*4882a593Smuzhiyun break;
1412*4882a593Smuzhiyun default:
1413*4882a593Smuzhiyun puts ("CAS latency(s) ");
1414*4882a593Smuzhiyun decode_bits (data[18], decode_CAS_default, 0);
1415*4882a593Smuzhiyun putc ('\n');
1416*4882a593Smuzhiyun break;
1417*4882a593Smuzhiyun }
1418*4882a593Smuzhiyun
1419*4882a593Smuzhiyun if (DDR2 != type) {
1420*4882a593Smuzhiyun puts ("CS latency(s) ");
1421*4882a593Smuzhiyun decode_bits (data[19], decode_CS_WE_default, 0);
1422*4882a593Smuzhiyun putc ('\n');
1423*4882a593Smuzhiyun }
1424*4882a593Smuzhiyun
1425*4882a593Smuzhiyun if (DDR2 != type) {
1426*4882a593Smuzhiyun puts ("WE latency(s) ");
1427*4882a593Smuzhiyun decode_bits (data[20], decode_CS_WE_default, 0);
1428*4882a593Smuzhiyun putc ('\n');
1429*4882a593Smuzhiyun }
1430*4882a593Smuzhiyun
1431*4882a593Smuzhiyun switch (type) {
1432*4882a593Smuzhiyun case DDR2:
1433*4882a593Smuzhiyun puts ("Module attributes:\n");
1434*4882a593Smuzhiyun if (data[21] & 0x80)
1435*4882a593Smuzhiyun puts (" TBD (bit 7)\n");
1436*4882a593Smuzhiyun if (data[21] & 0x40)
1437*4882a593Smuzhiyun puts (" Analysis probe installed\n");
1438*4882a593Smuzhiyun if (data[21] & 0x20)
1439*4882a593Smuzhiyun puts (" TBD (bit 5)\n");
1440*4882a593Smuzhiyun if (data[21] & 0x10)
1441*4882a593Smuzhiyun puts (" FET switch external enable\n");
1442*4882a593Smuzhiyun printf (" %d PLLs on DIMM\n", (data[21] >> 2) & 0x03);
1443*4882a593Smuzhiyun if (data[20] & 0x11) {
1444*4882a593Smuzhiyun printf (" %d active registers on DIMM\n",
1445*4882a593Smuzhiyun (data[21] & 0x03) + 1);
1446*4882a593Smuzhiyun }
1447*4882a593Smuzhiyun break;
1448*4882a593Smuzhiyun default:
1449*4882a593Smuzhiyun puts ("Module attributes:\n");
1450*4882a593Smuzhiyun if (!data[21])
1451*4882a593Smuzhiyun puts (" (none)\n");
1452*4882a593Smuzhiyun else
1453*4882a593Smuzhiyun decode_bits (data[21], decode_byte21_default, 0);
1454*4882a593Smuzhiyun break;
1455*4882a593Smuzhiyun }
1456*4882a593Smuzhiyun
1457*4882a593Smuzhiyun switch (type) {
1458*4882a593Smuzhiyun case DDR2:
1459*4882a593Smuzhiyun decode_bits (data[22], decode_byte22_DDR2, 0);
1460*4882a593Smuzhiyun break;
1461*4882a593Smuzhiyun default:
1462*4882a593Smuzhiyun puts ("Device attributes:\n");
1463*4882a593Smuzhiyun if (data[22] & 0x80) puts (" TBD (bit 7)\n");
1464*4882a593Smuzhiyun if (data[22] & 0x40) puts (" TBD (bit 6)\n");
1465*4882a593Smuzhiyun if (data[22] & 0x20) puts (" Upper Vcc tolerance 5%\n");
1466*4882a593Smuzhiyun else puts (" Upper Vcc tolerance 10%\n");
1467*4882a593Smuzhiyun if (data[22] & 0x10) puts (" Lower Vcc tolerance 5%\n");
1468*4882a593Smuzhiyun else puts (" Lower Vcc tolerance 10%\n");
1469*4882a593Smuzhiyun if (data[22] & 0x08) puts (" Supports write1/read burst\n");
1470*4882a593Smuzhiyun if (data[22] & 0x04) puts (" Supports precharge all\n");
1471*4882a593Smuzhiyun if (data[22] & 0x02) puts (" Supports auto precharge\n");
1472*4882a593Smuzhiyun if (data[22] & 0x01) puts (" Supports early RAS# precharge\n");
1473*4882a593Smuzhiyun break;
1474*4882a593Smuzhiyun }
1475*4882a593Smuzhiyun
1476*4882a593Smuzhiyun switch (type) {
1477*4882a593Smuzhiyun case DDR2:
1478*4882a593Smuzhiyun printf ("SDRAM cycle time (2nd highest CAS latency) ");
1479*4882a593Smuzhiyun print_ddr2_tcyc (data[23]);
1480*4882a593Smuzhiyun break;
1481*4882a593Smuzhiyun default:
1482*4882a593Smuzhiyun printf ("SDRAM cycle time (2nd highest CAS latency) %d."
1483*4882a593Smuzhiyun "%d ns\n", (data[23] >> 4) & 0x0F, data[23] & 0x0F);
1484*4882a593Smuzhiyun break;
1485*4882a593Smuzhiyun }
1486*4882a593Smuzhiyun
1487*4882a593Smuzhiyun switch (type) {
1488*4882a593Smuzhiyun case DDR2:
1489*4882a593Smuzhiyun printf ("SDRAM access from clock (2nd highest CAS latency) 0."
1490*4882a593Smuzhiyun "%d%d ns\n", (data[24] >> 4) & 0x0F, data[24] & 0x0F);
1491*4882a593Smuzhiyun break;
1492*4882a593Smuzhiyun default:
1493*4882a593Smuzhiyun printf ("SDRAM access from clock (2nd highest CAS latency) %d."
1494*4882a593Smuzhiyun "%d ns\n", (data[24] >> 4) & 0x0F, data[24] & 0x0F);
1495*4882a593Smuzhiyun break;
1496*4882a593Smuzhiyun }
1497*4882a593Smuzhiyun
1498*4882a593Smuzhiyun switch (type) {
1499*4882a593Smuzhiyun case DDR2:
1500*4882a593Smuzhiyun printf ("SDRAM cycle time (3rd highest CAS latency) ");
1501*4882a593Smuzhiyun print_ddr2_tcyc (data[25]);
1502*4882a593Smuzhiyun break;
1503*4882a593Smuzhiyun default:
1504*4882a593Smuzhiyun printf ("SDRAM cycle time (3rd highest CAS latency) %d."
1505*4882a593Smuzhiyun "%d ns\n", (data[25] >> 4) & 0x0F, data[25] & 0x0F);
1506*4882a593Smuzhiyun break;
1507*4882a593Smuzhiyun }
1508*4882a593Smuzhiyun
1509*4882a593Smuzhiyun switch (type) {
1510*4882a593Smuzhiyun case DDR2:
1511*4882a593Smuzhiyun printf ("SDRAM access from clock (3rd highest CAS latency) 0."
1512*4882a593Smuzhiyun "%d%d ns\n", (data[26] >> 4) & 0x0F, data[26] & 0x0F);
1513*4882a593Smuzhiyun break;
1514*4882a593Smuzhiyun default:
1515*4882a593Smuzhiyun printf ("SDRAM access from clock (3rd highest CAS latency) %d."
1516*4882a593Smuzhiyun "%d ns\n", (data[26] >> 4) & 0x0F, data[26] & 0x0F);
1517*4882a593Smuzhiyun break;
1518*4882a593Smuzhiyun }
1519*4882a593Smuzhiyun
1520*4882a593Smuzhiyun switch (type) {
1521*4882a593Smuzhiyun case DDR2:
1522*4882a593Smuzhiyun printf ("Minimum row precharge %d.%02d ns\n",
1523*4882a593Smuzhiyun (data[27] >> 2) & 0x3F, 25 * (data[27] & 0x03));
1524*4882a593Smuzhiyun break;
1525*4882a593Smuzhiyun default:
1526*4882a593Smuzhiyun printf ("Minimum row precharge %d ns\n", data[27]);
1527*4882a593Smuzhiyun break;
1528*4882a593Smuzhiyun }
1529*4882a593Smuzhiyun
1530*4882a593Smuzhiyun switch (type) {
1531*4882a593Smuzhiyun case DDR2:
1532*4882a593Smuzhiyun printf ("Row active to row active min %d.%02d ns\n",
1533*4882a593Smuzhiyun (data[28] >> 2) & 0x3F, 25 * (data[28] & 0x03));
1534*4882a593Smuzhiyun break;
1535*4882a593Smuzhiyun default:
1536*4882a593Smuzhiyun printf ("Row active to row active min %d ns\n", data[28]);
1537*4882a593Smuzhiyun break;
1538*4882a593Smuzhiyun }
1539*4882a593Smuzhiyun
1540*4882a593Smuzhiyun switch (type) {
1541*4882a593Smuzhiyun case DDR2:
1542*4882a593Smuzhiyun printf ("RAS to CAS delay min %d.%02d ns\n",
1543*4882a593Smuzhiyun (data[29] >> 2) & 0x3F, 25 * (data[29] & 0x03));
1544*4882a593Smuzhiyun break;
1545*4882a593Smuzhiyun default:
1546*4882a593Smuzhiyun printf ("RAS to CAS delay min %d ns\n", data[29]);
1547*4882a593Smuzhiyun break;
1548*4882a593Smuzhiyun }
1549*4882a593Smuzhiyun
1550*4882a593Smuzhiyun printf ("Minimum RAS pulse width %d ns\n", data[30]);
1551*4882a593Smuzhiyun
1552*4882a593Smuzhiyun switch (type) {
1553*4882a593Smuzhiyun case DDR2:
1554*4882a593Smuzhiyun puts ("Density of each row ");
1555*4882a593Smuzhiyun decode_bits (data[31], decode_row_density_DDR2, 1);
1556*4882a593Smuzhiyun putc ('\n');
1557*4882a593Smuzhiyun break;
1558*4882a593Smuzhiyun default:
1559*4882a593Smuzhiyun puts ("Density of each row ");
1560*4882a593Smuzhiyun decode_bits (data[31], decode_row_density_default, 1);
1561*4882a593Smuzhiyun putc ('\n');
1562*4882a593Smuzhiyun break;
1563*4882a593Smuzhiyun }
1564*4882a593Smuzhiyun
1565*4882a593Smuzhiyun switch (type) {
1566*4882a593Smuzhiyun case DDR2:
1567*4882a593Smuzhiyun puts ("Command and Address setup ");
1568*4882a593Smuzhiyun if (data[32] >= 0xA0) {
1569*4882a593Smuzhiyun printf ("1.%d%d ns\n",
1570*4882a593Smuzhiyun ((data[32] >> 4) & 0x0F) - 10, data[32] & 0x0F);
1571*4882a593Smuzhiyun } else {
1572*4882a593Smuzhiyun printf ("0.%d%d ns\n",
1573*4882a593Smuzhiyun ((data[32] >> 4) & 0x0F), data[32] & 0x0F);
1574*4882a593Smuzhiyun }
1575*4882a593Smuzhiyun break;
1576*4882a593Smuzhiyun default:
1577*4882a593Smuzhiyun printf ("Command and Address setup %c%d.%d ns\n",
1578*4882a593Smuzhiyun (data[32] & 0x80) ? '-' : '+',
1579*4882a593Smuzhiyun (data[32] >> 4) & 0x07, data[32] & 0x0F);
1580*4882a593Smuzhiyun break;
1581*4882a593Smuzhiyun }
1582*4882a593Smuzhiyun
1583*4882a593Smuzhiyun switch (type) {
1584*4882a593Smuzhiyun case DDR2:
1585*4882a593Smuzhiyun puts ("Command and Address hold ");
1586*4882a593Smuzhiyun if (data[33] >= 0xA0) {
1587*4882a593Smuzhiyun printf ("1.%d%d ns\n",
1588*4882a593Smuzhiyun ((data[33] >> 4) & 0x0F) - 10, data[33] & 0x0F);
1589*4882a593Smuzhiyun } else {
1590*4882a593Smuzhiyun printf ("0.%d%d ns\n",
1591*4882a593Smuzhiyun ((data[33] >> 4) & 0x0F), data[33] & 0x0F);
1592*4882a593Smuzhiyun }
1593*4882a593Smuzhiyun break;
1594*4882a593Smuzhiyun default:
1595*4882a593Smuzhiyun printf ("Command and Address hold %c%d.%d ns\n",
1596*4882a593Smuzhiyun (data[33] & 0x80) ? '-' : '+',
1597*4882a593Smuzhiyun (data[33] >> 4) & 0x07, data[33] & 0x0F);
1598*4882a593Smuzhiyun break;
1599*4882a593Smuzhiyun }
1600*4882a593Smuzhiyun
1601*4882a593Smuzhiyun switch (type) {
1602*4882a593Smuzhiyun case DDR2:
1603*4882a593Smuzhiyun printf ("Data signal input setup 0.%d%d ns\n",
1604*4882a593Smuzhiyun (data[34] >> 4) & 0x0F, data[34] & 0x0F);
1605*4882a593Smuzhiyun break;
1606*4882a593Smuzhiyun default:
1607*4882a593Smuzhiyun printf ("Data signal input setup %c%d.%d ns\n",
1608*4882a593Smuzhiyun (data[34] & 0x80) ? '-' : '+',
1609*4882a593Smuzhiyun (data[34] >> 4) & 0x07, data[34] & 0x0F);
1610*4882a593Smuzhiyun break;
1611*4882a593Smuzhiyun }
1612*4882a593Smuzhiyun
1613*4882a593Smuzhiyun switch (type) {
1614*4882a593Smuzhiyun case DDR2:
1615*4882a593Smuzhiyun printf ("Data signal input hold 0.%d%d ns\n",
1616*4882a593Smuzhiyun (data[35] >> 4) & 0x0F, data[35] & 0x0F);
1617*4882a593Smuzhiyun break;
1618*4882a593Smuzhiyun default:
1619*4882a593Smuzhiyun printf ("Data signal input hold %c%d.%d ns\n",
1620*4882a593Smuzhiyun (data[35] & 0x80) ? '-' : '+',
1621*4882a593Smuzhiyun (data[35] >> 4) & 0x07, data[35] & 0x0F);
1622*4882a593Smuzhiyun break;
1623*4882a593Smuzhiyun }
1624*4882a593Smuzhiyun
1625*4882a593Smuzhiyun puts ("Manufacturer's JEDEC ID ");
1626*4882a593Smuzhiyun for (j = 64; j <= 71; j++)
1627*4882a593Smuzhiyun printf ("%02X ", data[j]);
1628*4882a593Smuzhiyun putc ('\n');
1629*4882a593Smuzhiyun printf ("Manufacturing Location %02X\n", data[72]);
1630*4882a593Smuzhiyun puts ("Manufacturer's Part Number ");
1631*4882a593Smuzhiyun for (j = 73; j <= 90; j++)
1632*4882a593Smuzhiyun printf ("%02X ", data[j]);
1633*4882a593Smuzhiyun putc ('\n');
1634*4882a593Smuzhiyun printf ("Revision Code %02X %02X\n", data[91], data[92]);
1635*4882a593Smuzhiyun printf ("Manufacturing Date %02X %02X\n", data[93], data[94]);
1636*4882a593Smuzhiyun puts ("Assembly Serial Number ");
1637*4882a593Smuzhiyun for (j = 95; j <= 98; j++)
1638*4882a593Smuzhiyun printf ("%02X ", data[j]);
1639*4882a593Smuzhiyun putc ('\n');
1640*4882a593Smuzhiyun
1641*4882a593Smuzhiyun if (DDR2 != type) {
1642*4882a593Smuzhiyun printf ("Speed rating PC%d\n",
1643*4882a593Smuzhiyun data[126] == 0x66 ? 66 : data[126]);
1644*4882a593Smuzhiyun }
1645*4882a593Smuzhiyun return 0;
1646*4882a593Smuzhiyun }
1647*4882a593Smuzhiyun #endif
1648*4882a593Smuzhiyun
1649*4882a593Smuzhiyun /*
1650*4882a593Smuzhiyun * Syntax:
1651*4882a593Smuzhiyun * i2c edid {i2c_chip}
1652*4882a593Smuzhiyun */
1653*4882a593Smuzhiyun #if defined(CONFIG_I2C_EDID)
do_edid(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])1654*4882a593Smuzhiyun int do_edid(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1655*4882a593Smuzhiyun {
1656*4882a593Smuzhiyun uint chip;
1657*4882a593Smuzhiyun struct edid1_info edid;
1658*4882a593Smuzhiyun int ret;
1659*4882a593Smuzhiyun #ifdef CONFIG_DM_I2C
1660*4882a593Smuzhiyun struct udevice *dev;
1661*4882a593Smuzhiyun #endif
1662*4882a593Smuzhiyun
1663*4882a593Smuzhiyun if (argc < 2) {
1664*4882a593Smuzhiyun cmd_usage(cmdtp);
1665*4882a593Smuzhiyun return 1;
1666*4882a593Smuzhiyun }
1667*4882a593Smuzhiyun
1668*4882a593Smuzhiyun chip = simple_strtoul(argv[1], NULL, 16);
1669*4882a593Smuzhiyun #ifdef CONFIG_DM_I2C
1670*4882a593Smuzhiyun ret = i2c_get_cur_bus_chip(chip, &dev);
1671*4882a593Smuzhiyun if (!ret)
1672*4882a593Smuzhiyun ret = dm_i2c_read(dev, 0, (uchar *)&edid, sizeof(edid));
1673*4882a593Smuzhiyun #else
1674*4882a593Smuzhiyun ret = i2c_read(chip, 0, 1, (uchar *)&edid, sizeof(edid));
1675*4882a593Smuzhiyun #endif
1676*4882a593Smuzhiyun if (ret)
1677*4882a593Smuzhiyun return i2c_report_err(ret, I2C_ERR_READ);
1678*4882a593Smuzhiyun
1679*4882a593Smuzhiyun if (edid_check_info(&edid)) {
1680*4882a593Smuzhiyun puts("Content isn't valid EDID.\n");
1681*4882a593Smuzhiyun return 1;
1682*4882a593Smuzhiyun }
1683*4882a593Smuzhiyun
1684*4882a593Smuzhiyun edid_print_info(&edid);
1685*4882a593Smuzhiyun return 0;
1686*4882a593Smuzhiyun
1687*4882a593Smuzhiyun }
1688*4882a593Smuzhiyun #endif /* CONFIG_I2C_EDID */
1689*4882a593Smuzhiyun
1690*4882a593Smuzhiyun #ifdef CONFIG_DM_I2C
show_bus(struct udevice * bus)1691*4882a593Smuzhiyun static void show_bus(struct udevice *bus)
1692*4882a593Smuzhiyun {
1693*4882a593Smuzhiyun struct udevice *dev;
1694*4882a593Smuzhiyun
1695*4882a593Smuzhiyun printf("Bus %d:\t%s", bus->req_seq, bus->name);
1696*4882a593Smuzhiyun if (device_active(bus))
1697*4882a593Smuzhiyun printf(" (active %d)", bus->seq);
1698*4882a593Smuzhiyun printf("\n");
1699*4882a593Smuzhiyun for (device_find_first_child(bus, &dev);
1700*4882a593Smuzhiyun dev;
1701*4882a593Smuzhiyun device_find_next_child(&dev)) {
1702*4882a593Smuzhiyun struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
1703*4882a593Smuzhiyun
1704*4882a593Smuzhiyun printf(" %02x: %s, offset len %x, flags %x\n",
1705*4882a593Smuzhiyun chip->chip_addr, dev->name, chip->offset_len,
1706*4882a593Smuzhiyun chip->flags);
1707*4882a593Smuzhiyun }
1708*4882a593Smuzhiyun }
1709*4882a593Smuzhiyun #endif
1710*4882a593Smuzhiyun
1711*4882a593Smuzhiyun /**
1712*4882a593Smuzhiyun * do_i2c_show_bus() - Handle the "i2c bus" command-line command
1713*4882a593Smuzhiyun * @cmdtp: Command data struct pointer
1714*4882a593Smuzhiyun * @flag: Command flag
1715*4882a593Smuzhiyun * @argc: Command-line argument count
1716*4882a593Smuzhiyun * @argv: Array of command-line arguments
1717*4882a593Smuzhiyun *
1718*4882a593Smuzhiyun * Returns zero always.
1719*4882a593Smuzhiyun */
1720*4882a593Smuzhiyun #if defined(CONFIG_SYS_I2C) || defined(CONFIG_DM_I2C)
do_i2c_show_bus(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])1721*4882a593Smuzhiyun static int do_i2c_show_bus(cmd_tbl_t *cmdtp, int flag, int argc,
1722*4882a593Smuzhiyun char * const argv[])
1723*4882a593Smuzhiyun {
1724*4882a593Smuzhiyun if (argc == 1) {
1725*4882a593Smuzhiyun /* show all busses */
1726*4882a593Smuzhiyun #ifdef CONFIG_DM_I2C
1727*4882a593Smuzhiyun struct udevice *bus;
1728*4882a593Smuzhiyun struct uclass *uc;
1729*4882a593Smuzhiyun int ret;
1730*4882a593Smuzhiyun
1731*4882a593Smuzhiyun ret = uclass_get(UCLASS_I2C, &uc);
1732*4882a593Smuzhiyun if (ret)
1733*4882a593Smuzhiyun return CMD_RET_FAILURE;
1734*4882a593Smuzhiyun uclass_foreach_dev(bus, uc)
1735*4882a593Smuzhiyun show_bus(bus);
1736*4882a593Smuzhiyun #else
1737*4882a593Smuzhiyun int i;
1738*4882a593Smuzhiyun
1739*4882a593Smuzhiyun for (i = 0; i < CONFIG_SYS_NUM_I2C_BUSES; i++) {
1740*4882a593Smuzhiyun printf("Bus %d:\t%s", i, I2C_ADAP_NR(i)->name);
1741*4882a593Smuzhiyun #ifndef CONFIG_SYS_I2C_DIRECT_BUS
1742*4882a593Smuzhiyun int j;
1743*4882a593Smuzhiyun
1744*4882a593Smuzhiyun for (j = 0; j < CONFIG_SYS_I2C_MAX_HOPS; j++) {
1745*4882a593Smuzhiyun if (i2c_bus[i].next_hop[j].chip == 0)
1746*4882a593Smuzhiyun break;
1747*4882a593Smuzhiyun printf("->%s@0x%2x:%d",
1748*4882a593Smuzhiyun i2c_bus[i].next_hop[j].mux.name,
1749*4882a593Smuzhiyun i2c_bus[i].next_hop[j].chip,
1750*4882a593Smuzhiyun i2c_bus[i].next_hop[j].channel);
1751*4882a593Smuzhiyun }
1752*4882a593Smuzhiyun #endif
1753*4882a593Smuzhiyun printf("\n");
1754*4882a593Smuzhiyun }
1755*4882a593Smuzhiyun #endif
1756*4882a593Smuzhiyun } else {
1757*4882a593Smuzhiyun int i;
1758*4882a593Smuzhiyun
1759*4882a593Smuzhiyun /* show specific bus */
1760*4882a593Smuzhiyun i = simple_strtoul(argv[1], NULL, 10);
1761*4882a593Smuzhiyun #ifdef CONFIG_DM_I2C
1762*4882a593Smuzhiyun struct udevice *bus;
1763*4882a593Smuzhiyun int ret;
1764*4882a593Smuzhiyun
1765*4882a593Smuzhiyun ret = uclass_get_device_by_seq(UCLASS_I2C, i, &bus);
1766*4882a593Smuzhiyun if (ret) {
1767*4882a593Smuzhiyun printf("Invalid bus %d: err=%d\n", i, ret);
1768*4882a593Smuzhiyun return CMD_RET_FAILURE;
1769*4882a593Smuzhiyun }
1770*4882a593Smuzhiyun show_bus(bus);
1771*4882a593Smuzhiyun #else
1772*4882a593Smuzhiyun if (i >= CONFIG_SYS_NUM_I2C_BUSES) {
1773*4882a593Smuzhiyun printf("Invalid bus %d\n", i);
1774*4882a593Smuzhiyun return -1;
1775*4882a593Smuzhiyun }
1776*4882a593Smuzhiyun printf("Bus %d:\t%s", i, I2C_ADAP_NR(i)->name);
1777*4882a593Smuzhiyun #ifndef CONFIG_SYS_I2C_DIRECT_BUS
1778*4882a593Smuzhiyun int j;
1779*4882a593Smuzhiyun for (j = 0; j < CONFIG_SYS_I2C_MAX_HOPS; j++) {
1780*4882a593Smuzhiyun if (i2c_bus[i].next_hop[j].chip == 0)
1781*4882a593Smuzhiyun break;
1782*4882a593Smuzhiyun printf("->%s@0x%2x:%d",
1783*4882a593Smuzhiyun i2c_bus[i].next_hop[j].mux.name,
1784*4882a593Smuzhiyun i2c_bus[i].next_hop[j].chip,
1785*4882a593Smuzhiyun i2c_bus[i].next_hop[j].channel);
1786*4882a593Smuzhiyun }
1787*4882a593Smuzhiyun #endif
1788*4882a593Smuzhiyun printf("\n");
1789*4882a593Smuzhiyun #endif
1790*4882a593Smuzhiyun }
1791*4882a593Smuzhiyun
1792*4882a593Smuzhiyun return 0;
1793*4882a593Smuzhiyun }
1794*4882a593Smuzhiyun #endif
1795*4882a593Smuzhiyun
1796*4882a593Smuzhiyun /**
1797*4882a593Smuzhiyun * do_i2c_bus_num() - Handle the "i2c dev" command-line command
1798*4882a593Smuzhiyun * @cmdtp: Command data struct pointer
1799*4882a593Smuzhiyun * @flag: Command flag
1800*4882a593Smuzhiyun * @argc: Command-line argument count
1801*4882a593Smuzhiyun * @argv: Array of command-line arguments
1802*4882a593Smuzhiyun *
1803*4882a593Smuzhiyun * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
1804*4882a593Smuzhiyun * on error.
1805*4882a593Smuzhiyun */
1806*4882a593Smuzhiyun #if defined(CONFIG_SYS_I2C) || defined(CONFIG_I2C_MULTI_BUS) || \
1807*4882a593Smuzhiyun defined(CONFIG_DM_I2C)
do_i2c_bus_num(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])1808*4882a593Smuzhiyun static int do_i2c_bus_num(cmd_tbl_t *cmdtp, int flag, int argc,
1809*4882a593Smuzhiyun char * const argv[])
1810*4882a593Smuzhiyun {
1811*4882a593Smuzhiyun int ret = 0;
1812*4882a593Smuzhiyun int bus_no;
1813*4882a593Smuzhiyun
1814*4882a593Smuzhiyun if (argc == 1) {
1815*4882a593Smuzhiyun /* querying current setting */
1816*4882a593Smuzhiyun #ifdef CONFIG_DM_I2C
1817*4882a593Smuzhiyun struct udevice *bus;
1818*4882a593Smuzhiyun
1819*4882a593Smuzhiyun if (!i2c_get_cur_bus(&bus))
1820*4882a593Smuzhiyun bus_no = bus->seq;
1821*4882a593Smuzhiyun else
1822*4882a593Smuzhiyun bus_no = -1;
1823*4882a593Smuzhiyun #else
1824*4882a593Smuzhiyun bus_no = i2c_get_bus_num();
1825*4882a593Smuzhiyun #endif
1826*4882a593Smuzhiyun printf("Current bus is %d\n", bus_no);
1827*4882a593Smuzhiyun } else {
1828*4882a593Smuzhiyun bus_no = simple_strtoul(argv[1], NULL, 10);
1829*4882a593Smuzhiyun #if defined(CONFIG_SYS_I2C)
1830*4882a593Smuzhiyun if (bus_no >= CONFIG_SYS_NUM_I2C_BUSES) {
1831*4882a593Smuzhiyun printf("Invalid bus %d\n", bus_no);
1832*4882a593Smuzhiyun return -1;
1833*4882a593Smuzhiyun }
1834*4882a593Smuzhiyun #endif
1835*4882a593Smuzhiyun printf("Setting bus to %d\n", bus_no);
1836*4882a593Smuzhiyun #ifdef CONFIG_DM_I2C
1837*4882a593Smuzhiyun ret = cmd_i2c_set_bus_num(bus_no);
1838*4882a593Smuzhiyun #else
1839*4882a593Smuzhiyun ret = i2c_set_bus_num(bus_no);
1840*4882a593Smuzhiyun #endif
1841*4882a593Smuzhiyun if (ret)
1842*4882a593Smuzhiyun printf("Failure changing bus number (%d)\n", ret);
1843*4882a593Smuzhiyun }
1844*4882a593Smuzhiyun
1845*4882a593Smuzhiyun return ret ? CMD_RET_FAILURE : 0;
1846*4882a593Smuzhiyun }
1847*4882a593Smuzhiyun #endif /* defined(CONFIG_SYS_I2C) */
1848*4882a593Smuzhiyun
1849*4882a593Smuzhiyun /**
1850*4882a593Smuzhiyun * do_i2c_bus_speed() - Handle the "i2c speed" command-line command
1851*4882a593Smuzhiyun * @cmdtp: Command data struct pointer
1852*4882a593Smuzhiyun * @flag: Command flag
1853*4882a593Smuzhiyun * @argc: Command-line argument count
1854*4882a593Smuzhiyun * @argv: Array of command-line arguments
1855*4882a593Smuzhiyun *
1856*4882a593Smuzhiyun * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
1857*4882a593Smuzhiyun * on error.
1858*4882a593Smuzhiyun */
do_i2c_bus_speed(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])1859*4882a593Smuzhiyun static int do_i2c_bus_speed(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
1860*4882a593Smuzhiyun {
1861*4882a593Smuzhiyun int speed, ret=0;
1862*4882a593Smuzhiyun
1863*4882a593Smuzhiyun #ifdef CONFIG_DM_I2C
1864*4882a593Smuzhiyun struct udevice *bus;
1865*4882a593Smuzhiyun
1866*4882a593Smuzhiyun if (i2c_get_cur_bus(&bus))
1867*4882a593Smuzhiyun return 1;
1868*4882a593Smuzhiyun #endif
1869*4882a593Smuzhiyun if (argc == 1) {
1870*4882a593Smuzhiyun #ifdef CONFIG_DM_I2C
1871*4882a593Smuzhiyun speed = dm_i2c_get_bus_speed(bus);
1872*4882a593Smuzhiyun #else
1873*4882a593Smuzhiyun speed = i2c_get_bus_speed();
1874*4882a593Smuzhiyun #endif
1875*4882a593Smuzhiyun /* querying current speed */
1876*4882a593Smuzhiyun printf("Current bus speed=%d\n", speed);
1877*4882a593Smuzhiyun } else {
1878*4882a593Smuzhiyun speed = simple_strtoul(argv[1], NULL, 10);
1879*4882a593Smuzhiyun printf("Setting bus speed to %d Hz\n", speed);
1880*4882a593Smuzhiyun #ifdef CONFIG_DM_I2C
1881*4882a593Smuzhiyun ret = dm_i2c_set_bus_speed(bus, speed);
1882*4882a593Smuzhiyun #else
1883*4882a593Smuzhiyun ret = i2c_set_bus_speed(speed);
1884*4882a593Smuzhiyun #endif
1885*4882a593Smuzhiyun if (ret)
1886*4882a593Smuzhiyun printf("Failure changing bus speed (%d)\n", ret);
1887*4882a593Smuzhiyun }
1888*4882a593Smuzhiyun
1889*4882a593Smuzhiyun return ret ? CMD_RET_FAILURE : 0;
1890*4882a593Smuzhiyun }
1891*4882a593Smuzhiyun
1892*4882a593Smuzhiyun /**
1893*4882a593Smuzhiyun * do_i2c_mm() - Handle the "i2c mm" command-line command
1894*4882a593Smuzhiyun * @cmdtp: Command data struct pointer
1895*4882a593Smuzhiyun * @flag: Command flag
1896*4882a593Smuzhiyun * @argc: Command-line argument count
1897*4882a593Smuzhiyun * @argv: Array of command-line arguments
1898*4882a593Smuzhiyun *
1899*4882a593Smuzhiyun * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
1900*4882a593Smuzhiyun * on error.
1901*4882a593Smuzhiyun */
do_i2c_mm(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])1902*4882a593Smuzhiyun static int do_i2c_mm(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
1903*4882a593Smuzhiyun {
1904*4882a593Smuzhiyun return mod_i2c_mem (cmdtp, 1, flag, argc, argv);
1905*4882a593Smuzhiyun }
1906*4882a593Smuzhiyun
1907*4882a593Smuzhiyun /**
1908*4882a593Smuzhiyun * do_i2c_nm() - Handle the "i2c nm" command-line command
1909*4882a593Smuzhiyun * @cmdtp: Command data struct pointer
1910*4882a593Smuzhiyun * @flag: Command flag
1911*4882a593Smuzhiyun * @argc: Command-line argument count
1912*4882a593Smuzhiyun * @argv: Array of command-line arguments
1913*4882a593Smuzhiyun *
1914*4882a593Smuzhiyun * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
1915*4882a593Smuzhiyun * on error.
1916*4882a593Smuzhiyun */
do_i2c_nm(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])1917*4882a593Smuzhiyun static int do_i2c_nm(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
1918*4882a593Smuzhiyun {
1919*4882a593Smuzhiyun return mod_i2c_mem (cmdtp, 0, flag, argc, argv);
1920*4882a593Smuzhiyun }
1921*4882a593Smuzhiyun
1922*4882a593Smuzhiyun /**
1923*4882a593Smuzhiyun * do_i2c_reset() - Handle the "i2c reset" command-line command
1924*4882a593Smuzhiyun * @cmdtp: Command data struct pointer
1925*4882a593Smuzhiyun * @flag: Command flag
1926*4882a593Smuzhiyun * @argc: Command-line argument count
1927*4882a593Smuzhiyun * @argv: Array of command-line arguments
1928*4882a593Smuzhiyun *
1929*4882a593Smuzhiyun * Returns zero always.
1930*4882a593Smuzhiyun */
do_i2c_reset(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])1931*4882a593Smuzhiyun static int do_i2c_reset(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
1932*4882a593Smuzhiyun {
1933*4882a593Smuzhiyun #if defined(CONFIG_DM_I2C)
1934*4882a593Smuzhiyun struct udevice *bus;
1935*4882a593Smuzhiyun
1936*4882a593Smuzhiyun if (i2c_get_cur_bus(&bus))
1937*4882a593Smuzhiyun return CMD_RET_FAILURE;
1938*4882a593Smuzhiyun if (i2c_deblock(bus)) {
1939*4882a593Smuzhiyun printf("Error: Not supported by the driver\n");
1940*4882a593Smuzhiyun return CMD_RET_FAILURE;
1941*4882a593Smuzhiyun }
1942*4882a593Smuzhiyun #elif defined(CONFIG_SYS_I2C)
1943*4882a593Smuzhiyun i2c_init(I2C_ADAP->speed, I2C_ADAP->slaveaddr);
1944*4882a593Smuzhiyun #else
1945*4882a593Smuzhiyun i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
1946*4882a593Smuzhiyun #endif
1947*4882a593Smuzhiyun return 0;
1948*4882a593Smuzhiyun }
1949*4882a593Smuzhiyun
1950*4882a593Smuzhiyun static cmd_tbl_t cmd_i2c_sub[] = {
1951*4882a593Smuzhiyun #if defined(CONFIG_SYS_I2C) || defined(CONFIG_DM_I2C)
1952*4882a593Smuzhiyun U_BOOT_CMD_MKENT(bus, 1, 1, do_i2c_show_bus, "", ""),
1953*4882a593Smuzhiyun #endif
1954*4882a593Smuzhiyun U_BOOT_CMD_MKENT(crc32, 3, 1, do_i2c_crc, "", ""),
1955*4882a593Smuzhiyun #if defined(CONFIG_SYS_I2C) || \
1956*4882a593Smuzhiyun defined(CONFIG_I2C_MULTI_BUS) || defined(CONFIG_DM_I2C)
1957*4882a593Smuzhiyun U_BOOT_CMD_MKENT(dev, 1, 1, do_i2c_bus_num, "", ""),
1958*4882a593Smuzhiyun #endif /* CONFIG_I2C_MULTI_BUS */
1959*4882a593Smuzhiyun #if defined(CONFIG_I2C_EDID)
1960*4882a593Smuzhiyun U_BOOT_CMD_MKENT(edid, 1, 1, do_edid, "", ""),
1961*4882a593Smuzhiyun #endif /* CONFIG_I2C_EDID */
1962*4882a593Smuzhiyun U_BOOT_CMD_MKENT(loop, 3, 1, do_i2c_loop, "", ""),
1963*4882a593Smuzhiyun U_BOOT_CMD_MKENT(md, 3, 1, do_i2c_md, "", ""),
1964*4882a593Smuzhiyun U_BOOT_CMD_MKENT(mm, 2, 1, do_i2c_mm, "", ""),
1965*4882a593Smuzhiyun U_BOOT_CMD_MKENT(mw, 3, 1, do_i2c_mw, "", ""),
1966*4882a593Smuzhiyun U_BOOT_CMD_MKENT(nm, 2, 1, do_i2c_nm, "", ""),
1967*4882a593Smuzhiyun U_BOOT_CMD_MKENT(probe, 0, 1, do_i2c_probe, "", ""),
1968*4882a593Smuzhiyun U_BOOT_CMD_MKENT(read, 5, 1, do_i2c_read, "", ""),
1969*4882a593Smuzhiyun U_BOOT_CMD_MKENT(write, 6, 0, do_i2c_write, "", ""),
1970*4882a593Smuzhiyun #ifdef CONFIG_DM_I2C
1971*4882a593Smuzhiyun U_BOOT_CMD_MKENT(flags, 2, 1, do_i2c_flags, "", ""),
1972*4882a593Smuzhiyun U_BOOT_CMD_MKENT(olen, 2, 1, do_i2c_olen, "", ""),
1973*4882a593Smuzhiyun #endif
1974*4882a593Smuzhiyun U_BOOT_CMD_MKENT(reset, 0, 1, do_i2c_reset, "", ""),
1975*4882a593Smuzhiyun #if defined(CONFIG_CMD_SDRAM)
1976*4882a593Smuzhiyun U_BOOT_CMD_MKENT(sdram, 1, 1, do_sdram, "", ""),
1977*4882a593Smuzhiyun #endif
1978*4882a593Smuzhiyun U_BOOT_CMD_MKENT(speed, 1, 1, do_i2c_bus_speed, "", ""),
1979*4882a593Smuzhiyun };
1980*4882a593Smuzhiyun
i2c_reloc(void)1981*4882a593Smuzhiyun static __maybe_unused void i2c_reloc(void)
1982*4882a593Smuzhiyun {
1983*4882a593Smuzhiyun static int relocated;
1984*4882a593Smuzhiyun
1985*4882a593Smuzhiyun if (!relocated) {
1986*4882a593Smuzhiyun fixup_cmdtable(cmd_i2c_sub, ARRAY_SIZE(cmd_i2c_sub));
1987*4882a593Smuzhiyun relocated = 1;
1988*4882a593Smuzhiyun };
1989*4882a593Smuzhiyun }
1990*4882a593Smuzhiyun
1991*4882a593Smuzhiyun /**
1992*4882a593Smuzhiyun * do_i2c() - Handle the "i2c" command-line command
1993*4882a593Smuzhiyun * @cmdtp: Command data struct pointer
1994*4882a593Smuzhiyun * @flag: Command flag
1995*4882a593Smuzhiyun * @argc: Command-line argument count
1996*4882a593Smuzhiyun * @argv: Array of command-line arguments
1997*4882a593Smuzhiyun *
1998*4882a593Smuzhiyun * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
1999*4882a593Smuzhiyun * on error.
2000*4882a593Smuzhiyun */
do_i2c(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])2001*4882a593Smuzhiyun static int do_i2c(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
2002*4882a593Smuzhiyun {
2003*4882a593Smuzhiyun cmd_tbl_t *c;
2004*4882a593Smuzhiyun
2005*4882a593Smuzhiyun #ifdef CONFIG_NEEDS_MANUAL_RELOC
2006*4882a593Smuzhiyun i2c_reloc();
2007*4882a593Smuzhiyun #endif
2008*4882a593Smuzhiyun
2009*4882a593Smuzhiyun if (argc < 2)
2010*4882a593Smuzhiyun return CMD_RET_USAGE;
2011*4882a593Smuzhiyun
2012*4882a593Smuzhiyun /* Strip off leading 'i2c' command argument */
2013*4882a593Smuzhiyun argc--;
2014*4882a593Smuzhiyun argv++;
2015*4882a593Smuzhiyun
2016*4882a593Smuzhiyun c = find_cmd_tbl(argv[0], &cmd_i2c_sub[0], ARRAY_SIZE(cmd_i2c_sub));
2017*4882a593Smuzhiyun
2018*4882a593Smuzhiyun if (c)
2019*4882a593Smuzhiyun return c->cmd(cmdtp, flag, argc, argv);
2020*4882a593Smuzhiyun else
2021*4882a593Smuzhiyun return CMD_RET_USAGE;
2022*4882a593Smuzhiyun }
2023*4882a593Smuzhiyun
2024*4882a593Smuzhiyun /***************************************************/
2025*4882a593Smuzhiyun #ifdef CONFIG_SYS_LONGHELP
2026*4882a593Smuzhiyun static char i2c_help_text[] =
2027*4882a593Smuzhiyun #if defined(CONFIG_SYS_I2C) || defined(CONFIG_DM_I2C)
2028*4882a593Smuzhiyun "bus [muxtype:muxaddr:muxchannel] - show I2C bus info\n"
2029*4882a593Smuzhiyun #endif
2030*4882a593Smuzhiyun "crc32 chip address[.0, .1, .2] count - compute CRC32 checksum\n"
2031*4882a593Smuzhiyun #if defined(CONFIG_SYS_I2C) || \
2032*4882a593Smuzhiyun defined(CONFIG_I2C_MULTI_BUS) || defined(CONFIG_DM_I2C)
2033*4882a593Smuzhiyun "i2c dev [dev] - show or set current I2C bus\n"
2034*4882a593Smuzhiyun #endif /* CONFIG_I2C_MULTI_BUS */
2035*4882a593Smuzhiyun #if defined(CONFIG_I2C_EDID)
2036*4882a593Smuzhiyun "i2c edid chip - print EDID configuration information\n"
2037*4882a593Smuzhiyun #endif /* CONFIG_I2C_EDID */
2038*4882a593Smuzhiyun "i2c loop chip address[.0, .1, .2] [# of objects] - looping read of device\n"
2039*4882a593Smuzhiyun "i2c md chip address[.0, .1, .2] [# of objects] - read from I2C device\n"
2040*4882a593Smuzhiyun "i2c mm chip address[.0, .1, .2] - write to I2C device (auto-incrementing)\n"
2041*4882a593Smuzhiyun "i2c mw chip address[.0, .1, .2] value [count] - write to I2C device (fill)\n"
2042*4882a593Smuzhiyun "i2c nm chip address[.0, .1, .2] - write to I2C device (constant address)\n"
2043*4882a593Smuzhiyun "i2c probe [address] - test for and show device(s) on the I2C bus\n"
2044*4882a593Smuzhiyun "i2c read chip address[.0, .1, .2] length memaddress - read to memory\n"
2045*4882a593Smuzhiyun "i2c write memaddress chip address[.0, .1, .2] length [-s] - write memory\n"
2046*4882a593Smuzhiyun " to I2C; the -s option selects bulk write in a single transaction\n"
2047*4882a593Smuzhiyun #ifdef CONFIG_DM_I2C
2048*4882a593Smuzhiyun "i2c flags chip [flags] - set or get chip flags\n"
2049*4882a593Smuzhiyun "i2c olen chip [offset_length] - set or get chip offset length\n"
2050*4882a593Smuzhiyun #endif
2051*4882a593Smuzhiyun "i2c reset - re-init the I2C Controller\n"
2052*4882a593Smuzhiyun #if defined(CONFIG_CMD_SDRAM)
2053*4882a593Smuzhiyun "i2c sdram chip - print SDRAM configuration information\n"
2054*4882a593Smuzhiyun #endif
2055*4882a593Smuzhiyun "i2c speed [speed] - show or set I2C bus speed";
2056*4882a593Smuzhiyun #endif
2057*4882a593Smuzhiyun
2058*4882a593Smuzhiyun U_BOOT_CMD(
2059*4882a593Smuzhiyun i2c, 7, 1, do_i2c,
2060*4882a593Smuzhiyun "I2C sub-system",
2061*4882a593Smuzhiyun i2c_help_text
2062*4882a593Smuzhiyun );
2063