1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2008 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <i2c.h>
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <fsl_ddr_sdram.h>
11*4882a593Smuzhiyun #include <fsl_ddr_dimm_params.h>
12*4882a593Smuzhiyun
get_spd(ddr2_spd_eeprom_t * spd,unsigned char i2c_address)13*4882a593Smuzhiyun void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
14*4882a593Smuzhiyun {
15*4882a593Smuzhiyun i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun /* We use soldered memory, but use an SPD EEPROM to describe it.
18*4882a593Smuzhiyun * The SPD has an unspecified dimm type, but the DDR2 initialization
19*4882a593Smuzhiyun * code requires a specific type to be specified. This sets the type
20*4882a593Smuzhiyun * as a standard unregistered SO-DIMM. */
21*4882a593Smuzhiyun if (spd->dimm_type == 0) {
22*4882a593Smuzhiyun spd->dimm_type = 0x4;
23*4882a593Smuzhiyun ((uchar *)spd)[63] += 0x4;
24*4882a593Smuzhiyun }
25*4882a593Smuzhiyun }
26*4882a593Smuzhiyun
fsl_ddr_board_options(memctl_options_t * popts,dimm_params_t * pdimm,unsigned int ctrl_num)27*4882a593Smuzhiyun void fsl_ddr_board_options(memctl_options_t *popts,
28*4882a593Smuzhiyun dimm_params_t *pdimm,
29*4882a593Smuzhiyun unsigned int ctrl_num)
30*4882a593Smuzhiyun {
31*4882a593Smuzhiyun /*
32*4882a593Smuzhiyun * Factors to consider for clock adjust:
33*4882a593Smuzhiyun * - number of chips on bus
34*4882a593Smuzhiyun * - position of slot
35*4882a593Smuzhiyun * - DDR1 vs. DDR2?
36*4882a593Smuzhiyun * - ???
37*4882a593Smuzhiyun *
38*4882a593Smuzhiyun * This needs to be determined on a board-by-board basis.
39*4882a593Smuzhiyun * 0110 3/4 cycle late
40*4882a593Smuzhiyun * 0111 7/8 cycle late
41*4882a593Smuzhiyun */
42*4882a593Smuzhiyun popts->clk_adjust = 7;
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun /*
45*4882a593Smuzhiyun * Factors to consider for CPO:
46*4882a593Smuzhiyun * - frequency
47*4882a593Smuzhiyun * - ddr1 vs. ddr2
48*4882a593Smuzhiyun */
49*4882a593Smuzhiyun popts->cpo_override = 9;
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun /*
52*4882a593Smuzhiyun * Factors to consider for write data delay:
53*4882a593Smuzhiyun * - number of DIMMs
54*4882a593Smuzhiyun *
55*4882a593Smuzhiyun * 1 = 1/4 clock delay
56*4882a593Smuzhiyun * 2 = 1/2 clock delay
57*4882a593Smuzhiyun * 3 = 3/4 clock delay
58*4882a593Smuzhiyun * 4 = 1 clock delay
59*4882a593Smuzhiyun * 5 = 5/4 clock delay
60*4882a593Smuzhiyun * 6 = 3/2 clock delay
61*4882a593Smuzhiyun */
62*4882a593Smuzhiyun popts->write_data_delay = 3;
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun /*
65*4882a593Smuzhiyun * Factors to consider for half-strength driver enable:
66*4882a593Smuzhiyun * - number of DIMMs installed
67*4882a593Smuzhiyun */
68*4882a593Smuzhiyun popts->half_strength_driver_enable = 0;
69*4882a593Smuzhiyun }
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