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/OK3568_Linux_fs/kernel/drivers/phy/marvell/
H A Dphy-mvebu-cp110-comphy.c1 // SPDX-License-Identifier: GPL-2.0
5 * Antoine Tenart <antoine.tenart@free-electrons.com>
8 #include <linux/arm-smccc.h>
19 /* Relative to priv->base */
30 #define MVEBU_COMPHY_SERDES_CFG1_RX_INIT BIT(4)
34 #define MVEBU_COMPHY_SERDES_CFG2_DFE_EN BIT(4)
38 #define MVEBU_COMPHY_SERDES_STATUS0_RX_INIT BIT(4)
62 #define MVEBU_COMPHY_GEN1_S2_TX_EMPH_EN BIT(4)
107 /* Relative to priv->regmap */
128 * A lane is described by the following bitfields:
[all …]
H A Dphy-armada38x-comphy.c1 // SPDX-License-Identifier: GPL-2.0
46 struct a38x_comphy_lane lane[MAX_A38X_COMPHY]; member
51 { 4, 5, 0 },
52 { 0, 4, 0 },
53 { 0, 0, 4 },
58 static void a38x_set_conf(struct a38x_comphy_lane *lane, bool enable) in a38x_set_conf() argument
60 struct a38x_comphy *priv = lane->priv; in a38x_set_conf()
63 if (priv->conf) { in a38x_set_conf()
64 conf = readl_relaxed(priv->conf); in a38x_set_conf()
66 conf |= BIT(lane->port); in a38x_set_conf()
[all …]
/OK3568_Linux_fs/kernel/drivers/phy/tegra/
H A Dxusb-tegra124.c1 // SPDX-License-Identifier: GPL-2.0-only
31 #define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_SHIFT(x) ((x) * 4)
39 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(x) (1 << (((x) * 4) + 3))
40 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_SHIFT(x) ((x) * 4)
41 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_MASK(x) (0x7 << ((x) * 4))
42 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(x, v) (((v) & 0x7) << ((x) * 4))
49 #define XUSB_PADCTL_ELPG_PROGRAM_SSPX_ELPG_VCORE_DOWN(x) (1 << (18 + (x) * 4))
51 (1 << (17 + (x) * 4))
52 #define XUSB_PADCTL_ELPG_PROGRAM_SSPX_ELPG_CLAMP_EN(x) (1 << (16 + (x) * 4))
62 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL (1 << 4)
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H A Dxusb-tegra210.c1 // SPDX-License-Identifier: GPL-2.0-only
25 ((x) ? (11 + ((x) - 1) * 6) : 0)
42 #define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_DISABLED(x) (0x0 << ((x) * 4))
43 #define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_HOST(x) (0x1 << ((x) * 4))
44 #define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_DEVICE(x) (0x2 << ((x) * 4))
45 #define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_OTG(x) (0x3 << ((x) * 4))
46 #define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_MASK(x) (0x3 << ((x) * 4))
49 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(x) (1 << (((x) * 5) + 4))
124 #define XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA0 (1 << 4)
158 #define XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD (1 << 4)
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/OK3568_Linux_fs/u-boot/arch/arm/mach-mvebu/serdes/axp/
H A Dhigh_speed_env_spec.h4 * SPDX-License-Identifier: GPL-2.0
53 MV_PEX_UNIT_CFG pex_mode[4];
56 * Bus speed - one bit per SERDES line:
69 {0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 0 */ \
70 {0, 1, -1 , -1, -1, -1, -1, -1, 2}, /* Lane 1 */ \
71 {0, 1, -1 , 2, -1, -1, -1, -1, 3}, /* Lane 2 */ \
72 {0, 1, -1 , -1, 2, -1, -1, 3, -1}, /* Lane 3 */ \
73 {0, 1, 2 , -1, -1, 3, -1, -1, 4}, /* Lane 4 */ \
74 {0, 1, 2 , -1, 3, -1, -1, 4, -1}, /* Lane 5 */ \
75 {0, 1, 2 , 4, -1, 3, -1, -1, -1}, /* Lane 6 */ \
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/OK3568_Linux_fs/u-boot/arch/powerpc/cpu/mpc85xx/
H A Dfsl_corenet_serdes.c2 * Copyright 2009-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
20 * The work-arounds for erratum SERDES8 and SERDES-A001 are linked together.
62 unsigned int lpd; /* RCW lane powerdown bit */
69 { 4, 156, FSL_SRDS_BANK_1 },
96 int serdes_get_lane_idx(int lane) in serdes_get_lane_idx() argument
98 return lanes[lane].idx; in serdes_get_lane_idx()
101 int serdes_get_bank_by_lane(int lane) in serdes_get_bank_by_lane() argument
103 return lanes[lane].bank; in serdes_get_bank_by_lane()
106 int serdes_lane_enabled(int lane) in serdes_lane_enabled() argument
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/OK3568_Linux_fs/u-boot/drivers/video/drm/
H A Danalogix_dp.c2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd
4 * SPDX-License-Identifier: GPL-2.0+
19 #include <asm/arch-rockchip/clock.h>
32 * struct rockchip_dp_chip_data - splite the grf setting of kind of chips
97 u8 buf[4]; in analogix_dp_link_start()
98 int lane, lane_count, retval; in analogix_dp_link_start() local
100 lane_count = dp->link_train.lane_count; in analogix_dp_link_start()
102 dp->link_train.lt_state = CLOCK_RECOVERY; in analogix_dp_link_start()
103 dp->link_train.eq_loop = 0; in analogix_dp_link_start()
105 for (lane = 0; lane < lane_count; lane++) in analogix_dp_link_start()
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H A Ddrm_dp_helper.c1 // SPDX-License-Identifier: GPL-2.0+
39 return link_status[r - DP_LANE0_1_STATUS]; in dp_link_status()
43 int lane) in dp_get_lane_status() argument
45 int i = DP_LANE0_1_STATUS + (lane >> 1); in dp_get_lane_status()
46 int s = (lane & 1) * 4; in dp_get_lane_status()
57 int lane; in drm_dp_channel_eq_ok() local
63 for (lane = 0; lane < lane_count; lane++) { in drm_dp_channel_eq_ok()
64 lane_status = dp_get_lane_status(link_status, lane); in drm_dp_channel_eq_ok()
74 int lane; in drm_dp_clock_recovery_ok() local
77 for (lane = 0; lane < lane_count; lane++) { in drm_dp_clock_recovery_ok()
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/OK3568_Linux_fs/kernel/drivers/phy/rockchip/
H A Dphy-rockchip-samsung-hdptx.c1 // SPDX-License-Identifier: GPL-2.0
44 #define ROPLL_ANA_CPP_CTRL_COARSE GENMASK(7, 4)
61 #define ANA_ROPLL_PMS_PDIV GENMASK(7, 4)
65 #define ROPLL_PMS_SDIV_RBR GENMASK(7, 4)
69 #define ROPLL_PMS_SDIV_HBR2 GENMASK(7, 4)
74 #define ROPLL_REF_CLK_SEL GENMASK(4, 3)
79 #define ROPLL_SDM_RSTN BIT(4)
87 #define ROPLL_SDC_RSTN BIT(4)
166 #define LS_SPEED_SEL BIT(4)
170 #define SB_RXRERM_EN BIT(4)
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H A Dphy-rockchip-naneng-edp.c1 // SPDX-License-Identifier: GPL-2.0
5 * Author: Wyon Bi <bivvy.bi@rock-chips.com>
24 #define EDP_PHY_TX_PD GENMASK(7, 4)
31 #define EDP_PHY_RATE GENMASK(5, 4)
36 #define EDP_PHY_TX1_EMP GENMASK(7, 4)
41 #define EDP_PHY_TX1_AMP GENMASK(6, 4)
46 #define EDP_PHY_TX2_AMP_SCALE GENMASK(5, 4)
60 #define EDP_PHY_AUX_DRV_PD_SEL BIT(4)
68 #define EDP_PHY_AUX_AMP GENMASK(6, 4)
90 } vp[4][4] = {
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/OK3568_Linux_fs/kernel/drivers/phy/xilinx/
H A Dphy-zynqmp.c1 // SPDX-License-Identifier: GPL-2.0
3 * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT.
5 * Copyright (C) 2018-2020 Xilinx Inc.
26 #include <dt-bindings/phy/phy.h>
29 * Lane Registers
32 /* TX De-emphasis parameters */
48 #define L0_TXPMD_TM_45_OVER_DP_POST2 BIT(4)
82 #define L0_Ln_REF_CLK_SEL(n) (0x2860 + (n) * 4)
94 #define L3_NSW_PIPE_SHIFT 4
104 #define PLL_REF_SEL(n) (0x10000 + (n) * 4)
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/OK3568_Linux_fs/u-boot/board/highbank/
H A Dahci.c4 * SPDX-License-Identifier: GPL-2.0+
82 static void cphy_spread_spectrum_override(u8 phy, u8 lane, u32 val) in cphy_spread_spectrum_override() argument
85 tmp = combo_phy_read(phy, CPHY_RX_INPUT_STS + lane * SPHY_LANE); in cphy_spread_spectrum_override()
87 combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp); in cphy_spread_spectrum_override()
90 combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp); in cphy_spread_spectrum_override()
94 combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp); in cphy_spread_spectrum_override()
97 static void cphy_tx_attenuation_override(u8 phy, u8 lane) in cphy_tx_attenuation_override() argument
103 shift = ((phy == 5) ? 4 : lane) * 4; in cphy_tx_attenuation_override()
110 tmp = combo_phy_read(phy, CPHY_TX_INPUT_STS + lane * SPHY_LANE); in cphy_tx_attenuation_override()
112 combo_phy_write(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp); in cphy_tx_attenuation_override()
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/OK3568_Linux_fs/u-boot/board/freescale/ls1043aqds/
H A Deth.c4 * SPDX-License-Identifier: GPL-2.0+
27 #define EMI1_SLOT3 4
43 /* Map SerDes1 4 lanes to default slot, will be initialized dynamically */
44 static u8 lane_to_slot[] = {1, 2, 3, 4};
86 brdcfg4 = QIXIS_READ(brdcfg[4]); in ls1043aqds_mux_mdio()
89 QIXIS_WRITE(brdcfg[4], brdcfg4); in ls1043aqds_mux_mdio()
96 struct ls1043aqds_mdio *priv = bus->priv; in ls1043aqds_mdio_read()
98 ls1043aqds_mux_mdio(priv->muxval); in ls1043aqds_mdio_read()
100 return priv->realbus->read(priv->realbus, addr, devad, regnum); in ls1043aqds_mdio_read()
106 struct ls1043aqds_mdio *priv = bus->priv; in ls1043aqds_mdio_write()
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/OK3568_Linux_fs/u-boot/drivers/phy/
H A Dphy-rockchip-samsung-hdptx.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <generic-phy.h>
44 #define ROPLL_ANA_CPP_CTRL_COARSE GENMASK(7, 4)
61 #define ANA_ROPLL_PMS_PDIV GENMASK(7, 4)
65 #define ROPLL_PMS_SDIV_RBR GENMASK(7, 4)
69 #define ROPLL_PMS_SDIV_HBR2 GENMASK(7, 4)
74 #define ROPLL_REF_CLK_SEL GENMASK(4, 3)
79 #define ROPLL_SDM_RSTN BIT(4)
87 #define ROPLL_SDC_RSTN BIT(4)
166 #define LS_SPEED_SEL BIT(4)
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H A Dphy-rockchip-naneng-edp.c1 // SPDX-License-Identifier: GPL-2.0
5 * Author: Wyon Bi <bivvy.bi@rock-chips.com>
10 #include <generic-phy.h>
19 #define EDP_PHY_TX_PD GENMASK(7, 4)
26 #define EDP_PHY_RATE GENMASK(5, 4)
31 #define EDP_PHY_TX1_EMP GENMASK(7, 4)
36 #define EDP_PHY_TX1_AMP GENMASK(6, 4)
41 #define EDP_PHY_TX2_AMP_SCALE GENMASK(5, 4)
55 #define EDP_PHY_AUX_DRV_PD_SEL BIT(4)
63 #define EDP_PHY_AUX_AMP GENMASK(6, 4)
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/OK3568_Linux_fs/u-boot/board/freescale/t4qds/
H A Deth.c4 * SPDX-License-Identifier: GPL-2.0+
37 #define EMI1_SLOT4 4
58 static u8 lane_to_slot_fsm2[] = {3, 3, 3, 3, 4, 4, 4, 4};
59 static u8 slot_qsgmii_phyaddr[5][4] = {
62 {4, 5, 6, 7},
102 brdcfg4 = QIXIS_READ(brdcfg[4]); in t4240qds_mux_mdio()
105 QIXIS_WRITE(brdcfg[4], brdcfg4); in t4240qds_mux_mdio()
112 struct t4240qds_mdio *priv = bus->priv; in t4240qds_mdio_read()
114 t4240qds_mux_mdio(priv->muxval); in t4240qds_mdio_read()
116 return priv->realbus->read(priv->realbus, addr, devad, regnum); in t4240qds_mdio_read()
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/OK3568_Linux_fs/kernel/drivers/phy/
H A Dphy-xgene.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * AppliedMicro X-Gene Multi-purpose PHY driver
10 * The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes.
19 * -----------------
20 * | Internal | |------|
21 * | Ref PLL CMU |----| | ------------- ---------
22 * ------------ ---- | MUX |-----|PHY PLL CMU|----| Serdes|
23 * | | | | ---------
24 * External Clock ------| | -------------
25 * |------|
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/OK3568_Linux_fs/u-boot/board/freescale/t1040qds/
H A Deth.c4 * SPDX-License-Identifier: GPL-2.0+
8 * The RGMII PHYs are provided by the two on-board PHY connected to
9 * dTSEC instances 4 and 5. The SGMII PHYs are provided by one on-board
10 * PHY or by the standard four-port SGMII riser card (VSC).
29 /* - In T1040 there are only 8 SERDES lanes, spread across 2 SERDES banks.
30 * Bank 1 -> Lanes A, B, C, D
31 * Bank 2 -> Lanes E, F, G, H
35 * means that the mapping must be determined dynamically, or that the lane
42 /* On the Vitesse VSC8234XHG SGMII riser card there are 4 SGMII PHYs
58 #define EMI1_SLOT4 4
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/OK3568_Linux_fs/u-boot/board/freescale/corenet_ds/
H A Deth_superhydra.c2 * Copyright 2009-2011 Freescale Semiconductor, Inc.
5 * SPDX-License-Identifier: GPL-2.0+
11 * board. The RGMII PHYs are the two on-board 1Gb ports. The SGMII PHYs are
12 * provided by the standard Freescale four-port SGMII riser card. The 10Gb
34 * 2) The phy-handle property of each active Ethernet MAC node is set to the
39 * values, so those values are hard-coded in the DTS. On the HYDRA board,
47 * and might need to be enabled, and also might need to have its mux-value
99 * that the mapping must be determined dynamically, or that the lane maps to
113 clrsetbits_8(&pixis->brdcfg1, mask, val); in super_hydra_mux_mdio()
125 struct super_hydra_mdio *priv = bus->priv; in super_hydra_mdio_read()
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H A Deth_p4080.c2 * Copyright 2009-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
60 * that the mapping must be determined dynamically, or that the lane maps to
64 1, 1, 2, 2, 3, 3, 3, 3, 6, 6, 4, 4, 4, 4, 5, 5, 5, 5
95 if (phydev->drv->config) in board_phy_config()
96 phydev->drv->config(phydev); in board_phy_config()
97 if (phydev->drv->uid == PHY_UID_TN2020) { in board_phy_config()
105 while (--timeout) { in board_phy_config()
109 "address %u\n", phydev->addr); in board_phy_config()
123 " to reset.\n", phydev->addr); in board_phy_config()
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/OK3568_Linux_fs/u-boot/drivers/phy/marvell/
H A Dcomphy_cp110.c2 * Copyright (C) 2015-2016 Marvell International Ltd.
4 * SPDX-License-Identifier: GPL-2.0+
20 #define SD_ADDR(base, lane) (base + 0x1000 * lane) argument
21 #define HPIPE_ADDR(base, lane) (SD_ADDR(base, lane) + 0x800) argument
22 #define COMPHY_ADDR(base, lane) (base + 0x28 * lane) argument
32 * For CP-110 we have 2 Selector registers "PHY Selectors",
40 {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII1, 0x1}, /* Lane 0 */
42 {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, /* Lane 1 */
44 {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x1}, /* Lane 2 */
47 {8, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_RXAUI1, 0x1}, /* Lane 3 */
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Darmada-8040-mcbin.dts4 * SPDX-License-Identifier: GPL-2.0
8 #include "armada-8040.dtsi" /* include SoC device tree */
11 model = "MACCHIATOBin-8040";
12 compatible = "marvell,armada8040-mcbin",
16 stdout-path = "serial0:115200n8";
33 simple-bus {
34 compatible = "simple-bus";
35 #address-cells = <1>;
36 #size-cells = <0>;
38 reg_usb3h0_vbus: usb3-vbus0 {
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/OK3568_Linux_fs/kernel/include/linux/phy/
H A Dphy-mipi-dphy.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 * struct phy_configure_opts_mipi_dphy - MIPI D-PHY configuration set
13 * MIPI D-PHY phy.
20 * Clock transitions and disable the Clock Lane HS-RX.
30 * send HS clock after the last associated Data Lane has
42 * the transmitter prior to any associated Data Lane beginning
53 * Lane LP-00 Line state immediately before the HS-0 Line
65 * should ignore any Clock Lane HS transitions, starting from
76 * Time, in picoseconds, for the Clock Lane receiver to enable
86 * Time, in picoseconds, that the transmitter drives the HS-0
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/phy/
H A Dphy-rockchip-usbdp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-rockchip-usbdp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Wang <frank.wang@rock-chips.com>
11 - Zhang Yubing <yubing.zhang@rock-chips.com>
16 - rockchip,rk3588-usbdp-phy
23 - description: phy ref clock.
24 - description: phy pcs immortal clock.
25 - description: phy peripheral clock.
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/i915/display/
H A Dintel_dp_link_training.c2 * Copyright © 2008-2015 Intel Corporation
34 link_status[3], link_status[4], link_status[5]); in intel_dp_dump_link_status()
58 int lane; in intel_dp_get_adjust_train() local
62 for (lane = 0; lane < intel_dp->lane_count; lane++) { in intel_dp_get_adjust_train()
63 v = max(v, drm_dp_get_adjust_request_voltage(link_status, lane)); in intel_dp_get_adjust_train()
64 p = max(p, drm_dp_get_adjust_request_pre_emphasis(link_status, lane)); in intel_dp_get_adjust_train()
67 preemph_max = intel_dp->preemph_max(intel_dp); in intel_dp_get_adjust_train()
68 drm_WARN_ON_ONCE(&i915->drm, in intel_dp_get_adjust_train()
77 voltage_max = intel_dp->voltage_max(intel_dp); in intel_dp_get_adjust_train()
78 drm_WARN_ON_ONCE(&i915->drm, in intel_dp_get_adjust_train()
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