1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/phy/phy-rockchip-usbdp.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Rockchip USBDP Combo PHY with Samsung IP block 8 9maintainers: 10 - Frank Wang <frank.wang@rock-chips.com> 11 - Zhang Yubing <yubing.zhang@rock-chips.com> 12 13properties: 14 compatible: 15 enum: 16 - rockchip,rk3588-usbdp-phy 17 18 reg: 19 maxItems: 1 20 21 clocks: 22 items: 23 - description: phy ref clock. 24 - description: phy pcs immortal clock. 25 - description: phy peripheral clock. 26 27 clock-names: 28 items: 29 - const: refclk 30 - const: immortal 31 - const: pclk 32 33 resets: 34 - description: phy init reset. 35 - description: phy cmn reset. 36 - description: phy lane reset. 37 - description: phy pcs apb reset. 38 - description: phy pma apb reset. 39 40 reset-names: 41 - const: init 42 - const: cmn 43 - const: lane 44 - const: pcs_apb 45 - const: pma_apb 46 47 rockchip,dp-lane-mux: 48 minItems: 2 49 maxItems: 4 50 description: 51 An array of physical Tyep-C lanes indexes. Position of an entry determines 52 the dp lane index, while the value of an entry indicater physical Type-C lane. 53 The support dp lanes number are 2 or 4. e.g. for 2 lanes dp lanes map, we could 54 have "rockchip,dp-lane-mux = <2, 3>;", assuming dp lane0 on Type-C phy lane2, 55 dp lane1 on Type-C phy lane3. For 4 lanes dp lanes map, we could have 56 "rockchip,dp-lane-mux = <0, 1, 2, 3>;", assuming dp lane0 on Type-C phy lane0, 57 dp lane1 on Type-C phy lane1, dp lane2 on Type-C phy lane2, dp lane3 on Type-C 58 phy lane3. If dp lane map by DisplayPort Alt mode, this property is not need. 59 60 rockchip,u2phy-grf: 61 $ref: /schemas/types.yaml#/definitions/phandle 62 description: 63 Phandle to the syscon managing the 'usb2 phy general register files'. 64 65 rockchip,usb-grf: 66 $ref: /schemas/types.yaml#/definitions/phandle 67 description: 68 Phandle to the syscon managing the 'usb general register files'. 69 70 rockchip,usbdpphy-grf: 71 $ref: /schemas/types.yaml#/definitions/phandle 72 description: 73 Phandle to the syscon managing the 'usbdp phy general register files'. 74 75 rockchip,vo-grf: 76 $ref: /schemas/types.yaml#/definitions/phandle 77 description: 78 Phandle to the syscon managing the 'video output general register files'. 79 When select the dp lane mapping will request its phandle. 80 81 dp-port: 82 type: object 83 additionalProperties: false 84 85 properties: 86 "#phy-cells": 87 const: 0 88 89 required: 90 - "#phy-cells" 91 92 u3-port: 93 type: object 94 additionalProperties: false 95 96 properties: 97 "#phy-cells": 98 const: 0 99 100 required: 101 - "#phy-cells" 102 103required: 104 - compatible 105 - reg 106 - clocks 107 - clock-names 108 - resets 109 - reset-names 110 - dp-port 111 - u3-port 112 113additionalProperties: false 114 115examples: 116 - | 117 #include <dt-bindings/clock/rk3588-cru.h> 118 119 usbdp_phy0: phy@fed80000 { 120 compatible = "rockchip,rk3588-usbdp-phy"; 121 reg = <0x0 0xfed80000 0x0 0x10000>; 122 rockchip,u2phy-grf = <&usb2phy0_grf>; 123 rockchip,usb-grf = <&usb_grf>; 124 rockchip,usbdpphy-grf = <&usbdpphy0_grf>; 125 rockchip,vo-grf = <&vo0_grf>; 126 clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, 127 <&cru CLK_USBDP_PHY0_IMMORTAL>, 128 <&cru PCLK_USBDPPHY0>; 129 clock-names = "refclk", "immortal", "pclk"; 130 resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>, 131 <&cru SRST_USBDP_COMBO_PHY0_CMN>, 132 <&cru SRST_USBDP_COMBO_PHY0_LANE>, 133 <&cru SRST_USBDP_COMBO_PHY0_PCS>, 134 <&cru SRST_P_USBDPPHY0>; 135 reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; 136 status = "disabled"; 137 138 usbdp_phy0_dp: dp-port { 139 #phy-cells = <0>; 140 status = "disabled"; 141 }; 142 143 usbdp_phy0_u3: u3-port { 144 #phy-cells = <0>; 145 status = "disabled"; 146 }; 147