1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Rockchip HDMI/DP Combo PHY with Samsung IP block
4 *
5 * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
6 */
7
8 #include <linux/bitfield.h>
9 #include <linux/clk.h>
10 #include <linux/kernel.h>
11 #include <linux/mfd/syscon.h>
12 #include <linux/module.h>
13 #include <linux/of_device.h>
14 #include <linux/phy/phy.h>
15 #include <linux/platform_device.h>
16 #include <linux/regmap.h>
17 #include <linux/reset.h>
18
19 #define HDPTXPHY_GRF_CON0 0x0000
20 #define RO_REF_CLK_SEL GENMASK(11, 10)
21 #define LC_REF_CLK_SEL GENMASK(9, 8)
22 #define PLL_EN BIT(7)
23 #define BIAS_EN BIT(6)
24 #define BGR_EN BIT(5)
25 #define HDPTX_MODE_SEL BIT(0)
26 #define HDPTXPHY_GRF_STATUS0 0x0080
27 #define PLL_LOCK_DONE BIT(3)
28 #define PHY_CLK_RDY BIT(2)
29 #define PHY_RDY BIT(1)
30 #define SB_RDY BIT(0)
31
32 /* cmn_reg0008 */
33 #define OVRD_LCPLL_EN BIT(7)
34 #define LCPLL_EN BIT(6)
35
36 /* cmn_reg003C */
37 #define ANA_LCPLL_RESERVED7 BIT(7)
38
39 /* cmn_reg003D */
40 #define OVRD_ROPLL_EN BIT(7)
41 #define ROPLL_EN BIT(6)
42
43 /* cmn_reg0046 */
44 #define ROPLL_ANA_CPP_CTRL_COARSE GENMASK(7, 4)
45 #define ROPLL_ANA_CPP_CTRL_FINE GENMASK(3, 0)
46
47 /* cmn_reg0047 */
48 #define ROPLL_ANA_LPF_C_SEL_COARSE GENMASK(5, 3)
49 #define ROPLL_ANA_LPF_C_SEL_FINE GENMASK(2, 0)
50
51 /* cmn_reg004E */
52 #define ANA_ROPLL_PI_EN BIT(5)
53
54 /* cmn_reg0051 */
55 #define ROPLL_PMS_MDIV GENMASK(7, 0)
56
57 /* cmn_reg0055 */
58 #define ROPLL_PMS_MDIV_AFC GENMASK(7, 0)
59
60 /* cmn_reg0059 */
61 #define ANA_ROPLL_PMS_PDIV GENMASK(7, 4)
62 #define ANA_ROPLL_PMS_REFDIV GENMASK(3, 0)
63
64 /* cmn_reg005A */
65 #define ROPLL_PMS_SDIV_RBR GENMASK(7, 4)
66 #define ROPLL_PMS_SDIV_HBR GENMASK(3, 0)
67
68 /* cmn_reg005B */
69 #define ROPLL_PMS_SDIV_HBR2 GENMASK(7, 4)
70 #define ROPLL_PMS_SDIV_HBR3 GENMASK(3, 0)
71
72 /* cmn_reg005D */
73 #define OVRD_ROPLL_REF_CLK_SEL BIT(5)
74 #define ROPLL_REF_CLK_SEL GENMASK(4, 3)
75
76 /* cmn_reg005E */
77 #define ANA_ROPLL_SDM_EN BIT(6)
78 #define OVRD_ROPLL_SDM_RSTN BIT(5)
79 #define ROPLL_SDM_RSTN BIT(4)
80 #define ROPLL_SDC_FRACTIONAL_EN_RBR BIT(3)
81 #define ROPLL_SDC_FRACTIONAL_EN_HBR BIT(2)
82 #define ROPLL_SDC_FRACTIONAL_EN_HBR2 BIT(1)
83 #define ROPLL_SDC_FRACTIONAL_EN_HBR3 BIT(0)
84
85 /* cmn_reg005F */
86 #define OVRD_ROPLL_SDC_RSTN BIT(5)
87 #define ROPLL_SDC_RSTN BIT(4)
88
89 /* cmn_reg0060 */
90 #define ROPLL_SDM_DENOMINATOR GENMASK(7, 0)
91
92 /* cmn_reg0064 */
93 #define ROPLL_SDM_NUMERATOR_SIGN_RBR BIT(3)
94 #define ROPLL_SDM_NUMERATOR_SIGN_HBR BIT(2)
95 #define ROPLL_SDM_NUMERATOR_SIGN_HBR2 BIT(1)
96 #define ROPLL_SDM_NUMERATOR_SIGN_HBR3 BIT(0)
97
98 /* cmn_reg0065 */
99 #define ROPLL_SDM_NUMERATOR GENMASK(7, 0)
100
101 /* cmn_reg0069 */
102 #define ROPLL_SDC_N_RBR GENMASK(2, 0)
103
104 /* cmn_reg006A */
105 #define ROPLL_SDC_N_HBR GENMASK(5, 3)
106 #define ROPLL_SDC_N_HBR2 GENMASK(2, 0)
107
108 /* cmn_reg006B */
109 #define ROPLL_SDC_N_HBR3 GENMASK(3, 1)
110
111 /* cmn_reg006C */
112 #define ROPLL_SDC_NUMERATOR GENMASK(5, 0)
113
114 /* cmn_reg0070 */
115 #define ROPLL_SDC_DENOMINATOR GENMASK(5, 0)
116
117 /* cmn_reg0074 */
118 #define OVRD_ROPLL_SDC_NDIV_RSTN BIT(3)
119 #define ROPLL_SDC_NDIV_RSTN BIT(2)
120 #define OVRD_ROPLL_SSC_EN BIT(1)
121 #define ROPLL_SSC_EN BIT(0)
122
123 /* cmn_reg0075 */
124 #define ANA_ROPLL_SSC_FM_DEVIATION GENMASK(5, 0)
125
126 /* cmn_reg0076 */
127 #define ANA_ROPLL_SSC_FM_FREQ GENMASK(6, 2)
128
129 /* cmn_reg0077 */
130 #define ANA_ROPLL_SSC_CLK_DIV_SEL GENMASK(6, 3)
131
132 /* cmn_reg0081 */
133 #define ANA_PLL_CD_TX_SER_RATE_SEL BIT(3)
134 #define ANA_PLL_CD_HSCLK_WEST_EN BIT(1)
135 #define ANA_PLL_CD_HSCLK_EAST_EN BIT(0)
136
137 /* cmn_reg0082 */
138 #define ANA_PLL_CD_VREG_GAIN_CTRL GENMASK(3, 0)
139
140 /* cmn_reg0083 */
141 #define ANA_PLL_CD_VREG_ICTRL GENMASK(6, 5)
142
143 /* cmn_reg0084 */
144 #define PLL_LCRO_CLK_SEL BIT(5)
145
146 /* cmn_reg0085 */
147 #define ANA_PLL_SYNC_LOSS_DET_MODE GENMASK(1, 0)
148
149 /* cmn_reg0087 */
150 #define ANA_PLL_TX_HS_CLK_EN BIT(2)
151
152 /* cmn_reg0095 */
153 #define DP_TX_LINK_BW GENMASK(1, 0)
154
155 /* cmn_reg0097 */
156 #define DIG_CLK_SEL BIT(1)
157
158 /* cmn_reg0099 */
159 #define SSC_EN GENMASK(7, 6)
160 #define CMN_ROPLL_ALONE_MODE BIT(2)
161
162 /* cmn_reg009A */
163 #define HS_SPEED_SEL BIT(0)
164
165 /* cmn_reg009B */
166 #define LS_SPEED_SEL BIT(4)
167
168 /* sb_reg0102 */
169 #define OVRD_SB_RXTERM_EN BIT(5)
170 #define SB_RXRERM_EN BIT(4)
171 #define ANA_SB_RXTERM_OFFSP GENMASK(3, 0)
172
173 /* sb_reg0103 */
174 #define ANA_SB_RXTERM_OFFSN GENMASK(6, 3)
175 #define OVRD_SB_RX_RESCAL_DONE BIT(1)
176 #define SB_RX_RESCAL_DONE BIT(0)
177
178 /* sb_reg0104 */
179 #define OVRD_SB_EN BIT(5)
180 #define SB_EN BIT(4)
181 #define OVRD_SB_AUX_EN BIT(1)
182 #define SB_AUX_EN BIT(0)
183
184 /* sb_reg0105 */
185 #define ANA_SB_TX_HLVL_PROG GENMASK(2, 0)
186
187 /* sb_reg0106 */
188 #define ANA_SB_TX_LLVL_PROG GENMASK(6, 4)
189
190 /* sb_reg010D */
191 #define ANA_SB_DMRX_LPBK_DATA BIT(4)
192
193 /* sb_reg010F */
194 #define OVRD_SB_VREG_EN BIT(7)
195 #define SB_VREG_EN BIT(6)
196 #define ANA_SB_VREG_GAIN_CTRL GENMASK(3, 0)
197
198 /* sb_reg0110 */
199 #define ANA_SB_VREG_OUT_SEL BIT(1)
200 #define ANA_SB_VREG_REF_SEL BIT(0)
201
202 /* sb_reg0113 */
203 #define SB_RX_RCAL_OPT_CODE GENMASK(5, 4)
204 #define SB_RX_RTERM_CTRL GENMASK(3, 0)
205
206 /* sb_reg0114 */
207 #define SB_TG_SB_EN_DELAY_TIME GENMASK(5, 3)
208 #define SB_TG_RXTERN_EN_DELAY_TIME GENMASK(2, 0)
209
210 /* sb_reg0115 */
211 #define SB_READY_DELAY_TIME GENMASK(5, 3)
212 #define SB_TG_OSC_EN_DELAY_TIME GENMASK(2, 0)
213
214 /* sb_reg0116 */
215 #define SB_TG_OSC_EN_TO_AFC_RSTN_DELAT_TIME GENMASK(6, 4)
216
217 /* sb_reg0117 */
218 #define SB_TG_PLL_CD_VREG_FAST_PULSE_TIME GENMASK(3, 0)
219
220 /* sb_reg0118 */
221 #define SB_TG_EARC_DMRX_RECVRD_CLK_CNT GENMASK(7, 0)
222
223 /* sb_reg011A */
224 #define SB_TG_CNT_RUN_NO_7_0 GENMASK(7, 0)
225
226 /* sb_reg011B */
227 #define SB_EARC_SIG_DET_BYPASS BIT(4)
228 #define SB_AFC_TOL GENMASK(3, 0)
229
230 /* sb_reg011C */
231 #define SB_AFC_STB_NUM GENMASK(3, 0)
232
233 /* sb_reg011D */
234 #define SB_TG_OSC_CNT_MIN GENMASK(7, 0)
235
236 /* sb_reg011E */
237 #define SB_TG_OSC_CNT_MAX GENMASK(7, 0)
238
239 /* sb_reg011F */
240 #define SB_PWM_AFC_CTRL GENMASK(7, 2)
241 #define SB_RCAL_RSTN BIT(1)
242
243 /* sb_reg0120 */
244 #define SB_AUX_EN_IN BIT(7)
245
246 /* sb_reg0123 */
247 #define OVRD_SB_READY BIT(5)
248 #define SB_READY BIT(4)
249
250 /* lntop_reg0200 */
251 #define PROTOCOL_SEL BIT(2)
252
253 /* lntop_reg0206 */
254 #define DATA_BUS_WIDTH GENMASK(2, 1)
255 #define BUS_WIDTH_SEL BIT(0)
256
257 /* lntop_reg0207 */
258 #define LANE_EN GENMASK(3, 0)
259
260 /* lane_reg0301 */
261 #define OVRD_LN_TX_DRV_EI_EN BIT(7)
262 #define LN_TX_DRV_EI_EN BIT(6)
263
264 /* lane_reg0303 */
265 #define OVRD_LN_TX_DRV_LVL_CTRL BIT(5)
266 #define LN_TX_DRV_LVL_CTRL GENMASK(4, 0)
267
268 /* lane_reg0304 */
269 #define OVRD_LN_TX_DRV_POST_LVL_CTRL BIT(4)
270 #define LN_TX_DRV_POST_LVL_CTRL GENMASK(3, 0)
271
272 /* lane_reg0305 */
273 #define OVRD_LN_TX_DRV_PRE_LVL_CTRL BIT(6)
274 #define LN_TX_DRV_PRE_LVL_CTRL GENMASK(5, 2)
275
276 /* lane_reg0306 */
277 #define LN_ANA_TX_DRV_IDRV_IDN_CTRL GENMASK(7, 5)
278 #define LN_ANA_TX_DRV_IDRV_IUP_CTRL GENMASK(4, 2)
279 #define LN_ANA_TX_DRV_ACCDRV_EN BIT(0)
280
281 /* lane_reg0307 */
282 #define LN_ANA_TX_DRV_ACCDRV_POL_SEL BIT(6)
283 #define LN_ANA_TX_DRV_ACCDRV_CTRL GENMASK(5, 3)
284
285 /* lane_reg030A */
286 #define LN_ANA_TX_JEQ_EN BIT(4)
287 #define LN_TX_JEQ_EVEN_CTRL_RBR GENMASK(3, 0)
288
289 /* lane_reg030B */
290 #define LN_TX_JEQ_EVEN_CTRL_HBR GENMASK(7, 4)
291 #define LN_TX_JEQ_EVEN_CTRL_HBR2 GENMASK(3, 0)
292
293 /* lane_reg030C */
294 #define LN_TX_JEQ_EVEN_CTRL_HBR3 GENMASK(7, 4)
295 #define LN_TX_JEQ_ODD_CTRL_RBR GENMASK(3, 0)
296
297 /* lane_reg030D */
298 #define LN_TX_JEQ_ODD_CTRL_HBR GENMASK(7, 4)
299 #define LN_TX_JEQ_ODD_CTRL_HBR2 GENMASK(3, 0)
300
301 /* lane_reg030E */
302 #define LN_TX_JEQ_ODD_CTRL_HBR3 GENMASK(7, 4)
303
304 /* lane_reg0310 */
305 #define LN_ANA_TX_SYNC_LOSS_DET_MODE GENMASK(1, 0)
306
307 /* lane_reg0311 */
308 #define LN_TX_SER_40BIT_EN_RBR BIT(3)
309 #define LN_TX_SER_40BIT_EN_HBR BIT(2)
310 #define LN_TX_SER_40BIT_EN_HBR2 BIT(1)
311 #define LN_TX_SER_40BIT_EN_HBR3 BIT(0)
312
313 /* lane_reg0316 */
314 #define LN_ANA_TX_SER_VREG_GAIN_CTRL GENMASK(3, 0)
315
316 /* lane_reg031B */
317 #define LN_ANA_TX_RESERVED GENMASK(7, 0)
318
319 /* lane_reg031E */
320 #define LN_POLARITY_INV BIT(2)
321
322 #define LANE_REG(lane, offset) (0x400 * (lane) + (offset))
323
324 struct rockchip_hdptx_phy {
325 struct device *dev;
326 struct clk_bulk_data *clks;
327 int nr_clks;
328 struct reset_control *apb_reset;
329 struct reset_control *cmn_reset;
330 struct reset_control *init_reset;
331 struct reset_control *lane_reset;
332 struct regmap *regmap;
333 struct regmap *grf;
334 u32 lane_polarity_invert[4];
335 };
336
337 enum {
338 DP_BW_RBR,
339 DP_BW_HBR,
340 DP_BW_HBR2,
341 DP_BW_HBR3,
342 };
343
344 struct tx_drv_ctrl {
345 u8 tx_drv_lvl_ctrl;
346 u8 tx_drv_post_lvl_ctrl;
347 u8 ana_tx_drv_idrv_idn_ctrl;
348 u8 ana_tx_drv_idrv_iup_ctrl;
349 u8 ana_tx_drv_accdrv_en;
350 u8 ana_tx_drv_accdrv_ctrl;
351 } __packed;
352
353 static struct tx_drv_ctrl tx_drv_ctrl_rbr[4][4] = {
354 /* voltage swing 0, pre-emphasis 0->3 */
355 {
356 { 0x1, 0x0, 0x4, 0x6, 0x0, 0x4 },
357 { 0x4, 0x3, 0x4, 0x6, 0x0, 0x4 },
358 { 0x7, 0x6, 0x4, 0x6, 0x0, 0x4 },
359 { 0xd, 0xb, 0x7, 0x7, 0x1, 0x7 },
360 },
361
362 /* voltage swing 1, pre-emphasis 0->2 */
363 {
364 { 0x4, 0x0, 0x4, 0x6, 0x0, 0x4 },
365 { 0xa, 0x5, 0x4, 0x6, 0x0, 0x4 },
366 { 0xd, 0x8, 0x7, 0x7, 0x1, 0x7 },
367 },
368
369 /* voltage swing 2, pre-emphasis 0->1 */
370 {
371 { 0x8, 0x0, 0x4, 0x6, 0x0, 0x4 },
372 { 0xd, 0x5, 0x7, 0x7, 0x1, 0x7 },
373 },
374
375 /* voltage swing 3, pre-emphasis 0 */
376 {
377 { 0xd, 0x0, 0x7, 0x7, 0x1, 0x4 },
378 }
379 };
380
381 static struct tx_drv_ctrl tx_drv_ctrl_hbr[4][4] = {
382 /* voltage swing 0, pre-emphasis 0->3 */
383 {
384 { 0x2, 0x1, 0x4, 0x6, 0x0, 0x4 },
385 { 0x5, 0x4, 0x4, 0x6, 0x0, 0x4 },
386 { 0x9, 0x8, 0x4, 0x6, 0x0, 0x4 },
387 { 0xd, 0xb, 0x7, 0x7, 0x1, 0x7 },
388 },
389
390 /* voltage swing 1, pre-emphasis 0->2 */
391 {
392 { 0x6, 0x1, 0x4, 0x6, 0x0, 0x4 },
393 { 0xb, 0x6, 0x4, 0x6, 0x0, 0x4 },
394 { 0xd, 0x8, 0x7, 0x7, 0x1, 0x7 },
395 },
396
397 /* voltage swing 2, pre-emphasis 0->1 */
398 {
399 { 0x9, 0x1, 0x4, 0x6, 0x0, 0x4 },
400 { 0xd, 0x6, 0x7, 0x7, 0x1, 0x7 },
401 },
402
403 /* voltage swing 3, pre-emphasis 0 */
404 {
405 { 0xd, 0x1, 0x7, 0x7, 0x1, 0x4 },
406 }
407 };
408
409 static struct tx_drv_ctrl tx_drv_ctrl_hbr2[4][4] = {
410 /* voltage swing 0, pre-emphasis 0->3 */
411 {
412 { 0x2, 0x1, 0x4, 0x6, 0x0, 0x4 },
413 { 0x5, 0x4, 0x4, 0x6, 0x0, 0x4 },
414 { 0x9, 0x8, 0x4, 0x6, 0x1, 0x4 },
415 { 0xd, 0xb, 0x7, 0x7, 0x1, 0x7 },
416 },
417
418 /* voltage swing 1, pre-emphasis 0->2 */
419 {
420 { 0x6, 0x1, 0x4, 0x6, 0x0, 0x4 },
421 { 0xc, 0x7, 0x4, 0x6, 0x0, 0x4 },
422 { 0xd, 0x8, 0x7, 0x7, 0x1, 0x7 },
423 },
424
425 /* voltage swing 2, pre-emphasis 0->1 */
426 {
427 { 0x9, 0x1, 0x4, 0x6, 0x0, 0x4 },
428 { 0xd, 0x6, 0x7, 0x7, 0x1, 0x7 },
429 },
430
431 /* voltage swing 3, pre-emphasis 0 */
432 {
433 { 0xd, 0x0, 0x7, 0x7, 0x1, 0x4 },
434 }
435 };
436
rockchip_hdptx_phy_parse_training_table(struct device * dev)437 static int rockchip_hdptx_phy_parse_training_table(struct device *dev)
438 {
439 size_t size = sizeof(struct tx_drv_ctrl) * 10;
440 u8 *buf, *training_table;
441 int i, j;
442
443 buf = kzalloc(size, GFP_KERNEL);
444 if (!buf)
445 return -ENOMEM;
446
447 if (device_property_read_u8_array(dev, "training-table", buf, size)) {
448 kfree(buf);
449 return 0;
450 }
451
452 training_table = buf;
453
454 for (i = 0; i < 4; i++) {
455 for (j = 0; j < 4; j++) {
456 struct tx_drv_ctrl *ctrl;
457
458 if (i + j > 3)
459 continue;
460
461 ctrl = (struct tx_drv_ctrl *)training_table;
462 tx_drv_ctrl_rbr[i][j] = *ctrl;
463 tx_drv_ctrl_hbr[i][j] = *ctrl;
464 tx_drv_ctrl_hbr2[i][j] = *ctrl;
465 training_table += sizeof(*ctrl);
466 }
467 }
468
469 kfree(buf);
470
471 return 0;
472 }
473
rockchip_grf_write(struct regmap * grf,unsigned int reg,unsigned int mask,unsigned int val)474 static int rockchip_grf_write(struct regmap *grf, unsigned int reg,
475 unsigned int mask, unsigned int val)
476 {
477 return regmap_write(grf, reg, (mask << 16) | (val & mask));
478 }
479
rockchip_hdptx_phy_set_mode(struct phy * phy,enum phy_mode mode,int submode)480 static int rockchip_hdptx_phy_set_mode(struct phy *phy, enum phy_mode mode,
481 int submode)
482 {
483 return 0;
484 }
485
rockchip_hdptx_phy_verify_config(struct rockchip_hdptx_phy * hdptx,struct phy_configure_opts_dp * dp)486 static int rockchip_hdptx_phy_verify_config(struct rockchip_hdptx_phy *hdptx,
487 struct phy_configure_opts_dp *dp)
488 {
489 int i;
490
491 if (dp->set_rate) {
492 switch (dp->link_rate) {
493 case 1620:
494 case 2700:
495 case 5400:
496 break;
497 default:
498 return -EINVAL;
499 }
500 }
501
502 switch (dp->lanes) {
503 case 0:
504 case 1:
505 case 2:
506 case 4:
507 break;
508 default:
509 return -EINVAL;
510 }
511
512 if (dp->set_voltages) {
513 for (i = 0; i < dp->lanes; i++) {
514 if (dp->voltage[i] > 3 || dp->pre[i] > 3)
515 return -EINVAL;
516
517 if (dp->voltage[i] + dp->pre[i] > 3)
518 return -EINVAL;
519 }
520 }
521
522 return 0;
523 }
524
rockchip_hdptx_phy_set_voltage(struct rockchip_hdptx_phy * hdptx,struct phy_configure_opts_dp * dp,u8 lane)525 static void rockchip_hdptx_phy_set_voltage(struct rockchip_hdptx_phy *hdptx,
526 struct phy_configure_opts_dp *dp,
527 u8 lane)
528 {
529 const struct tx_drv_ctrl *ctrl;
530
531 switch (dp->link_rate) {
532 case 1620:
533 ctrl = &tx_drv_ctrl_rbr[dp->voltage[lane]][dp->pre[lane]];
534 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c44),
535 LN_TX_SER_40BIT_EN_RBR,
536 FIELD_PREP(LN_TX_SER_40BIT_EN_RBR, 0x1));
537 break;
538 case 2700:
539 ctrl = &tx_drv_ctrl_hbr[dp->voltage[lane]][dp->pre[lane]];
540 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c44),
541 LN_TX_SER_40BIT_EN_HBR,
542 FIELD_PREP(LN_TX_SER_40BIT_EN_HBR, 0x1));
543 break;
544 case 5400:
545 default:
546 ctrl = &tx_drv_ctrl_hbr2[dp->voltage[lane]][dp->pre[lane]];
547 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c44),
548 LN_TX_SER_40BIT_EN_HBR2,
549 FIELD_PREP(LN_TX_SER_40BIT_EN_HBR2, 0x1));
550 break;
551 }
552
553 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c0c),
554 OVRD_LN_TX_DRV_LVL_CTRL | LN_TX_DRV_LVL_CTRL,
555 FIELD_PREP(OVRD_LN_TX_DRV_LVL_CTRL, 0x1) |
556 FIELD_PREP(LN_TX_DRV_LVL_CTRL,
557 ctrl->tx_drv_lvl_ctrl));
558
559 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c10),
560 OVRD_LN_TX_DRV_POST_LVL_CTRL |
561 LN_TX_DRV_POST_LVL_CTRL,
562 FIELD_PREP(OVRD_LN_TX_DRV_POST_LVL_CTRL, 0x1) |
563 FIELD_PREP(LN_TX_DRV_POST_LVL_CTRL,
564 ctrl->tx_drv_post_lvl_ctrl));
565
566 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c18),
567 LN_ANA_TX_DRV_IDRV_IDN_CTRL |
568 LN_ANA_TX_DRV_IDRV_IUP_CTRL |
569 LN_ANA_TX_DRV_ACCDRV_EN,
570 FIELD_PREP(LN_ANA_TX_DRV_IDRV_IDN_CTRL,
571 ctrl->ana_tx_drv_idrv_idn_ctrl) |
572 FIELD_PREP(LN_ANA_TX_DRV_IDRV_IUP_CTRL,
573 ctrl->ana_tx_drv_idrv_iup_ctrl) |
574 FIELD_PREP(LN_ANA_TX_DRV_ACCDRV_EN,
575 ctrl->ana_tx_drv_accdrv_en));
576
577 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c1c),
578 LN_ANA_TX_DRV_ACCDRV_POL_SEL |
579 LN_ANA_TX_DRV_ACCDRV_CTRL,
580 FIELD_PREP(LN_ANA_TX_DRV_ACCDRV_POL_SEL, 0x1) |
581 FIELD_PREP(LN_ANA_TX_DRV_ACCDRV_CTRL,
582 ctrl->ana_tx_drv_accdrv_ctrl));
583 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c6c),
584 LN_ANA_TX_RESERVED,
585 FIELD_PREP(LN_ANA_TX_RESERVED, 0x1));
586 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c58),
587 LN_ANA_TX_SER_VREG_GAIN_CTRL,
588 FIELD_PREP(LN_ANA_TX_SER_VREG_GAIN_CTRL, 0x2));
589 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c40),
590 LN_ANA_TX_SYNC_LOSS_DET_MODE,
591 FIELD_PREP(LN_ANA_TX_SYNC_LOSS_DET_MODE, 0x3));
592 }
593
rockchip_hdptx_phy_set_voltages(struct rockchip_hdptx_phy * hdptx,struct phy_configure_opts_dp * dp)594 static int rockchip_hdptx_phy_set_voltages(struct rockchip_hdptx_phy *hdptx,
595 struct phy_configure_opts_dp *dp)
596 {
597 u8 lane;
598 u32 status;
599 int ret;
600
601 for (lane = 0; lane < dp->lanes; lane++)
602 rockchip_hdptx_phy_set_voltage(hdptx, dp, lane);
603
604 reset_control_deassert(hdptx->lane_reset);
605
606 ret = regmap_read_poll_timeout(hdptx->grf, HDPTXPHY_GRF_STATUS0,
607 status, FIELD_GET(PHY_RDY, status),
608 50, 5000);
609 if (ret) {
610 dev_err(hdptx->dev, "timeout waiting for phy_rdy\n");
611 return ret;
612 }
613
614 return 0;
615 }
616
rockchip_hdptx_phy_lane_disable(struct rockchip_hdptx_phy * hdptx)617 static void rockchip_hdptx_phy_lane_disable(struct rockchip_hdptx_phy *hdptx)
618 {
619 reset_control_assert(hdptx->lane_reset);
620
621 regmap_update_bits(hdptx->regmap, 0x081c, LANE_EN,
622 FIELD_PREP(LANE_EN, 0x0));
623
624 rockchip_grf_write(hdptx->grf, HDPTXPHY_GRF_CON0, PLL_EN,
625 FIELD_PREP(PLL_EN, 0x0));
626
627 regmap_update_bits(hdptx->regmap, 0x0020, OVRD_LCPLL_EN | LCPLL_EN,
628 FIELD_PREP(OVRD_LCPLL_EN, 0x1) |
629 FIELD_PREP(LCPLL_EN, 0x0));
630 regmap_update_bits(hdptx->regmap, 0x00f4, OVRD_ROPLL_EN | ROPLL_EN,
631 FIELD_PREP(OVRD_ROPLL_EN, 0x1) |
632 FIELD_PREP(ROPLL_EN, 0x0));
633 }
634
rockchip_hdptx_phy_set_lanes(struct rockchip_hdptx_phy * hdptx,struct phy_configure_opts_dp * dp)635 static int rockchip_hdptx_phy_set_lanes(struct rockchip_hdptx_phy *hdptx,
636 struct phy_configure_opts_dp *dp)
637 {
638 if (!dp->lanes) {
639 rockchip_hdptx_phy_lane_disable(hdptx);
640 return 0;
641 }
642
643 regmap_update_bits(hdptx->regmap, 0x081c, LANE_EN,
644 FIELD_PREP(LANE_EN, GENMASK(dp->lanes - 1, 0)));
645
646 return 0;
647 }
648
rockchip_hdptx_phy_set_rate(struct rockchip_hdptx_phy * hdptx,struct phy_configure_opts_dp * dp)649 static int rockchip_hdptx_phy_set_rate(struct rockchip_hdptx_phy *hdptx,
650 struct phy_configure_opts_dp *dp)
651 {
652 u32 bw, status;
653 int ret;
654
655 rockchip_grf_write(hdptx->grf, HDPTXPHY_GRF_CON0, PLL_EN,
656 FIELD_PREP(PLL_EN, 0x0));
657
658 switch (dp->link_rate) {
659 case 1620:
660 bw = DP_BW_RBR;
661 break;
662 case 2700:
663 bw = DP_BW_HBR;
664 break;
665 case 5400:
666 bw = DP_BW_HBR2;
667 break;
668 default:
669 return -EINVAL;
670 }
671
672 regmap_update_bits(hdptx->regmap, 0x0254, DP_TX_LINK_BW,
673 FIELD_PREP(DP_TX_LINK_BW, bw));
674
675 if (dp->ssc) {
676 regmap_update_bits(hdptx->regmap, 0x01d0,
677 OVRD_ROPLL_SSC_EN | ROPLL_SSC_EN,
678 FIELD_PREP(OVRD_ROPLL_SSC_EN, 0x1) |
679 FIELD_PREP(ROPLL_SSC_EN, 0x1));
680 regmap_write(hdptx->regmap, 0x01d4,
681 FIELD_PREP(ANA_ROPLL_SSC_FM_DEVIATION, 0xc));
682 regmap_update_bits(hdptx->regmap, 0x01d8,
683 ANA_ROPLL_SSC_FM_FREQ,
684 FIELD_PREP(ANA_ROPLL_SSC_FM_FREQ, 0x1f));
685 regmap_update_bits(hdptx->regmap, 0x0264, SSC_EN,
686 FIELD_PREP(SSC_EN, 0x2));
687 } else {
688 regmap_update_bits(hdptx->regmap, 0x01d0,
689 OVRD_ROPLL_SSC_EN | ROPLL_SSC_EN,
690 FIELD_PREP(OVRD_ROPLL_SSC_EN, 0x1) |
691 FIELD_PREP(ROPLL_SSC_EN, 0x0));
692 regmap_write(hdptx->regmap, 0x01d4,
693 FIELD_PREP(ANA_ROPLL_SSC_FM_DEVIATION, 0x20));
694 regmap_update_bits(hdptx->regmap, 0x01d8,
695 ANA_ROPLL_SSC_FM_FREQ,
696 FIELD_PREP(ANA_ROPLL_SSC_FM_FREQ, 0xc));
697 regmap_update_bits(hdptx->regmap, 0x0264, SSC_EN,
698 FIELD_PREP(SSC_EN, 0x0));
699 }
700
701 regmap_update_bits(hdptx->regmap, 0x0020, OVRD_LCPLL_EN | LCPLL_EN,
702 FIELD_PREP(OVRD_LCPLL_EN, 0x1) |
703 FIELD_PREP(LCPLL_EN, 0x0));
704 regmap_update_bits(hdptx->regmap, 0x00f4, OVRD_ROPLL_EN | ROPLL_EN,
705 FIELD_PREP(OVRD_ROPLL_EN, 0x1) |
706 FIELD_PREP(ROPLL_EN, 0x1));
707
708 rockchip_grf_write(hdptx->grf, HDPTXPHY_GRF_CON0, PLL_EN,
709 FIELD_PREP(PLL_EN, 0x1));
710
711 ret = regmap_read_poll_timeout(hdptx->grf, HDPTXPHY_GRF_STATUS0,
712 status, FIELD_GET(PLL_LOCK_DONE, status),
713 50, 1000);
714 if (ret) {
715 dev_err(hdptx->dev, "timeout waiting for pll_lock_done\n");
716 return ret;
717 }
718
719 return 0;
720 }
721
rockchip_hdptx_phy_configure(struct phy * phy,union phy_configure_opts * opts)722 static int rockchip_hdptx_phy_configure(struct phy *phy,
723 union phy_configure_opts *opts)
724 {
725 struct rockchip_hdptx_phy *hdptx = phy_get_drvdata(phy);
726 enum phy_mode mode = phy_get_mode(phy);
727 int ret;
728
729 if (mode != PHY_MODE_DP)
730 return -EINVAL;
731
732 ret = rockchip_hdptx_phy_verify_config(hdptx, &opts->dp);
733 if (ret) {
734 dev_err(hdptx->dev, "invalid params for phy configure\n");
735 return ret;
736 }
737
738 if (opts->dp.set_rate) {
739 ret = rockchip_hdptx_phy_set_rate(hdptx, &opts->dp);
740 if (ret) {
741 dev_err(hdptx->dev, "failed to set rate: %d\n", ret);
742 return ret;
743 }
744 }
745
746 if (opts->dp.set_lanes) {
747 ret = rockchip_hdptx_phy_set_lanes(hdptx, &opts->dp);
748 if (ret) {
749 dev_err(hdptx->dev, "failed to set lanes: %d\n", ret);
750 return ret;
751 }
752 }
753
754 if (opts->dp.set_voltages) {
755 ret = rockchip_hdptx_phy_set_voltages(hdptx, &opts->dp);
756 if (ret) {
757 dev_err(hdptx->dev, "failed to set voltages: %d\n",
758 ret);
759 return ret;
760 }
761 }
762
763 return 0;
764 }
765
rockchip_hdptx_phy_dp_pll_init(struct rockchip_hdptx_phy * hdptx)766 static void rockchip_hdptx_phy_dp_pll_init(struct rockchip_hdptx_phy *hdptx)
767 {
768 regmap_write(hdptx->regmap, 0x0144, FIELD_PREP(ROPLL_PMS_MDIV, 0x87));
769 regmap_write(hdptx->regmap, 0x0148, FIELD_PREP(ROPLL_PMS_MDIV, 0x71));
770 regmap_write(hdptx->regmap, 0x014c, FIELD_PREP(ROPLL_PMS_MDIV, 0x71));
771
772 regmap_write(hdptx->regmap, 0x0154,
773 FIELD_PREP(ROPLL_PMS_MDIV_AFC, 0x87));
774 regmap_write(hdptx->regmap, 0x0158,
775 FIELD_PREP(ROPLL_PMS_MDIV_AFC, 0x71));
776 regmap_write(hdptx->regmap, 0x015c,
777 FIELD_PREP(ROPLL_PMS_MDIV_AFC, 0x71));
778
779 regmap_write(hdptx->regmap, 0x0164,
780 FIELD_PREP(ANA_ROPLL_PMS_PDIV, 0x1) |
781 FIELD_PREP(ANA_ROPLL_PMS_REFDIV, 0x1));
782
783 regmap_write(hdptx->regmap, 0x0168,
784 FIELD_PREP(ROPLL_PMS_SDIV_RBR, 0x3) |
785 FIELD_PREP(ROPLL_PMS_SDIV_HBR, 0x1));
786 regmap_update_bits(hdptx->regmap, 0x016c, ROPLL_PMS_SDIV_HBR2,
787 FIELD_PREP(ROPLL_PMS_SDIV_HBR2, 0x0));
788
789 regmap_update_bits(hdptx->regmap, 0x0178, ANA_ROPLL_SDM_EN,
790 FIELD_PREP(ANA_ROPLL_SDM_EN, 0x1));
791 regmap_update_bits(hdptx->regmap, 0x0178,
792 OVRD_ROPLL_SDM_RSTN | ROPLL_SDM_RSTN,
793 FIELD_PREP(OVRD_ROPLL_SDM_RSTN, 0x1) |
794 FIELD_PREP(ROPLL_SDM_RSTN, 0x1));
795 regmap_update_bits(hdptx->regmap, 0x0178, ROPLL_SDC_FRACTIONAL_EN_RBR,
796 FIELD_PREP(ROPLL_SDC_FRACTIONAL_EN_RBR, 0x1));
797 regmap_update_bits(hdptx->regmap, 0x0178, ROPLL_SDC_FRACTIONAL_EN_HBR,
798 FIELD_PREP(ROPLL_SDC_FRACTIONAL_EN_HBR, 0x1));
799 regmap_update_bits(hdptx->regmap, 0x0178, ROPLL_SDC_FRACTIONAL_EN_HBR2,
800 FIELD_PREP(ROPLL_SDC_FRACTIONAL_EN_HBR2, 0x1));
801 regmap_update_bits(hdptx->regmap, 0x017c,
802 OVRD_ROPLL_SDC_RSTN | ROPLL_SDC_RSTN,
803 FIELD_PREP(OVRD_ROPLL_SDC_RSTN, 0x1) |
804 FIELD_PREP(ROPLL_SDC_RSTN, 0x1));
805
806 regmap_write(hdptx->regmap, 0x0180,
807 FIELD_PREP(ROPLL_SDM_DENOMINATOR, 0x21));
808 regmap_write(hdptx->regmap, 0x0184,
809 FIELD_PREP(ROPLL_SDM_DENOMINATOR, 0x27));
810 regmap_write(hdptx->regmap, 0x0188,
811 FIELD_PREP(ROPLL_SDM_DENOMINATOR, 0x27));
812
813 regmap_update_bits(hdptx->regmap, 0x0190,
814 ROPLL_SDM_NUMERATOR_SIGN_RBR |
815 ROPLL_SDM_NUMERATOR_SIGN_HBR |
816 ROPLL_SDM_NUMERATOR_SIGN_HBR2,
817 FIELD_PREP(ROPLL_SDM_NUMERATOR_SIGN_RBR, 0x0) |
818 FIELD_PREP(ROPLL_SDM_NUMERATOR_SIGN_HBR, 0x1) |
819 FIELD_PREP(ROPLL_SDM_NUMERATOR_SIGN_HBR2, 0x1));
820
821 regmap_write(hdptx->regmap, 0x0194,
822 FIELD_PREP(ROPLL_SDM_NUMERATOR, 0x0));
823 regmap_write(hdptx->regmap, 0x0198,
824 FIELD_PREP(ROPLL_SDM_NUMERATOR, 0xd));
825 regmap_write(hdptx->regmap, 0x019c,
826 FIELD_PREP(ROPLL_SDM_NUMERATOR, 0xd));
827
828 regmap_update_bits(hdptx->regmap, 0x01a4, ROPLL_SDC_N_RBR,
829 FIELD_PREP(ROPLL_SDC_N_RBR, 0x2));
830 regmap_update_bits(hdptx->regmap, 0x01a8,
831 ROPLL_SDC_N_HBR | ROPLL_SDC_N_HBR2,
832 FIELD_PREP(ROPLL_SDC_N_HBR, 0x2) |
833 FIELD_PREP(ROPLL_SDC_N_HBR2, 0x2));
834
835 regmap_write(hdptx->regmap, 0x01b0,
836 FIELD_PREP(ROPLL_SDC_NUMERATOR, 0x3));
837 regmap_write(hdptx->regmap, 0x01b4,
838 FIELD_PREP(ROPLL_SDC_NUMERATOR, 0x7));
839 regmap_write(hdptx->regmap, 0x01b8,
840 FIELD_PREP(ROPLL_SDC_NUMERATOR, 0x7));
841
842 regmap_write(hdptx->regmap, 0x01c0,
843 FIELD_PREP(ROPLL_SDC_DENOMINATOR, 0x8));
844 regmap_write(hdptx->regmap, 0x01c4,
845 FIELD_PREP(ROPLL_SDC_DENOMINATOR, 0x18));
846 regmap_write(hdptx->regmap, 0x01c8,
847 FIELD_PREP(ROPLL_SDC_DENOMINATOR, 0x18));
848
849 regmap_update_bits(hdptx->regmap, 0x01d0,
850 OVRD_ROPLL_SDC_NDIV_RSTN | ROPLL_SDC_NDIV_RSTN,
851 FIELD_PREP(OVRD_ROPLL_SDC_NDIV_RSTN, 0x1) |
852 FIELD_PREP(ROPLL_SDC_NDIV_RSTN, 0x1));
853 regmap_update_bits(hdptx->regmap, 0x01dc, ANA_ROPLL_SSC_CLK_DIV_SEL,
854 FIELD_PREP(ANA_ROPLL_SSC_CLK_DIV_SEL, 0x1));
855
856 regmap_update_bits(hdptx->regmap, 0x0118,
857 ROPLL_ANA_CPP_CTRL_COARSE | ROPLL_ANA_CPP_CTRL_FINE,
858 FIELD_PREP(ROPLL_ANA_CPP_CTRL_COARSE, 0xe) |
859 FIELD_PREP(ROPLL_ANA_CPP_CTRL_FINE, 0xe));
860 regmap_update_bits(hdptx->regmap, 0x011c,
861 ROPLL_ANA_LPF_C_SEL_COARSE |
862 ROPLL_ANA_LPF_C_SEL_FINE,
863 FIELD_PREP(ROPLL_ANA_LPF_C_SEL_COARSE, 0x4) |
864 FIELD_PREP(ROPLL_ANA_LPF_C_SEL_FINE, 0x4));
865
866 regmap_update_bits(hdptx->regmap, 0x0204, ANA_PLL_CD_TX_SER_RATE_SEL,
867 FIELD_PREP(ANA_PLL_CD_TX_SER_RATE_SEL, 0x0));
868
869 regmap_update_bits(hdptx->regmap, 0x025c, DIG_CLK_SEL,
870 FIELD_PREP(DIG_CLK_SEL, 0x1));
871 regmap_update_bits(hdptx->regmap, 0x021c, ANA_PLL_TX_HS_CLK_EN,
872 FIELD_PREP(ANA_PLL_TX_HS_CLK_EN, 0x1));
873 regmap_update_bits(hdptx->regmap, 0x0204,
874 ANA_PLL_CD_HSCLK_EAST_EN | ANA_PLL_CD_HSCLK_WEST_EN,
875 FIELD_PREP(ANA_PLL_CD_HSCLK_EAST_EN, 0x1) |
876 FIELD_PREP(ANA_PLL_CD_HSCLK_WEST_EN, 0x0));
877 regmap_update_bits(hdptx->regmap, 0x0264, CMN_ROPLL_ALONE_MODE,
878 FIELD_PREP(CMN_ROPLL_ALONE_MODE, 0x1));
879 regmap_update_bits(hdptx->regmap, 0x0208, ANA_PLL_CD_VREG_GAIN_CTRL,
880 FIELD_PREP(ANA_PLL_CD_VREG_GAIN_CTRL, 0x4));
881 regmap_update_bits(hdptx->regmap, 0x00f0, ANA_LCPLL_RESERVED7,
882 FIELD_PREP(ANA_LCPLL_RESERVED7, 0x1));
883 regmap_update_bits(hdptx->regmap, 0x020c, ANA_PLL_CD_VREG_ICTRL,
884 FIELD_PREP(ANA_PLL_CD_VREG_ICTRL, 0x1));
885 regmap_update_bits(hdptx->regmap, 0x0214, ANA_PLL_SYNC_LOSS_DET_MODE,
886 FIELD_PREP(ANA_PLL_SYNC_LOSS_DET_MODE, 0x3));
887 regmap_update_bits(hdptx->regmap, 0x0210, PLL_LCRO_CLK_SEL,
888 FIELD_PREP(PLL_LCRO_CLK_SEL, 0x1));
889 regmap_update_bits(hdptx->regmap, 0x0268, HS_SPEED_SEL,
890 FIELD_PREP(HS_SPEED_SEL, 0x1));
891 regmap_update_bits(hdptx->regmap, 0x026c, LS_SPEED_SEL,
892 FIELD_PREP(LS_SPEED_SEL, 0x1));
893 }
894
rockchip_hdptx_phy_dp_aux_init(struct rockchip_hdptx_phy * hdptx)895 static int rockchip_hdptx_phy_dp_aux_init(struct rockchip_hdptx_phy *hdptx)
896 {
897 u32 status;
898 int ret;
899
900 regmap_update_bits(hdptx->regmap, 0x0414, ANA_SB_TX_HLVL_PROG,
901 FIELD_PREP(ANA_SB_TX_HLVL_PROG, 0x7));
902 regmap_update_bits(hdptx->regmap, 0x0418, ANA_SB_TX_LLVL_PROG,
903 FIELD_PREP(ANA_SB_TX_LLVL_PROG, 0x7));
904
905 regmap_update_bits(hdptx->regmap, 0x044c,
906 SB_RX_RCAL_OPT_CODE | SB_RX_RTERM_CTRL,
907 FIELD_PREP(SB_RX_RCAL_OPT_CODE, 0x1) |
908 FIELD_PREP(SB_RX_RTERM_CTRL, 0x3));
909 regmap_update_bits(hdptx->regmap, 0x0450,
910 SB_TG_SB_EN_DELAY_TIME | SB_TG_RXTERN_EN_DELAY_TIME,
911 FIELD_PREP(SB_TG_SB_EN_DELAY_TIME, 0x2) |
912 FIELD_PREP(SB_TG_RXTERN_EN_DELAY_TIME, 0x2));
913 regmap_update_bits(hdptx->regmap, 0x0454,
914 SB_READY_DELAY_TIME | SB_TG_OSC_EN_DELAY_TIME,
915 FIELD_PREP(SB_READY_DELAY_TIME, 0x2) |
916 FIELD_PREP(SB_TG_OSC_EN_DELAY_TIME, 0x2));
917 regmap_update_bits(hdptx->regmap, 0x0458,
918 SB_TG_OSC_EN_TO_AFC_RSTN_DELAT_TIME,
919 FIELD_PREP(SB_TG_OSC_EN_TO_AFC_RSTN_DELAT_TIME, 0x2));
920 regmap_update_bits(hdptx->regmap, 0x045c,
921 SB_TG_PLL_CD_VREG_FAST_PULSE_TIME,
922 FIELD_PREP(SB_TG_PLL_CD_VREG_FAST_PULSE_TIME, 0x4));
923 regmap_update_bits(hdptx->regmap, 0x0460,
924 SB_TG_EARC_DMRX_RECVRD_CLK_CNT,
925 FIELD_PREP(SB_TG_EARC_DMRX_RECVRD_CLK_CNT, 0xa));
926 regmap_update_bits(hdptx->regmap, 0x0468, SB_TG_CNT_RUN_NO_7_0,
927 FIELD_PREP(SB_TG_CNT_RUN_NO_7_0, 0x3));
928 regmap_update_bits(hdptx->regmap, 0x046c,
929 SB_EARC_SIG_DET_BYPASS | SB_AFC_TOL,
930 FIELD_PREP(SB_EARC_SIG_DET_BYPASS, 0x1) |
931 FIELD_PREP(SB_AFC_TOL, 0x3));
932 regmap_update_bits(hdptx->regmap, 0x0470, SB_AFC_STB_NUM,
933 FIELD_PREP(SB_AFC_STB_NUM, 0x4));
934 regmap_update_bits(hdptx->regmap, 0x0474, SB_TG_OSC_CNT_MIN,
935 FIELD_PREP(SB_TG_OSC_CNT_MIN, 0x67));
936 regmap_update_bits(hdptx->regmap, 0x0478, SB_TG_OSC_CNT_MAX,
937 FIELD_PREP(SB_TG_OSC_CNT_MAX, 0x6a));
938 regmap_update_bits(hdptx->regmap, 0x047c, SB_PWM_AFC_CTRL,
939 FIELD_PREP(SB_PWM_AFC_CTRL, 0x5));
940 regmap_update_bits(hdptx->regmap, 0x0434, ANA_SB_DMRX_LPBK_DATA,
941 FIELD_PREP(ANA_SB_DMRX_LPBK_DATA, 0x1));
942 regmap_update_bits(hdptx->regmap, 0x0440,
943 ANA_SB_VREG_OUT_SEL | ANA_SB_VREG_REF_SEL,
944 FIELD_PREP(ANA_SB_VREG_OUT_SEL, 0x1) |
945 FIELD_PREP(ANA_SB_VREG_REF_SEL, 0x1));
946 regmap_update_bits(hdptx->regmap, 0x043c, ANA_SB_VREG_GAIN_CTRL,
947 FIELD_PREP(ANA_SB_VREG_GAIN_CTRL, 0x0));
948 regmap_update_bits(hdptx->regmap, 0x0408, ANA_SB_RXTERM_OFFSP,
949 FIELD_PREP(ANA_SB_RXTERM_OFFSP, 0x3));
950 regmap_update_bits(hdptx->regmap, 0x040c, ANA_SB_RXTERM_OFFSN,
951 FIELD_PREP(ANA_SB_RXTERM_OFFSN, 0x3));
952 regmap_update_bits(hdptx->regmap, 0x047c, SB_RCAL_RSTN,
953 FIELD_PREP(SB_RCAL_RSTN, 0x1));
954 regmap_update_bits(hdptx->regmap, 0x0410, SB_AUX_EN,
955 FIELD_PREP(SB_AUX_EN, 0x1));
956 regmap_update_bits(hdptx->regmap, 0x0480, SB_AUX_EN_IN,
957 FIELD_PREP(SB_AUX_EN_IN, 0x1));
958 regmap_update_bits(hdptx->regmap, 0x040c, OVRD_SB_RX_RESCAL_DONE,
959 FIELD_PREP(OVRD_SB_RX_RESCAL_DONE, 0x1));
960 regmap_update_bits(hdptx->regmap, 0x0410, OVRD_SB_EN,
961 FIELD_PREP(OVRD_SB_EN, 0x1));
962 regmap_update_bits(hdptx->regmap, 0x0408, OVRD_SB_RXTERM_EN,
963 FIELD_PREP(OVRD_SB_RXTERM_EN, 0x1));
964 regmap_update_bits(hdptx->regmap, 0x043c, OVRD_SB_VREG_EN,
965 FIELD_PREP(OVRD_SB_VREG_EN, 0x1));
966 regmap_update_bits(hdptx->regmap, 0x0410, OVRD_SB_AUX_EN,
967 FIELD_PREP(OVRD_SB_AUX_EN, 0x1));
968
969 rockchip_grf_write(hdptx->grf, HDPTXPHY_GRF_CON0, BGR_EN,
970 FIELD_PREP(BGR_EN, 0x1));
971 rockchip_grf_write(hdptx->grf, HDPTXPHY_GRF_CON0, BIAS_EN,
972 FIELD_PREP(BIAS_EN, 0x1));
973 udelay(20);
974
975 reset_control_deassert(hdptx->init_reset);
976 udelay(20);
977 reset_control_deassert(hdptx->cmn_reset);
978 udelay(20);
979
980 regmap_update_bits(hdptx->regmap, 0x040c, SB_RX_RESCAL_DONE,
981 FIELD_PREP(SB_RX_RESCAL_DONE, 0x1));
982 udelay(100);
983 regmap_update_bits(hdptx->regmap, 0x0410, SB_EN,
984 FIELD_PREP(SB_EN, 0x1));
985 udelay(100);
986 regmap_update_bits(hdptx->regmap, 0x0408, SB_RXRERM_EN,
987 FIELD_PREP(SB_RXRERM_EN, 0x1));
988 udelay(20);
989 regmap_update_bits(hdptx->regmap, 0x043c, SB_VREG_EN,
990 FIELD_PREP(SB_VREG_EN, 0x1));
991 udelay(20);
992 regmap_update_bits(hdptx->regmap, 0x0410, SB_AUX_EN,
993 FIELD_PREP(SB_AUX_EN, 0x1));
994 udelay(100);
995
996 ret = regmap_read_poll_timeout(hdptx->grf, HDPTXPHY_GRF_STATUS0,
997 status, FIELD_GET(SB_RDY, status),
998 50, 1000);
999 if (ret) {
1000 dev_err(hdptx->dev, "timeout waiting for sb_rdy\n");
1001 return ret;
1002 }
1003
1004 return 0;
1005 }
1006
rockchip_hdptx_phy_reset(struct rockchip_hdptx_phy * hdptx)1007 static void rockchip_hdptx_phy_reset(struct rockchip_hdptx_phy *hdptx)
1008 {
1009 u32 lane;
1010
1011 reset_control_assert(hdptx->lane_reset);
1012 reset_control_assert(hdptx->cmn_reset);
1013 reset_control_assert(hdptx->init_reset);
1014
1015 reset_control_assert(hdptx->apb_reset);
1016 udelay(10);
1017 reset_control_deassert(hdptx->apb_reset);
1018
1019 for (lane = 0; lane < 4; lane++)
1020 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c04),
1021 OVRD_LN_TX_DRV_EI_EN | LN_TX_DRV_EI_EN,
1022 FIELD_PREP(OVRD_LN_TX_DRV_EI_EN, 1) |
1023 FIELD_PREP(LN_TX_DRV_EI_EN, 0));
1024
1025 rockchip_grf_write(hdptx->grf, HDPTXPHY_GRF_CON0, PLL_EN,
1026 FIELD_PREP(PLL_EN, 0));
1027 rockchip_grf_write(hdptx->grf, HDPTXPHY_GRF_CON0, BIAS_EN,
1028 FIELD_PREP(BIAS_EN, 0));
1029 rockchip_grf_write(hdptx->grf, HDPTXPHY_GRF_CON0, BGR_EN,
1030 FIELD_PREP(BGR_EN, 0));
1031 }
1032
rockchip_hdptx_phy_enabled(struct rockchip_hdptx_phy * hdptx)1033 static bool rockchip_hdptx_phy_enabled(struct rockchip_hdptx_phy *hdptx)
1034 {
1035 u32 status;
1036
1037 regmap_read(hdptx->grf, HDPTXPHY_GRF_STATUS0, &status);
1038
1039 return FIELD_GET(SB_RDY, status);
1040 }
1041
rockchip_hdptx_phy_power_on(struct phy * phy)1042 static int rockchip_hdptx_phy_power_on(struct phy *phy)
1043 {
1044 struct rockchip_hdptx_phy *hdptx = phy_get_drvdata(phy);
1045 enum phy_mode mode = phy_get_mode(phy);
1046 u32 lane;
1047 int ret;
1048
1049 ret = clk_bulk_prepare_enable(hdptx->nr_clks, hdptx->clks);
1050 if (ret)
1051 return ret;
1052
1053 if (rockchip_hdptx_phy_enabled(hdptx))
1054 return 0;
1055
1056 rockchip_hdptx_phy_reset(hdptx);
1057
1058 for (lane = 0; lane < 4; lane++) {
1059 u32 invert = hdptx->lane_polarity_invert[lane];
1060
1061 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c78),
1062 LN_POLARITY_INV,
1063 FIELD_PREP(LN_POLARITY_INV, invert));
1064 }
1065
1066 if (mode == PHY_MODE_DP) {
1067 rockchip_grf_write(hdptx->grf, HDPTXPHY_GRF_CON0,
1068 HDPTX_MODE_SEL,
1069 FIELD_PREP(HDPTX_MODE_SEL, 0x1));
1070
1071 regmap_update_bits(hdptx->regmap, 0x0800, PROTOCOL_SEL,
1072 FIELD_PREP(PROTOCOL_SEL, 0x0));
1073 regmap_update_bits(hdptx->regmap, 0x0818, DATA_BUS_WIDTH,
1074 FIELD_PREP(DATA_BUS_WIDTH, 0x1));
1075 regmap_update_bits(hdptx->regmap, 0x0818, BUS_WIDTH_SEL,
1076 FIELD_PREP(BUS_WIDTH_SEL, 0x0));
1077
1078 rockchip_hdptx_phy_dp_pll_init(hdptx);
1079 rockchip_hdptx_phy_dp_aux_init(hdptx);
1080 } else {
1081 rockchip_grf_write(hdptx->grf, HDPTXPHY_GRF_CON0,
1082 HDPTX_MODE_SEL,
1083 FIELD_PREP(HDPTX_MODE_SEL, 0x0));
1084
1085 regmap_update_bits(hdptx->regmap, 0x0800, PROTOCOL_SEL,
1086 FIELD_PREP(PROTOCOL_SEL, 0x1));
1087 }
1088
1089 return 0;
1090 }
1091
rockchip_hdptx_phy_power_off(struct phy * phy)1092 static int rockchip_hdptx_phy_power_off(struct phy *phy)
1093 {
1094 struct rockchip_hdptx_phy *hdptx = phy_get_drvdata(phy);
1095
1096 rockchip_hdptx_phy_reset(hdptx);
1097
1098 clk_bulk_disable_unprepare(hdptx->nr_clks, hdptx->clks);
1099
1100 return 0;
1101 }
1102
1103 static const struct phy_ops rockchip_hdptx_phy_ops = {
1104 .set_mode = rockchip_hdptx_phy_set_mode,
1105 .configure = rockchip_hdptx_phy_configure,
1106 .power_on = rockchip_hdptx_phy_power_on,
1107 .power_off = rockchip_hdptx_phy_power_off,
1108 .owner = THIS_MODULE,
1109 };
1110
rockchip_hdptx_phy_is_accissible_reg(struct device * dev,unsigned int reg)1111 static bool rockchip_hdptx_phy_is_accissible_reg(struct device *dev,
1112 unsigned int reg)
1113 {
1114 switch (reg) {
1115 case 0x0000 ... 0x029c: /* CMN Register */
1116 case 0x0400 ... 0x04a4: /* Sideband Register */
1117 case 0x0800 ... 0x08a4: /* Lane Top Register */
1118 case 0x0c00 ... 0x0cb4: /* Lane 0 Register */
1119 case 0x1000 ... 0x10b4: /* Lane 1 Register */
1120 case 0x1400 ... 0x14b4: /* Lane 2 Register */
1121 case 0x1800 ... 0x18b4: /* Lane 3 Register */
1122 return true;
1123 default:
1124 return false;
1125 }
1126 }
1127
1128 static const struct regmap_config rockchip_hdptx_phy_regmap_config = {
1129 .reg_bits = 32,
1130 .reg_stride = 4,
1131 .val_bits = 32,
1132 .fast_io = true,
1133 .max_register = 0x18b4,
1134 .readable_reg = rockchip_hdptx_phy_is_accissible_reg,
1135 .writeable_reg = rockchip_hdptx_phy_is_accissible_reg,
1136 };
1137
rockchip_hdptx_phy_probe(struct platform_device * pdev)1138 static int rockchip_hdptx_phy_probe(struct platform_device *pdev)
1139 {
1140 struct device *dev = &pdev->dev;
1141 struct rockchip_hdptx_phy *hdptx;
1142 struct phy *phy;
1143 struct phy_provider *phy_provider;
1144 void __iomem *regs;
1145 int ret;
1146
1147 hdptx = devm_kzalloc(dev, sizeof(*hdptx), GFP_KERNEL);
1148 if (!hdptx)
1149 return -ENOMEM;
1150
1151 hdptx->dev = dev;
1152 platform_set_drvdata(pdev, hdptx);
1153
1154 regs = devm_platform_ioremap_resource(pdev, 0);
1155 if (IS_ERR(regs))
1156 return PTR_ERR(regs);
1157
1158 hdptx->regmap = devm_regmap_init_mmio(dev, regs,
1159 &rockchip_hdptx_phy_regmap_config);
1160 if (IS_ERR(hdptx->regmap))
1161 return dev_err_probe(dev, PTR_ERR(hdptx->regmap),
1162 "failed to create regmap\n");
1163
1164 ret = devm_clk_bulk_get_all(dev, &hdptx->clks);
1165 if (ret < 1)
1166 return dev_err_probe(dev, ret, "failed to get clocks\n");
1167
1168 hdptx->nr_clks = ret;
1169
1170 hdptx->apb_reset = devm_reset_control_get(dev, "apb");
1171 if (IS_ERR(hdptx->apb_reset))
1172 return dev_err_probe(dev, PTR_ERR(hdptx->apb_reset),
1173 "failed to get apb reset\n");
1174
1175 hdptx->init_reset = devm_reset_control_get(dev, "init");
1176 if (IS_ERR(hdptx->init_reset))
1177 return dev_err_probe(dev, PTR_ERR(hdptx->init_reset),
1178 "failed to get init reset\n");
1179
1180 hdptx->cmn_reset = devm_reset_control_get(dev, "cmn");
1181 if (IS_ERR(hdptx->cmn_reset))
1182 return dev_err_probe(dev, PTR_ERR(hdptx->cmn_reset),
1183 "failed to get cmn reset\n");
1184
1185 hdptx->lane_reset = devm_reset_control_get(dev, "lane");
1186 if (IS_ERR(hdptx->lane_reset))
1187 return dev_err_probe(dev, PTR_ERR(hdptx->lane_reset),
1188 "failed to get lane reset\n");
1189
1190 hdptx->grf = syscon_regmap_lookup_by_phandle(dev->of_node,
1191 "rockchip,grf");
1192 if (IS_ERR(hdptx->grf))
1193 return dev_err_probe(dev, PTR_ERR(hdptx->grf),
1194 "failed to get grf regmap\n");
1195
1196 device_property_read_u32_array(dev, "lane-polarity-invert",
1197 hdptx->lane_polarity_invert, 4);
1198
1199 ret = rockchip_hdptx_phy_parse_training_table(dev);
1200 if (ret)
1201 return dev_err_probe(dev, ret, "failed to parse training table\n");
1202
1203 phy = devm_phy_create(dev, NULL, &rockchip_hdptx_phy_ops);
1204 if (IS_ERR(phy))
1205 return dev_err_probe(dev, PTR_ERR(phy), "failed to create PHY\n");
1206
1207 phy_set_drvdata(phy, hdptx);
1208
1209 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
1210
1211 return PTR_ERR_OR_ZERO(phy_provider);
1212 }
1213
1214 static const struct of_device_id rockchip_hdptx_phy_of_match[] = {
1215 { .compatible = "rockchip,rk3588-hdptx-phy", },
1216 {}
1217 };
1218 MODULE_DEVICE_TABLE(of, rockchip_hdptx_phy_of_match);
1219
1220 static struct platform_driver rockchip_hdptx_phy_driver = {
1221 .probe = rockchip_hdptx_phy_probe,
1222 .driver = {
1223 .name = "rockchip-hdptx-phy",
1224 .of_match_table = rockchip_hdptx_phy_of_match,
1225 }
1226 };
1227 module_platform_driver(rockchip_hdptx_phy_driver);
1228
1229 MODULE_AUTHOR("Wyon Bi <bivvy.bi@rock-chips.com>");
1230 MODULE_DESCRIPTION("Rockchip HDMI/DP Combo PHY with Samsung IP block");
1231 MODULE_LICENSE("GPL v2");
1232