xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2*4882a593Smuzhiyun%YAML 1.2
3*4882a593Smuzhiyun---
4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/phy/phy-rockchip-usbdp.yaml#
5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml#
6*4882a593Smuzhiyun
7*4882a593Smuzhiyuntitle: Rockchip USBDP Combo PHY with Samsung IP block
8*4882a593Smuzhiyun
9*4882a593Smuzhiyunmaintainers:
10*4882a593Smuzhiyun  - Frank Wang <frank.wang@rock-chips.com>
11*4882a593Smuzhiyun  - Zhang Yubing <yubing.zhang@rock-chips.com>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyunproperties:
14*4882a593Smuzhiyun  compatible:
15*4882a593Smuzhiyun    enum:
16*4882a593Smuzhiyun      - rockchip,rk3588-usbdp-phy
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun  reg:
19*4882a593Smuzhiyun    maxItems: 1
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun  clocks:
22*4882a593Smuzhiyun    items:
23*4882a593Smuzhiyun      - description: phy ref clock.
24*4882a593Smuzhiyun      - description: phy pcs immortal clock.
25*4882a593Smuzhiyun      - description: phy peripheral clock.
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun  clock-names:
28*4882a593Smuzhiyun    items:
29*4882a593Smuzhiyun      - const: refclk
30*4882a593Smuzhiyun      - const: immortal
31*4882a593Smuzhiyun      - const: pclk
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun  resets:
34*4882a593Smuzhiyun      - description: phy init reset.
35*4882a593Smuzhiyun      - description: phy cmn reset.
36*4882a593Smuzhiyun      - description: phy lane reset.
37*4882a593Smuzhiyun      - description: phy pcs apb reset.
38*4882a593Smuzhiyun      - description: phy pma apb reset.
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun  reset-names:
41*4882a593Smuzhiyun      - const: init
42*4882a593Smuzhiyun      - const: cmn
43*4882a593Smuzhiyun      - const: lane
44*4882a593Smuzhiyun      - const: pcs_apb
45*4882a593Smuzhiyun      - const: pma_apb
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun  rockchip,dp-lane-mux:
48*4882a593Smuzhiyun    minItems: 2
49*4882a593Smuzhiyun    maxItems: 4
50*4882a593Smuzhiyun    description:
51*4882a593Smuzhiyun      An array of physical Tyep-C lanes indexes. Position of an entry determines
52*4882a593Smuzhiyun      the dp lane index, while the value of an entry indicater physical Type-C lane.
53*4882a593Smuzhiyun      The support dp lanes number are 2 or 4. e.g. for 2 lanes dp lanes map, we could
54*4882a593Smuzhiyun      have "rockchip,dp-lane-mux = <2, 3>;", assuming dp lane0 on Type-C phy lane2,
55*4882a593Smuzhiyun      dp lane1 on Type-C phy lane3. For 4 lanes dp lanes map, we could have
56*4882a593Smuzhiyun      "rockchip,dp-lane-mux = <0, 1, 2, 3>;", assuming dp lane0 on Type-C phy lane0,
57*4882a593Smuzhiyun      dp lane1 on Type-C phy lane1, dp lane2 on Type-C phy lane2, dp lane3 on Type-C
58*4882a593Smuzhiyun      phy lane3. If dp lane map by DisplayPort Alt mode, this property is not need.
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun  rockchip,u2phy-grf:
61*4882a593Smuzhiyun    $ref: /schemas/types.yaml#/definitions/phandle
62*4882a593Smuzhiyun    description:
63*4882a593Smuzhiyun      Phandle to the syscon managing the 'usb2 phy general register files'.
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun  rockchip,usb-grf:
66*4882a593Smuzhiyun    $ref: /schemas/types.yaml#/definitions/phandle
67*4882a593Smuzhiyun    description:
68*4882a593Smuzhiyun      Phandle to the syscon managing the 'usb general register files'.
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun  rockchip,usbdpphy-grf:
71*4882a593Smuzhiyun    $ref: /schemas/types.yaml#/definitions/phandle
72*4882a593Smuzhiyun    description:
73*4882a593Smuzhiyun      Phandle to the syscon managing the 'usbdp phy general register files'.
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun  rockchip,vo-grf:
76*4882a593Smuzhiyun    $ref: /schemas/types.yaml#/definitions/phandle
77*4882a593Smuzhiyun    description:
78*4882a593Smuzhiyun      Phandle to the syscon managing the 'video output general register files'.
79*4882a593Smuzhiyun      When select the dp lane mapping will request its phandle.
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun  dp-port:
82*4882a593Smuzhiyun    type: object
83*4882a593Smuzhiyun    additionalProperties: false
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun    properties:
86*4882a593Smuzhiyun      "#phy-cells":
87*4882a593Smuzhiyun        const: 0
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun    required:
90*4882a593Smuzhiyun      - "#phy-cells"
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun  u3-port:
93*4882a593Smuzhiyun    type: object
94*4882a593Smuzhiyun    additionalProperties: false
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun    properties:
97*4882a593Smuzhiyun      "#phy-cells":
98*4882a593Smuzhiyun        const: 0
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun    required:
101*4882a593Smuzhiyun      - "#phy-cells"
102*4882a593Smuzhiyun
103*4882a593Smuzhiyunrequired:
104*4882a593Smuzhiyun  - compatible
105*4882a593Smuzhiyun  - reg
106*4882a593Smuzhiyun  - clocks
107*4882a593Smuzhiyun  - clock-names
108*4882a593Smuzhiyun  - resets
109*4882a593Smuzhiyun  - reset-names
110*4882a593Smuzhiyun  - dp-port
111*4882a593Smuzhiyun  - u3-port
112*4882a593Smuzhiyun
113*4882a593SmuzhiyunadditionalProperties: false
114*4882a593Smuzhiyun
115*4882a593Smuzhiyunexamples:
116*4882a593Smuzhiyun  - |
117*4882a593Smuzhiyun    #include <dt-bindings/clock/rk3588-cru.h>
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun    usbdp_phy0: phy@fed80000 {
120*4882a593Smuzhiyun      compatible = "rockchip,rk3588-usbdp-phy";
121*4882a593Smuzhiyun      reg = <0x0 0xfed80000 0x0 0x10000>;
122*4882a593Smuzhiyun      rockchip,u2phy-grf = <&usb2phy0_grf>;
123*4882a593Smuzhiyun      rockchip,usb-grf = <&usb_grf>;
124*4882a593Smuzhiyun      rockchip,usbdpphy-grf = <&usbdpphy0_grf>;
125*4882a593Smuzhiyun      rockchip,vo-grf = <&vo0_grf>;
126*4882a593Smuzhiyun      clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
127*4882a593Smuzhiyun               <&cru CLK_USBDP_PHY0_IMMORTAL>,
128*4882a593Smuzhiyun               <&cru PCLK_USBDPPHY0>;
129*4882a593Smuzhiyun      clock-names = "refclk", "immortal", "pclk";
130*4882a593Smuzhiyun      resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>,
131*4882a593Smuzhiyun               <&cru SRST_USBDP_COMBO_PHY0_CMN>,
132*4882a593Smuzhiyun               <&cru SRST_USBDP_COMBO_PHY0_LANE>,
133*4882a593Smuzhiyun               <&cru SRST_USBDP_COMBO_PHY0_PCS>,
134*4882a593Smuzhiyun               <&cru SRST_P_USBDPPHY0>;
135*4882a593Smuzhiyun      reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
136*4882a593Smuzhiyun      status = "disabled";
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun      usbdp_phy0_dp: dp-port {
139*4882a593Smuzhiyun        #phy-cells = <0>;
140*4882a593Smuzhiyun        status = "disabled";
141*4882a593Smuzhiyun      };
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun      usbdp_phy0_u3: u3-port {
144*4882a593Smuzhiyun        #phy-cells = <0>;
145*4882a593Smuzhiyun        status = "disabled";
146*4882a593Smuzhiyun    };
147