Lines Matching +full:4 +full:- +full:lane
1 // SPDX-License-Identifier: GPL-2.0
10 #include <generic-phy.h>
44 #define ROPLL_ANA_CPP_CTRL_COARSE GENMASK(7, 4)
61 #define ANA_ROPLL_PMS_PDIV GENMASK(7, 4)
65 #define ROPLL_PMS_SDIV_RBR GENMASK(7, 4)
69 #define ROPLL_PMS_SDIV_HBR2 GENMASK(7, 4)
74 #define ROPLL_REF_CLK_SEL GENMASK(4, 3)
79 #define ROPLL_SDM_RSTN BIT(4)
87 #define ROPLL_SDC_RSTN BIT(4)
166 #define LS_SPEED_SEL BIT(4)
170 #define SB_RXRERM_EN BIT(4)
180 #define SB_EN BIT(4)
188 #define ANA_SB_TX_LLVL_PROG GENMASK(6, 4)
191 #define ANA_SB_DMRX_LPBK_DATA BIT(4)
203 #define SB_RX_RCAL_OPT_CODE GENMASK(5, 4)
215 #define SB_TG_OSC_EN_TO_AFC_RSTN_DELAT_TIME GENMASK(6, 4)
227 #define SB_EARC_SIG_DET_BYPASS BIT(4)
248 #define SB_READY BIT(4)
266 #define LN_TX_DRV_LVL_CTRL GENMASK(4, 0)
269 #define OVRD_LN_TX_DRV_POST_LVL_CTRL BIT(4)
278 #define LN_ANA_TX_DRV_IDRV_IUP_CTRL GENMASK(4, 2)
286 #define LN_ANA_TX_JEQ_EN BIT(4)
290 #define LN_TX_JEQ_EVEN_CTRL_HBR GENMASK(7, 4)
294 #define LN_TX_JEQ_EVEN_CTRL_HBR3 GENMASK(7, 4)
298 #define LN_TX_JEQ_ODD_CTRL_HBR GENMASK(7, 4)
302 #define LN_TX_JEQ_ODD_CTRL_HBR3 GENMASK(7, 4)
322 #define LANE_REG(lane, offset) (0x400 * (lane) + (offset)) argument
333 u32 lane_polarity_invert[4];
352 static struct tx_drv_ctrl tx_drv_ctrl_rbr[4][4] = {
353 /* voltage swing 0, pre-emphasis 0->3 */
361 /* voltage swing 1, pre-emphasis 0->2 */
368 /* voltage swing 2, pre-emphasis 0->1 */
374 /* voltage swing 3, pre-emphasis 0 */
380 static struct tx_drv_ctrl tx_drv_ctrl_hbr[4][4] = {
381 /* voltage swing 0, pre-emphasis 0->3 */
389 /* voltage swing 1, pre-emphasis 0->2 */
396 /* voltage swing 2, pre-emphasis 0->1 */
402 /* voltage swing 3, pre-emphasis 0 */
408 static struct tx_drv_ctrl tx_drv_ctrl_hbr2[4][4] = {
409 /* voltage swing 0, pre-emphasis 0->3 */
417 /* voltage swing 1, pre-emphasis 0->2 */
424 /* voltage swing 2, pre-emphasis 0->1 */
430 /* voltage swing 3, pre-emphasis 0 */
443 prop = dev_read_u8_array_ptr(dev, "training-table", size); in rockchip_hdptx_phy_parse_training_table()
449 return -ENOMEM; in rockchip_hdptx_phy_parse_training_table()
455 for (i = 0; i < 4; i++) { in rockchip_hdptx_phy_parse_training_table()
456 for (j = 0; j < 4; j++) { in rockchip_hdptx_phy_parse_training_table()
492 if (dp->set_rate) { in rockchip_hdptx_phy_verify_config()
493 switch (dp->link_rate) { in rockchip_hdptx_phy_verify_config()
499 return -EINVAL; in rockchip_hdptx_phy_verify_config()
503 switch (dp->lanes) { in rockchip_hdptx_phy_verify_config()
506 case 4: in rockchip_hdptx_phy_verify_config()
509 return -EINVAL; in rockchip_hdptx_phy_verify_config()
512 if (dp->set_voltages) { in rockchip_hdptx_phy_verify_config()
513 for (i = 0; i < dp->lanes; i++) { in rockchip_hdptx_phy_verify_config()
514 if (dp->voltage[i] > 3 || dp->pre[i] > 3) in rockchip_hdptx_phy_verify_config()
515 return -EINVAL; in rockchip_hdptx_phy_verify_config()
517 if (dp->voltage[i] + dp->pre[i] > 3) in rockchip_hdptx_phy_verify_config()
518 return -EINVAL; in rockchip_hdptx_phy_verify_config()
527 u8 lane) in rockchip_hdptx_phy_set_voltage() argument
531 switch (dp->link_rate) { in rockchip_hdptx_phy_set_voltage()
533 ctrl = &tx_drv_ctrl_rbr[dp->voltage[lane]][dp->pre[lane]]; in rockchip_hdptx_phy_set_voltage()
534 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c44), in rockchip_hdptx_phy_set_voltage()
539 ctrl = &tx_drv_ctrl_hbr[dp->voltage[lane]][dp->pre[lane]]; in rockchip_hdptx_phy_set_voltage()
540 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c44), in rockchip_hdptx_phy_set_voltage()
546 ctrl = &tx_drv_ctrl_hbr2[dp->voltage[lane]][dp->pre[lane]]; in rockchip_hdptx_phy_set_voltage()
547 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c44), in rockchip_hdptx_phy_set_voltage()
553 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c0c), in rockchip_hdptx_phy_set_voltage()
557 ctrl->tx_drv_lvl_ctrl)); in rockchip_hdptx_phy_set_voltage()
558 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c10), in rockchip_hdptx_phy_set_voltage()
563 ctrl->tx_drv_post_lvl_ctrl)); in rockchip_hdptx_phy_set_voltage()
564 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c18), in rockchip_hdptx_phy_set_voltage()
569 ctrl->ana_tx_drv_idrv_idn_ctrl) | in rockchip_hdptx_phy_set_voltage()
571 ctrl->ana_tx_drv_idrv_iup_ctrl) | in rockchip_hdptx_phy_set_voltage()
573 ctrl->ana_tx_drv_accdrv_en)); in rockchip_hdptx_phy_set_voltage()
574 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c1c), in rockchip_hdptx_phy_set_voltage()
579 ctrl->ana_tx_drv_accdrv_ctrl)); in rockchip_hdptx_phy_set_voltage()
580 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c6c), in rockchip_hdptx_phy_set_voltage()
583 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c58), in rockchip_hdptx_phy_set_voltage()
586 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c40), in rockchip_hdptx_phy_set_voltage()
594 u8 lane; in rockchip_hdptx_phy_set_voltages() local
598 for (lane = 0; lane < dp->lanes; lane++) in rockchip_hdptx_phy_set_voltages()
599 rockchip_hdptx_phy_set_voltage(hdptx, dp, lane); in rockchip_hdptx_phy_set_voltages()
601 reset_deassert(&hdptx->lane_reset); in rockchip_hdptx_phy_set_voltages()
603 ret = regmap_read_poll_timeout(hdptx->grf, HDPTXPHY_GRF_STATUS0, in rockchip_hdptx_phy_set_voltages()
607 dev_err(hdptx->dev, "timeout waiting for phy_rdy\n"); in rockchip_hdptx_phy_set_voltages()
620 reset_assert(&hdptx->lane_reset); in rockchip_hdptx_phy_set_rate()
622 reset_assert(&hdptx->cmn_reset); in rockchip_hdptx_phy_set_rate()
624 rockchip_grf_write(hdptx->grf, HDPTXPHY_GRF_CON0, PLL_EN, in rockchip_hdptx_phy_set_rate()
627 regmap_update_bits(hdptx->regmap, 0x081c, LANE_EN, in rockchip_hdptx_phy_set_rate()
630 switch (dp->link_rate) { in rockchip_hdptx_phy_set_rate()
641 return -EINVAL; in rockchip_hdptx_phy_set_rate()
644 regmap_update_bits(hdptx->regmap, 0x0254, DP_TX_LINK_BW, in rockchip_hdptx_phy_set_rate()
647 if (dp->ssc) { in rockchip_hdptx_phy_set_rate()
648 regmap_update_bits(hdptx->regmap, 0x01d0, in rockchip_hdptx_phy_set_rate()
652 regmap_update_bits(hdptx->regmap, 0x01d4, in rockchip_hdptx_phy_set_rate()
655 regmap_update_bits(hdptx->regmap, 0x01d8, in rockchip_hdptx_phy_set_rate()
658 regmap_update_bits(hdptx->regmap, 0x0264, SSC_EN, in rockchip_hdptx_phy_set_rate()
661 regmap_update_bits(hdptx->regmap, 0x01d0, in rockchip_hdptx_phy_set_rate()
665 regmap_update_bits(hdptx->regmap, 0x01d4, in rockchip_hdptx_phy_set_rate()
668 regmap_update_bits(hdptx->regmap, 0x01d8, in rockchip_hdptx_phy_set_rate()
671 regmap_update_bits(hdptx->regmap, 0x0264, SSC_EN, in rockchip_hdptx_phy_set_rate()
675 rockchip_grf_write(hdptx->grf, HDPTXPHY_GRF_CON0, PLL_EN, in rockchip_hdptx_phy_set_rate()
678 reset_deassert(&hdptx->cmn_reset); in rockchip_hdptx_phy_set_rate()
681 ret = regmap_read_poll_timeout(hdptx->grf, HDPTXPHY_GRF_STATUS0, in rockchip_hdptx_phy_set_rate()
685 dev_err(hdptx->dev, "timeout waiting for pll_lock_done\n"); in rockchip_hdptx_phy_set_rate()
689 regmap_update_bits(hdptx->regmap, 0x081c, LANE_EN, in rockchip_hdptx_phy_set_rate()
690 FIELD_PREP(LANE_EN, GENMASK(dp->lanes - 1, 0))); in rockchip_hdptx_phy_set_rate()
698 struct rockchip_hdptx_phy *hdptx = dev_get_priv(phy->dev); in rockchip_hdptx_phy_configure()
703 return -EINVAL; in rockchip_hdptx_phy_configure()
705 ret = rockchip_hdptx_phy_verify_config(hdptx, &opts->dp); in rockchip_hdptx_phy_configure()
707 dev_err(hdptx->dev, "invalid params for phy configure\n"); in rockchip_hdptx_phy_configure()
711 if (opts->dp.set_rate) { in rockchip_hdptx_phy_configure()
712 ret = rockchip_hdptx_phy_set_rate(hdptx, &opts->dp); in rockchip_hdptx_phy_configure()
714 dev_err(hdptx->dev, "failed to set rate: %d\n", ret); in rockchip_hdptx_phy_configure()
719 if (opts->dp.set_voltages) { in rockchip_hdptx_phy_configure()
720 ret = rockchip_hdptx_phy_set_voltages(hdptx, &opts->dp); in rockchip_hdptx_phy_configure()
722 dev_err(hdptx->dev, "failed to set voltages: %d\n", in rockchip_hdptx_phy_configure()
733 regmap_update_bits(hdptx->regmap, 0x0020, OVRD_LCPLL_EN | LCPLL_EN, in rockchip_hdptx_phy_dp_pll_init()
736 regmap_update_bits(hdptx->regmap, 0x00f4, OVRD_ROPLL_EN | ROPLL_EN, in rockchip_hdptx_phy_dp_pll_init()
739 regmap_update_bits(hdptx->regmap, 0x0138, ANA_ROPLL_PI_EN, in rockchip_hdptx_phy_dp_pll_init()
741 regmap_write(hdptx->regmap, 0x0144, FIELD_PREP(ROPLL_PMS_MDIV, 0x87)); in rockchip_hdptx_phy_dp_pll_init()
742 regmap_write(hdptx->regmap, 0x0148, FIELD_PREP(ROPLL_PMS_MDIV, 0x71)); in rockchip_hdptx_phy_dp_pll_init()
743 regmap_write(hdptx->regmap, 0x014c, FIELD_PREP(ROPLL_PMS_MDIV, 0x71)); in rockchip_hdptx_phy_dp_pll_init()
744 regmap_write(hdptx->regmap, 0x0154, in rockchip_hdptx_phy_dp_pll_init()
746 regmap_write(hdptx->regmap, 0x0158, in rockchip_hdptx_phy_dp_pll_init()
748 regmap_write(hdptx->regmap, 0x015c, in rockchip_hdptx_phy_dp_pll_init()
750 regmap_write(hdptx->regmap, 0x0164, in rockchip_hdptx_phy_dp_pll_init()
753 regmap_write(hdptx->regmap, 0x0168, in rockchip_hdptx_phy_dp_pll_init()
756 regmap_update_bits(hdptx->regmap, 0x016c, ROPLL_PMS_SDIV_HBR2, in rockchip_hdptx_phy_dp_pll_init()
758 regmap_update_bits(hdptx->regmap, 0x0178, ANA_ROPLL_SDM_EN, in rockchip_hdptx_phy_dp_pll_init()
760 regmap_update_bits(hdptx->regmap, 0x0178, in rockchip_hdptx_phy_dp_pll_init()
764 regmap_update_bits(hdptx->regmap, 0x0178, ROPLL_SDC_FRACTIONAL_EN_RBR, in rockchip_hdptx_phy_dp_pll_init()
766 regmap_update_bits(hdptx->regmap, 0x0178, ROPLL_SDC_FRACTIONAL_EN_HBR, in rockchip_hdptx_phy_dp_pll_init()
768 regmap_update_bits(hdptx->regmap, 0x0178, ROPLL_SDC_FRACTIONAL_EN_HBR2, in rockchip_hdptx_phy_dp_pll_init()
770 regmap_update_bits(hdptx->regmap, 0x017c, in rockchip_hdptx_phy_dp_pll_init()
774 regmap_write(hdptx->regmap, 0x0180, in rockchip_hdptx_phy_dp_pll_init()
776 regmap_write(hdptx->regmap, 0x0184, in rockchip_hdptx_phy_dp_pll_init()
778 regmap_write(hdptx->regmap, 0x0188, in rockchip_hdptx_phy_dp_pll_init()
780 regmap_update_bits(hdptx->regmap, 0x0190, in rockchip_hdptx_phy_dp_pll_init()
787 regmap_write(hdptx->regmap, 0x0194, in rockchip_hdptx_phy_dp_pll_init()
789 regmap_write(hdptx->regmap, 0x0198, in rockchip_hdptx_phy_dp_pll_init()
791 regmap_write(hdptx->regmap, 0x019c, in rockchip_hdptx_phy_dp_pll_init()
793 regmap_update_bits(hdptx->regmap, 0x01a4, ROPLL_SDC_N_RBR, in rockchip_hdptx_phy_dp_pll_init()
795 regmap_update_bits(hdptx->regmap, 0x01a8, in rockchip_hdptx_phy_dp_pll_init()
799 regmap_write(hdptx->regmap, 0x01b0, in rockchip_hdptx_phy_dp_pll_init()
801 regmap_write(hdptx->regmap, 0x01b4, in rockchip_hdptx_phy_dp_pll_init()
803 regmap_write(hdptx->regmap, 0x01b8, in rockchip_hdptx_phy_dp_pll_init()
805 regmap_write(hdptx->regmap, 0x01c0, in rockchip_hdptx_phy_dp_pll_init()
807 regmap_write(hdptx->regmap, 0x01c4, in rockchip_hdptx_phy_dp_pll_init()
809 regmap_write(hdptx->regmap, 0x01c8, in rockchip_hdptx_phy_dp_pll_init()
811 regmap_update_bits(hdptx->regmap, 0x01d0, in rockchip_hdptx_phy_dp_pll_init()
815 regmap_update_bits(hdptx->regmap, 0x01dc, ANA_ROPLL_SSC_CLK_DIV_SEL, in rockchip_hdptx_phy_dp_pll_init()
817 regmap_update_bits(hdptx->regmap, 0x0118, in rockchip_hdptx_phy_dp_pll_init()
821 regmap_update_bits(hdptx->regmap, 0x011c, in rockchip_hdptx_phy_dp_pll_init()
826 regmap_update_bits(hdptx->regmap, 0x0204, ANA_PLL_CD_TX_SER_RATE_SEL, in rockchip_hdptx_phy_dp_pll_init()
828 regmap_update_bits(hdptx->regmap, 0x025c, DIG_CLK_SEL, in rockchip_hdptx_phy_dp_pll_init()
830 regmap_update_bits(hdptx->regmap, 0x021c, ANA_PLL_TX_HS_CLK_EN, in rockchip_hdptx_phy_dp_pll_init()
832 regmap_update_bits(hdptx->regmap, 0x0204, in rockchip_hdptx_phy_dp_pll_init()
836 regmap_update_bits(hdptx->regmap, 0x0264, CMN_ROPLL_ALONE_MODE, in rockchip_hdptx_phy_dp_pll_init()
838 regmap_update_bits(hdptx->regmap, 0x0208, ANA_PLL_CD_VREG_GAIN_CTRL, in rockchip_hdptx_phy_dp_pll_init()
840 regmap_update_bits(hdptx->regmap, 0x00f0, ANA_LCPLL_RESERVED7, in rockchip_hdptx_phy_dp_pll_init()
842 regmap_update_bits(hdptx->regmap, 0x020c, ANA_PLL_CD_VREG_ICTRL, in rockchip_hdptx_phy_dp_pll_init()
844 regmap_update_bits(hdptx->regmap, 0x0214, ANA_PLL_SYNC_LOSS_DET_MODE, in rockchip_hdptx_phy_dp_pll_init()
846 regmap_update_bits(hdptx->regmap, 0x0210, PLL_LCRO_CLK_SEL, in rockchip_hdptx_phy_dp_pll_init()
848 regmap_update_bits(hdptx->regmap, 0x0268, HS_SPEED_SEL, in rockchip_hdptx_phy_dp_pll_init()
850 regmap_update_bits(hdptx->regmap, 0x026c, LS_SPEED_SEL, in rockchip_hdptx_phy_dp_pll_init()
859 regmap_update_bits(hdptx->regmap, 0x0414, ANA_SB_TX_HLVL_PROG, in rockchip_hdptx_phy_dp_aux_init()
861 regmap_update_bits(hdptx->regmap, 0x0418, ANA_SB_TX_LLVL_PROG, in rockchip_hdptx_phy_dp_aux_init()
863 regmap_update_bits(hdptx->regmap, 0x044c, in rockchip_hdptx_phy_dp_aux_init()
867 regmap_update_bits(hdptx->regmap, 0x0450, in rockchip_hdptx_phy_dp_aux_init()
871 regmap_update_bits(hdptx->regmap, 0x0454, in rockchip_hdptx_phy_dp_aux_init()
875 regmap_update_bits(hdptx->regmap, 0x0458, in rockchip_hdptx_phy_dp_aux_init()
878 regmap_update_bits(hdptx->regmap, 0x045c, in rockchip_hdptx_phy_dp_aux_init()
881 regmap_update_bits(hdptx->regmap, 0x0460, in rockchip_hdptx_phy_dp_aux_init()
884 regmap_update_bits(hdptx->regmap, 0x0468, SB_TG_CNT_RUN_NO_7_0, in rockchip_hdptx_phy_dp_aux_init()
886 regmap_update_bits(hdptx->regmap, 0x046c, in rockchip_hdptx_phy_dp_aux_init()
890 regmap_update_bits(hdptx->regmap, 0x0470, SB_AFC_STB_NUM, in rockchip_hdptx_phy_dp_aux_init()
892 regmap_update_bits(hdptx->regmap, 0x0474, SB_TG_OSC_CNT_MIN, in rockchip_hdptx_phy_dp_aux_init()
894 regmap_update_bits(hdptx->regmap, 0x0478, SB_TG_OSC_CNT_MAX, in rockchip_hdptx_phy_dp_aux_init()
896 regmap_update_bits(hdptx->regmap, 0x047c, SB_PWM_AFC_CTRL, in rockchip_hdptx_phy_dp_aux_init()
898 regmap_update_bits(hdptx->regmap, 0x0434, ANA_SB_DMRX_LPBK_DATA, in rockchip_hdptx_phy_dp_aux_init()
900 regmap_update_bits(hdptx->regmap, 0x0440, in rockchip_hdptx_phy_dp_aux_init()
904 regmap_update_bits(hdptx->regmap, 0x043c, ANA_SB_VREG_GAIN_CTRL, in rockchip_hdptx_phy_dp_aux_init()
906 regmap_update_bits(hdptx->regmap, 0x0408, ANA_SB_RXTERM_OFFSP, in rockchip_hdptx_phy_dp_aux_init()
908 regmap_update_bits(hdptx->regmap, 0x040c, ANA_SB_RXTERM_OFFSN, in rockchip_hdptx_phy_dp_aux_init()
910 regmap_update_bits(hdptx->regmap, 0x047c, SB_RCAL_RSTN, in rockchip_hdptx_phy_dp_aux_init()
912 regmap_update_bits(hdptx->regmap, 0x0410, SB_AUX_EN, in rockchip_hdptx_phy_dp_aux_init()
914 regmap_update_bits(hdptx->regmap, 0x0480, SB_AUX_EN_IN, in rockchip_hdptx_phy_dp_aux_init()
916 regmap_update_bits(hdptx->regmap, 0x040c, OVRD_SB_RX_RESCAL_DONE, in rockchip_hdptx_phy_dp_aux_init()
918 regmap_update_bits(hdptx->regmap, 0x0410, OVRD_SB_EN, in rockchip_hdptx_phy_dp_aux_init()
920 regmap_update_bits(hdptx->regmap, 0x0408, OVRD_SB_RXTERM_EN, in rockchip_hdptx_phy_dp_aux_init()
922 regmap_update_bits(hdptx->regmap, 0x043c, OVRD_SB_VREG_EN, in rockchip_hdptx_phy_dp_aux_init()
924 regmap_update_bits(hdptx->regmap, 0x0410, OVRD_SB_AUX_EN, in rockchip_hdptx_phy_dp_aux_init()
927 rockchip_grf_write(hdptx->grf, HDPTXPHY_GRF_CON0, BGR_EN, in rockchip_hdptx_phy_dp_aux_init()
929 rockchip_grf_write(hdptx->grf, HDPTXPHY_GRF_CON0, BIAS_EN, in rockchip_hdptx_phy_dp_aux_init()
932 reset_deassert(&hdptx->init_reset); in rockchip_hdptx_phy_dp_aux_init()
934 reset_deassert(&hdptx->cmn_reset); in rockchip_hdptx_phy_dp_aux_init()
937 regmap_update_bits(hdptx->regmap, 0x040c, SB_RX_RESCAL_DONE, in rockchip_hdptx_phy_dp_aux_init()
940 regmap_update_bits(hdptx->regmap, 0x0410, SB_EN, in rockchip_hdptx_phy_dp_aux_init()
943 regmap_update_bits(hdptx->regmap, 0x0408, SB_RXRERM_EN, in rockchip_hdptx_phy_dp_aux_init()
946 regmap_update_bits(hdptx->regmap, 0x043c, SB_VREG_EN, in rockchip_hdptx_phy_dp_aux_init()
949 regmap_update_bits(hdptx->regmap, 0x0410, SB_AUX_EN, in rockchip_hdptx_phy_dp_aux_init()
953 ret = regmap_read_poll_timeout(hdptx->grf, HDPTXPHY_GRF_STATUS0, in rockchip_hdptx_phy_dp_aux_init()
957 dev_err(hdptx->dev, "timeout waiting for sb_rdy\n"); in rockchip_hdptx_phy_dp_aux_init()
966 u32 lane; in rockchip_hdptx_phy_reset() local
968 reset_assert(&hdptx->lane_reset); in rockchip_hdptx_phy_reset()
969 reset_assert(&hdptx->cmn_reset); in rockchip_hdptx_phy_reset()
970 reset_assert(&hdptx->init_reset); in rockchip_hdptx_phy_reset()
972 reset_assert(&hdptx->apb_reset); in rockchip_hdptx_phy_reset()
974 reset_deassert(&hdptx->apb_reset); in rockchip_hdptx_phy_reset()
976 for (lane = 0; lane < 4; lane++) in rockchip_hdptx_phy_reset()
977 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c04), in rockchip_hdptx_phy_reset()
982 rockchip_grf_write(hdptx->grf, HDPTXPHY_GRF_CON0, PLL_EN, in rockchip_hdptx_phy_reset()
984 rockchip_grf_write(hdptx->grf, HDPTXPHY_GRF_CON0, BIAS_EN, in rockchip_hdptx_phy_reset()
986 rockchip_grf_write(hdptx->grf, HDPTXPHY_GRF_CON0, BGR_EN, in rockchip_hdptx_phy_reset()
992 struct rockchip_hdptx_phy *hdptx = dev_get_priv(phy->dev); in rockchip_hdptx_phy_power_on()
994 u32 lane; in rockchip_hdptx_phy_power_on() local
998 for (lane = 0; lane < 4; lane++) { in rockchip_hdptx_phy_power_on()
999 u32 invert = hdptx->lane_polarity_invert[lane]; in rockchip_hdptx_phy_power_on()
1001 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c78), in rockchip_hdptx_phy_power_on()
1007 rockchip_grf_write(hdptx->grf, HDPTXPHY_GRF_CON0, in rockchip_hdptx_phy_power_on()
1011 regmap_update_bits(hdptx->regmap, 0x0800, PROTOCOL_SEL, in rockchip_hdptx_phy_power_on()
1013 regmap_update_bits(hdptx->regmap, 0x0818, DATA_BUS_WIDTH, in rockchip_hdptx_phy_power_on()
1015 regmap_update_bits(hdptx->regmap, 0x0818, BUS_WIDTH_SEL, in rockchip_hdptx_phy_power_on()
1021 rockchip_grf_write(hdptx->grf, HDPTXPHY_GRF_CON0, in rockchip_hdptx_phy_power_on()
1025 regmap_update_bits(hdptx->regmap, 0x0800, PROTOCOL_SEL, in rockchip_hdptx_phy_power_on()
1034 struct rockchip_hdptx_phy *hdptx = dev_get_priv(phy->dev); in rockchip_hdptx_phy_power_off()
1052 u32 prop[4]; in rockchip_hdptx_phy_probe()
1055 ret = regmap_init_mem(dev, &hdptx->regmap); in rockchip_hdptx_phy_probe()
1064 hdptx->grf = syscon_get_regmap(syscon); in rockchip_hdptx_phy_probe()
1065 if (IS_ERR(hdptx->grf)) { in rockchip_hdptx_phy_probe()
1066 ret = PTR_ERR(hdptx->grf); in rockchip_hdptx_phy_probe()
1071 hdptx->dev = dev; in rockchip_hdptx_phy_probe()
1073 ret = reset_get_by_name(dev, "apb", &hdptx->apb_reset); in rockchip_hdptx_phy_probe()
1079 ret = reset_get_by_name(dev, "init", &hdptx->init_reset); in rockchip_hdptx_phy_probe()
1085 ret = reset_get_by_name(dev, "cmn", &hdptx->cmn_reset); in rockchip_hdptx_phy_probe()
1091 ret = reset_get_by_name(dev, "lane", &hdptx->lane_reset); in rockchip_hdptx_phy_probe()
1093 dev_err(dev, "failed to get lane reset: %d\n", ret); in rockchip_hdptx_phy_probe()
1103 if (!dev_read_u32_array(dev, "lane-polarity-invert", prop, ARRAY_SIZE(prop))) { in rockchip_hdptx_phy_probe()
1104 hdptx->lane_polarity_invert[0] = prop[0]; in rockchip_hdptx_phy_probe()
1105 hdptx->lane_polarity_invert[1] = prop[1]; in rockchip_hdptx_phy_probe()
1106 hdptx->lane_polarity_invert[2] = prop[2]; in rockchip_hdptx_phy_probe()
1107 hdptx->lane_polarity_invert[3] = prop[3]; in rockchip_hdptx_phy_probe()
1114 { .compatible = "rockchip,rk3588-hdptx-phy", },