1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright © 2009 Keith Packard
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Permission to use, copy, modify, distribute, and sell this software and its
6*4882a593Smuzhiyun * documentation for any purpose is hereby granted without fee, provided that
7*4882a593Smuzhiyun * the above copyright notice appear in all copies and that both that copyright
8*4882a593Smuzhiyun * notice and this permission notice appear in supporting documentation, and
9*4882a593Smuzhiyun * that the name of the copyright holders not be used in advertising or
10*4882a593Smuzhiyun * publicity pertaining to distribution of the software without specific,
11*4882a593Smuzhiyun * written prior permission. The copyright holders make no representations
12*4882a593Smuzhiyun * about the suitability of this software for any purpose. It is provided "as
13*4882a593Smuzhiyun * is" without express or implied warranty.
14*4882a593Smuzhiyun *
15*4882a593Smuzhiyun * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
16*4882a593Smuzhiyun * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
17*4882a593Smuzhiyun * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
18*4882a593Smuzhiyun * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
19*4882a593Smuzhiyun * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
20*4882a593Smuzhiyun * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
21*4882a593Smuzhiyun * OF THIS SOFTWARE.
22*4882a593Smuzhiyun */
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun #include <common.h>
25*4882a593Smuzhiyun #include <drm/drm_dp_helper.h>
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun /**
28*4882a593Smuzhiyun * DOC: dp helpers
29*4882a593Smuzhiyun *
30*4882a593Smuzhiyun * These functions contain some common logic and helpers at various abstraction
31*4882a593Smuzhiyun * levels to deal with Display Port sink devices and related things like DP aux
32*4882a593Smuzhiyun * channel transfers, EDID reading over DP aux channels, decoding certain DPCD
33*4882a593Smuzhiyun * blocks, ...
34*4882a593Smuzhiyun */
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun /* Helpers for DP link training */
dp_link_status(const u8 link_status[DP_LINK_STATUS_SIZE],int r)37*4882a593Smuzhiyun static u8 dp_link_status(const u8 link_status[DP_LINK_STATUS_SIZE], int r)
38*4882a593Smuzhiyun {
39*4882a593Smuzhiyun return link_status[r - DP_LANE0_1_STATUS];
40*4882a593Smuzhiyun }
41*4882a593Smuzhiyun
dp_get_lane_status(const u8 link_status[DP_LINK_STATUS_SIZE],int lane)42*4882a593Smuzhiyun static u8 dp_get_lane_status(const u8 link_status[DP_LINK_STATUS_SIZE],
43*4882a593Smuzhiyun int lane)
44*4882a593Smuzhiyun {
45*4882a593Smuzhiyun int i = DP_LANE0_1_STATUS + (lane >> 1);
46*4882a593Smuzhiyun int s = (lane & 1) * 4;
47*4882a593Smuzhiyun u8 l = dp_link_status(link_status, i);
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun return (l >> s) & 0xf;
50*4882a593Smuzhiyun }
51*4882a593Smuzhiyun
drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],int lane_count)52*4882a593Smuzhiyun bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
53*4882a593Smuzhiyun int lane_count)
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun u8 lane_align;
56*4882a593Smuzhiyun u8 lane_status;
57*4882a593Smuzhiyun int lane;
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun lane_align = dp_link_status(link_status,
60*4882a593Smuzhiyun DP_LANE_ALIGN_STATUS_UPDATED);
61*4882a593Smuzhiyun if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
62*4882a593Smuzhiyun return false;
63*4882a593Smuzhiyun for (lane = 0; lane < lane_count; lane++) {
64*4882a593Smuzhiyun lane_status = dp_get_lane_status(link_status, lane);
65*4882a593Smuzhiyun if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS)
66*4882a593Smuzhiyun return false;
67*4882a593Smuzhiyun }
68*4882a593Smuzhiyun return true;
69*4882a593Smuzhiyun }
70*4882a593Smuzhiyun
drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],int lane_count)71*4882a593Smuzhiyun bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
72*4882a593Smuzhiyun int lane_count)
73*4882a593Smuzhiyun {
74*4882a593Smuzhiyun int lane;
75*4882a593Smuzhiyun u8 lane_status;
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun for (lane = 0; lane < lane_count; lane++) {
78*4882a593Smuzhiyun lane_status = dp_get_lane_status(link_status, lane);
79*4882a593Smuzhiyun if ((lane_status & DP_LANE_CR_DONE) == 0)
80*4882a593Smuzhiyun return false;
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun return true;
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun
drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],int lane)85*4882a593Smuzhiyun u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],
86*4882a593Smuzhiyun int lane)
87*4882a593Smuzhiyun {
88*4882a593Smuzhiyun int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
89*4882a593Smuzhiyun int s = ((lane & 1) ?
90*4882a593Smuzhiyun DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
91*4882a593Smuzhiyun DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
92*4882a593Smuzhiyun u8 l = dp_link_status(link_status, i);
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
95*4882a593Smuzhiyun }
96*4882a593Smuzhiyun
drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],int lane)97*4882a593Smuzhiyun u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],
98*4882a593Smuzhiyun int lane)
99*4882a593Smuzhiyun {
100*4882a593Smuzhiyun int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
101*4882a593Smuzhiyun int s = ((lane & 1) ?
102*4882a593Smuzhiyun DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
103*4882a593Smuzhiyun DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
104*4882a593Smuzhiyun u8 l = dp_link_status(link_status, i);
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
107*4882a593Smuzhiyun }
108*4882a593Smuzhiyun
drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE])109*4882a593Smuzhiyun void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
110*4882a593Smuzhiyun {
111*4882a593Smuzhiyun int rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
112*4882a593Smuzhiyun DP_TRAINING_AUX_RD_MASK;
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun if (rd_interval > 4)
115*4882a593Smuzhiyun printf("AUX interval %d, out of range (max 4)\n", rd_interval);
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun if (rd_interval == 0 || dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)
118*4882a593Smuzhiyun udelay(100);
119*4882a593Smuzhiyun else
120*4882a593Smuzhiyun mdelay(rd_interval * 4);
121*4882a593Smuzhiyun }
122*4882a593Smuzhiyun
drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE])123*4882a593Smuzhiyun void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
124*4882a593Smuzhiyun {
125*4882a593Smuzhiyun int rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
126*4882a593Smuzhiyun DP_TRAINING_AUX_RD_MASK;
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun if (rd_interval > 4)
129*4882a593Smuzhiyun printf("AUX interval %d, out of range (max 4)\n", rd_interval);
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun if (rd_interval == 0)
132*4882a593Smuzhiyun udelay(400);
133*4882a593Smuzhiyun else
134*4882a593Smuzhiyun mdelay(rd_interval * 4);
135*4882a593Smuzhiyun }
136*4882a593Smuzhiyun
drm_dp_link_rate_to_bw_code(int link_rate)137*4882a593Smuzhiyun u8 drm_dp_link_rate_to_bw_code(int link_rate)
138*4882a593Smuzhiyun {
139*4882a593Smuzhiyun switch (link_rate) {
140*4882a593Smuzhiyun default:
141*4882a593Smuzhiyun WARN(1, "unknown DP link rate %d, using %x\n", link_rate,
142*4882a593Smuzhiyun DP_LINK_BW_1_62);
143*4882a593Smuzhiyun case 162000:
144*4882a593Smuzhiyun return DP_LINK_BW_1_62;
145*4882a593Smuzhiyun case 270000:
146*4882a593Smuzhiyun return DP_LINK_BW_2_7;
147*4882a593Smuzhiyun case 540000:
148*4882a593Smuzhiyun return DP_LINK_BW_5_4;
149*4882a593Smuzhiyun case 810000:
150*4882a593Smuzhiyun return DP_LINK_BW_8_1;
151*4882a593Smuzhiyun }
152*4882a593Smuzhiyun }
153*4882a593Smuzhiyun
drm_dp_bw_code_to_link_rate(u8 link_bw)154*4882a593Smuzhiyun int drm_dp_bw_code_to_link_rate(u8 link_bw)
155*4882a593Smuzhiyun {
156*4882a593Smuzhiyun switch (link_bw) {
157*4882a593Smuzhiyun default:
158*4882a593Smuzhiyun WARN(1, "unknown DP link BW code %x, using 162000\n", link_bw);
159*4882a593Smuzhiyun case DP_LINK_BW_1_62:
160*4882a593Smuzhiyun return 162000;
161*4882a593Smuzhiyun case DP_LINK_BW_2_7:
162*4882a593Smuzhiyun return 270000;
163*4882a593Smuzhiyun case DP_LINK_BW_5_4:
164*4882a593Smuzhiyun return 540000;
165*4882a593Smuzhiyun case DP_LINK_BW_8_1:
166*4882a593Smuzhiyun return 810000;
167*4882a593Smuzhiyun }
168*4882a593Smuzhiyun }
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun #define AUX_RETRY_INTERVAL 500 /* us */
171*4882a593Smuzhiyun
drm_dp_dpcd_access(struct drm_dp_aux * aux,u8 request,unsigned int offset,void * buffer,size_t size)172*4882a593Smuzhiyun static int drm_dp_dpcd_access(struct drm_dp_aux *aux, u8 request,
173*4882a593Smuzhiyun unsigned int offset, void *buffer, size_t size)
174*4882a593Smuzhiyun {
175*4882a593Smuzhiyun struct drm_dp_aux_msg msg;
176*4882a593Smuzhiyun unsigned int retry, native_reply;
177*4882a593Smuzhiyun int err = 0, ret = 0;
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun memset(&msg, 0, sizeof(msg));
180*4882a593Smuzhiyun msg.address = offset;
181*4882a593Smuzhiyun msg.request = request;
182*4882a593Smuzhiyun msg.buffer = buffer;
183*4882a593Smuzhiyun msg.size = size;
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun /*
186*4882a593Smuzhiyun * The specification doesn't give any recommendation on how often to
187*4882a593Smuzhiyun * retry native transactions. We used to retry 7 times like for
188*4882a593Smuzhiyun * aux i2c transactions but real world devices this wasn't
189*4882a593Smuzhiyun * sufficient, bump to 32 which makes Dell 4k monitors happier.
190*4882a593Smuzhiyun */
191*4882a593Smuzhiyun for (retry = 0; retry < 32; retry++) {
192*4882a593Smuzhiyun if (ret != 0 && ret != -ETIMEDOUT)
193*4882a593Smuzhiyun udelay(AUX_RETRY_INTERVAL);
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun ret = aux->transfer(aux, &msg);
196*4882a593Smuzhiyun if (ret >= 0) {
197*4882a593Smuzhiyun native_reply = msg.reply & DP_AUX_NATIVE_REPLY_MASK;
198*4882a593Smuzhiyun if (native_reply == DP_AUX_NATIVE_REPLY_ACK) {
199*4882a593Smuzhiyun if (ret == size)
200*4882a593Smuzhiyun goto out;
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun ret = -EPROTO;
203*4882a593Smuzhiyun } else {
204*4882a593Smuzhiyun ret = -EIO;
205*4882a593Smuzhiyun }
206*4882a593Smuzhiyun }
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun /*
209*4882a593Smuzhiyun * We want the error we return to be the error we received on
210*4882a593Smuzhiyun * the first transaction, since we may get a different error the
211*4882a593Smuzhiyun * next time we retry
212*4882a593Smuzhiyun */
213*4882a593Smuzhiyun if (!err)
214*4882a593Smuzhiyun err = ret;
215*4882a593Smuzhiyun }
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun printf("%s: Too many retries, giving up. First error: %d\n",
218*4882a593Smuzhiyun aux->name, err);
219*4882a593Smuzhiyun ret = err;
220*4882a593Smuzhiyun
221*4882a593Smuzhiyun out:
222*4882a593Smuzhiyun return ret;
223*4882a593Smuzhiyun }
224*4882a593Smuzhiyun
drm_dp_dpcd_read(struct drm_dp_aux * aux,unsigned int offset,void * buffer,size_t size)225*4882a593Smuzhiyun ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset,
226*4882a593Smuzhiyun void *buffer, size_t size)
227*4882a593Smuzhiyun {
228*4882a593Smuzhiyun int ret;
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, DP_DPCD_REV,
231*4882a593Smuzhiyun buffer, 1);
232*4882a593Smuzhiyun if (ret != 1)
233*4882a593Smuzhiyun goto out;
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, offset,
236*4882a593Smuzhiyun buffer, size);
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun out:
239*4882a593Smuzhiyun return ret;
240*4882a593Smuzhiyun }
241*4882a593Smuzhiyun
drm_dp_dpcd_write(struct drm_dp_aux * aux,unsigned int offset,void * buffer,size_t size)242*4882a593Smuzhiyun ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset,
243*4882a593Smuzhiyun void *buffer, size_t size)
244*4882a593Smuzhiyun {
245*4882a593Smuzhiyun int ret;
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_WRITE, offset,
248*4882a593Smuzhiyun buffer, size);
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun return ret;
251*4882a593Smuzhiyun }
252*4882a593Smuzhiyun
drm_dp_dpcd_read_link_status(struct drm_dp_aux * aux,u8 status[DP_LINK_STATUS_SIZE])253*4882a593Smuzhiyun int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
254*4882a593Smuzhiyun u8 status[DP_LINK_STATUS_SIZE])
255*4882a593Smuzhiyun {
256*4882a593Smuzhiyun return drm_dp_dpcd_read(aux, DP_LANE0_1_STATUS, status,
257*4882a593Smuzhiyun DP_LINK_STATUS_SIZE);
258*4882a593Smuzhiyun }
259*4882a593Smuzhiyun
drm_dp_read_extended_dpcd_caps(struct drm_dp_aux * aux,u8 dpcd[DP_RECEIVER_CAP_SIZE])260*4882a593Smuzhiyun static int drm_dp_read_extended_dpcd_caps(struct drm_dp_aux *aux,
261*4882a593Smuzhiyun u8 dpcd[DP_RECEIVER_CAP_SIZE])
262*4882a593Smuzhiyun {
263*4882a593Smuzhiyun u8 dpcd_ext[6];
264*4882a593Smuzhiyun int ret;
265*4882a593Smuzhiyun
266*4882a593Smuzhiyun /*
267*4882a593Smuzhiyun * Prior to DP1.3 the bit represented by
268*4882a593Smuzhiyun * DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT was reserved.
269*4882a593Smuzhiyun * If it is set DP_DPCD_REV at 0000h could be at a value less than
270*4882a593Smuzhiyun * the true capability of the panel. The only way to check is to
271*4882a593Smuzhiyun * then compare 0000h and 2200h.
272*4882a593Smuzhiyun */
273*4882a593Smuzhiyun if (!(dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
274*4882a593Smuzhiyun DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT))
275*4882a593Smuzhiyun return 0;
276*4882a593Smuzhiyun
277*4882a593Smuzhiyun ret = drm_dp_dpcd_read(aux, DP_DP13_DPCD_REV, &dpcd_ext,
278*4882a593Smuzhiyun sizeof(dpcd_ext));
279*4882a593Smuzhiyun if (ret < 0)
280*4882a593Smuzhiyun return ret;
281*4882a593Smuzhiyun if (ret != sizeof(dpcd_ext))
282*4882a593Smuzhiyun return -EIO;
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun if (dpcd[DP_DPCD_REV] > dpcd_ext[DP_DPCD_REV]) {
285*4882a593Smuzhiyun printf("%s: Extended DPCD rev less than base DPCD rev (%d > %d)\n",
286*4882a593Smuzhiyun aux->name, dpcd[DP_DPCD_REV], dpcd_ext[DP_DPCD_REV]);
287*4882a593Smuzhiyun return 0;
288*4882a593Smuzhiyun }
289*4882a593Smuzhiyun
290*4882a593Smuzhiyun if (!memcmp(dpcd, dpcd_ext, sizeof(dpcd_ext)))
291*4882a593Smuzhiyun return 0;
292*4882a593Smuzhiyun
293*4882a593Smuzhiyun debug("%s: Base DPCD: %*ph\n",
294*4882a593Smuzhiyun aux->name, DP_RECEIVER_CAP_SIZE, dpcd);
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun memcpy(dpcd, dpcd_ext, sizeof(dpcd_ext));
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun return 0;
299*4882a593Smuzhiyun }
300*4882a593Smuzhiyun
drm_dp_read_dpcd_caps(struct drm_dp_aux * aux,u8 dpcd[DP_RECEIVER_CAP_SIZE])301*4882a593Smuzhiyun int drm_dp_read_dpcd_caps(struct drm_dp_aux *aux,
302*4882a593Smuzhiyun u8 dpcd[DP_RECEIVER_CAP_SIZE])
303*4882a593Smuzhiyun {
304*4882a593Smuzhiyun int ret;
305*4882a593Smuzhiyun
306*4882a593Smuzhiyun ret = drm_dp_dpcd_read(aux, DP_DPCD_REV, dpcd, DP_RECEIVER_CAP_SIZE);
307*4882a593Smuzhiyun if (ret < 0)
308*4882a593Smuzhiyun return ret;
309*4882a593Smuzhiyun if (ret != DP_RECEIVER_CAP_SIZE || dpcd[DP_DPCD_REV] == 0)
310*4882a593Smuzhiyun return -EIO;
311*4882a593Smuzhiyun
312*4882a593Smuzhiyun ret = drm_dp_read_extended_dpcd_caps(aux, dpcd);
313*4882a593Smuzhiyun if (ret < 0)
314*4882a593Smuzhiyun return ret;
315*4882a593Smuzhiyun
316*4882a593Smuzhiyun debug("%s: DPCD: %*ph\n",
317*4882a593Smuzhiyun aux->name, DP_RECEIVER_CAP_SIZE, dpcd);
318*4882a593Smuzhiyun
319*4882a593Smuzhiyun return ret;
320*4882a593Smuzhiyun }
321*4882a593Smuzhiyun
drm_dp_i2c_msg_write_status_update(struct drm_dp_aux_msg * msg)322*4882a593Smuzhiyun static void drm_dp_i2c_msg_write_status_update(struct drm_dp_aux_msg *msg)
323*4882a593Smuzhiyun {
324*4882a593Smuzhiyun /*
325*4882a593Smuzhiyun * In case of i2c defer or short i2c ack reply to a write,
326*4882a593Smuzhiyun * we need to switch to WRITE_STATUS_UPDATE to drain the
327*4882a593Smuzhiyun * rest of the message
328*4882a593Smuzhiyun */
329*4882a593Smuzhiyun if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_I2C_WRITE) {
330*4882a593Smuzhiyun msg->request &= DP_AUX_I2C_MOT;
331*4882a593Smuzhiyun msg->request |= DP_AUX_I2C_WRITE_STATUS_UPDATE;
332*4882a593Smuzhiyun }
333*4882a593Smuzhiyun }
334*4882a593Smuzhiyun
drm_dp_i2c_do_msg(struct drm_dp_aux * aux,struct drm_dp_aux_msg * msg)335*4882a593Smuzhiyun static int drm_dp_i2c_do_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
336*4882a593Smuzhiyun {
337*4882a593Smuzhiyun unsigned int retry, defer_i2c;
338*4882a593Smuzhiyun int ret;
339*4882a593Smuzhiyun /*
340*4882a593Smuzhiyun * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device
341*4882a593Smuzhiyun * is required to retry at least seven times upon receiving AUX_DEFER
342*4882a593Smuzhiyun * before giving up the AUX transaction.
343*4882a593Smuzhiyun *
344*4882a593Smuzhiyun * We also try to account for the i2c bus speed.
345*4882a593Smuzhiyun */
346*4882a593Smuzhiyun int max_retries = 7;
347*4882a593Smuzhiyun
348*4882a593Smuzhiyun for (retry = 0, defer_i2c = 0; retry < (max_retries + defer_i2c);
349*4882a593Smuzhiyun retry++) {
350*4882a593Smuzhiyun ret = aux->transfer(aux, msg);
351*4882a593Smuzhiyun if (ret < 0) {
352*4882a593Smuzhiyun if (ret == -EBUSY)
353*4882a593Smuzhiyun continue;
354*4882a593Smuzhiyun
355*4882a593Smuzhiyun /*
356*4882a593Smuzhiyun * While timeouts can be errors, they're usually normal
357*4882a593Smuzhiyun * behavior (for instance, when a driver tries to
358*4882a593Smuzhiyun * communicate with a non-existent DisplayPort device).
359*4882a593Smuzhiyun * Avoid spamming the kernel log with timeout errors.
360*4882a593Smuzhiyun */
361*4882a593Smuzhiyun if (ret == -ETIMEDOUT)
362*4882a593Smuzhiyun printf("%s: transaction timed out\n",
363*4882a593Smuzhiyun aux->name);
364*4882a593Smuzhiyun else
365*4882a593Smuzhiyun printf("%s: transaction failed: %d\n",
366*4882a593Smuzhiyun aux->name, ret);
367*4882a593Smuzhiyun return ret;
368*4882a593Smuzhiyun }
369*4882a593Smuzhiyun
370*4882a593Smuzhiyun switch (msg->reply & DP_AUX_NATIVE_REPLY_MASK) {
371*4882a593Smuzhiyun case DP_AUX_NATIVE_REPLY_ACK:
372*4882a593Smuzhiyun /*
373*4882a593Smuzhiyun * For I2C-over-AUX transactions this isn't enough, we
374*4882a593Smuzhiyun * need to check for the I2C ACK reply.
375*4882a593Smuzhiyun */
376*4882a593Smuzhiyun break;
377*4882a593Smuzhiyun
378*4882a593Smuzhiyun case DP_AUX_NATIVE_REPLY_NACK:
379*4882a593Smuzhiyun printf("%s: native nack (result=%d, size=%zu)\n",
380*4882a593Smuzhiyun aux->name, ret, msg->size);
381*4882a593Smuzhiyun return -EREMOTEIO;
382*4882a593Smuzhiyun
383*4882a593Smuzhiyun case DP_AUX_NATIVE_REPLY_DEFER:
384*4882a593Smuzhiyun printf("%s: native defer\n", aux->name);
385*4882a593Smuzhiyun /*
386*4882a593Smuzhiyun * We could check for I2C bit rate capabilities and if
387*4882a593Smuzhiyun * available adjust this interval. We could also be
388*4882a593Smuzhiyun * more careful with DP-to-legacy adapters where a
389*4882a593Smuzhiyun * long legacy cable may force very low I2C bit rates.
390*4882a593Smuzhiyun *
391*4882a593Smuzhiyun * For now just defer for long enough to hopefully be
392*4882a593Smuzhiyun * safe for all use-cases.
393*4882a593Smuzhiyun */
394*4882a593Smuzhiyun udelay(AUX_RETRY_INTERVAL);
395*4882a593Smuzhiyun continue;
396*4882a593Smuzhiyun
397*4882a593Smuzhiyun default:
398*4882a593Smuzhiyun printf("%s: invalid native reply %#04x\n",
399*4882a593Smuzhiyun aux->name, msg->reply);
400*4882a593Smuzhiyun return -EREMOTEIO;
401*4882a593Smuzhiyun }
402*4882a593Smuzhiyun
403*4882a593Smuzhiyun switch (msg->reply & DP_AUX_I2C_REPLY_MASK) {
404*4882a593Smuzhiyun case DP_AUX_I2C_REPLY_ACK:
405*4882a593Smuzhiyun /*
406*4882a593Smuzhiyun * Both native ACK and I2C ACK replies received. We
407*4882a593Smuzhiyun * can assume the transfer was successful.
408*4882a593Smuzhiyun */
409*4882a593Smuzhiyun if (ret != msg->size)
410*4882a593Smuzhiyun drm_dp_i2c_msg_write_status_update(msg);
411*4882a593Smuzhiyun return ret;
412*4882a593Smuzhiyun
413*4882a593Smuzhiyun case DP_AUX_I2C_REPLY_NACK:
414*4882a593Smuzhiyun printf("%s: I2C nack (result=%d, size=%zu)\n",
415*4882a593Smuzhiyun aux->name, ret, msg->size);
416*4882a593Smuzhiyun aux->i2c_nack_count++;
417*4882a593Smuzhiyun return -EREMOTEIO;
418*4882a593Smuzhiyun
419*4882a593Smuzhiyun case DP_AUX_I2C_REPLY_DEFER:
420*4882a593Smuzhiyun printf("%s: I2C defer\n", aux->name);
421*4882a593Smuzhiyun /* DP Compliance Test 4.2.2.5 Requirement:
422*4882a593Smuzhiyun * Must have at least 7 retries for I2C defers on the
423*4882a593Smuzhiyun * transaction to pass this test
424*4882a593Smuzhiyun */
425*4882a593Smuzhiyun aux->i2c_defer_count++;
426*4882a593Smuzhiyun if (defer_i2c < 7)
427*4882a593Smuzhiyun defer_i2c++;
428*4882a593Smuzhiyun udelay(AUX_RETRY_INTERVAL);
429*4882a593Smuzhiyun drm_dp_i2c_msg_write_status_update(msg);
430*4882a593Smuzhiyun
431*4882a593Smuzhiyun continue;
432*4882a593Smuzhiyun
433*4882a593Smuzhiyun default:
434*4882a593Smuzhiyun printf("%s: invalid I2C reply %#04x\n",
435*4882a593Smuzhiyun aux->name, msg->reply);
436*4882a593Smuzhiyun return -EREMOTEIO;
437*4882a593Smuzhiyun }
438*4882a593Smuzhiyun }
439*4882a593Smuzhiyun
440*4882a593Smuzhiyun printf("%s: Too many retries, giving up\n", aux->name);
441*4882a593Smuzhiyun return -EREMOTEIO;
442*4882a593Smuzhiyun }
443*4882a593Smuzhiyun
drm_dp_i2c_msg_set_request(struct drm_dp_aux_msg * msg,const struct i2c_msg * i2c_msg)444*4882a593Smuzhiyun static void drm_dp_i2c_msg_set_request(struct drm_dp_aux_msg *msg,
445*4882a593Smuzhiyun const struct i2c_msg *i2c_msg)
446*4882a593Smuzhiyun {
447*4882a593Smuzhiyun msg->request = (i2c_msg->flags & I2C_M_RD) ?
448*4882a593Smuzhiyun DP_AUX_I2C_READ : DP_AUX_I2C_WRITE;
449*4882a593Smuzhiyun if (!(i2c_msg->flags & I2C_M_STOP))
450*4882a593Smuzhiyun msg->request |= DP_AUX_I2C_MOT;
451*4882a593Smuzhiyun }
452*4882a593Smuzhiyun
453*4882a593Smuzhiyun /*
454*4882a593Smuzhiyun * Keep retrying drm_dp_i2c_do_msg until all data has been transferred.
455*4882a593Smuzhiyun *
456*4882a593Smuzhiyun * Returns an error code on failure, or a recommended transfer size on success.
457*4882a593Smuzhiyun */
drm_dp_i2c_drain_msg(struct drm_dp_aux * aux,struct drm_dp_aux_msg * orig_msg)458*4882a593Smuzhiyun static int drm_dp_i2c_drain_msg(struct drm_dp_aux *aux,
459*4882a593Smuzhiyun struct drm_dp_aux_msg *orig_msg)
460*4882a593Smuzhiyun {
461*4882a593Smuzhiyun int err, ret = orig_msg->size;
462*4882a593Smuzhiyun struct drm_dp_aux_msg msg = *orig_msg;
463*4882a593Smuzhiyun
464*4882a593Smuzhiyun while (msg.size > 0) {
465*4882a593Smuzhiyun err = drm_dp_i2c_do_msg(aux, &msg);
466*4882a593Smuzhiyun if (err <= 0)
467*4882a593Smuzhiyun return err == 0 ? -EPROTO : err;
468*4882a593Smuzhiyun
469*4882a593Smuzhiyun if (err < msg.size && err < ret) {
470*4882a593Smuzhiyun printf("%s: Reply: requested %zu bytes got %d bytes\n",
471*4882a593Smuzhiyun aux->name, msg.size, err);
472*4882a593Smuzhiyun ret = err;
473*4882a593Smuzhiyun }
474*4882a593Smuzhiyun
475*4882a593Smuzhiyun msg.size -= err;
476*4882a593Smuzhiyun msg.buffer += err;
477*4882a593Smuzhiyun }
478*4882a593Smuzhiyun
479*4882a593Smuzhiyun return ret;
480*4882a593Smuzhiyun }
481*4882a593Smuzhiyun
drm_dp_i2c_xfer(struct ddc_adapter * adapter,struct i2c_msg * msgs,int num)482*4882a593Smuzhiyun int drm_dp_i2c_xfer(struct ddc_adapter *adapter, struct i2c_msg *msgs,
483*4882a593Smuzhiyun int num)
484*4882a593Smuzhiyun {
485*4882a593Smuzhiyun struct drm_dp_aux *aux = container_of(adapter, struct drm_dp_aux, ddc);
486*4882a593Smuzhiyun unsigned int i, j;
487*4882a593Smuzhiyun unsigned int transfer_size;
488*4882a593Smuzhiyun struct drm_dp_aux_msg msg;
489*4882a593Smuzhiyun int err = 0;
490*4882a593Smuzhiyun
491*4882a593Smuzhiyun memset(&msg, 0, sizeof(msg));
492*4882a593Smuzhiyun
493*4882a593Smuzhiyun for (i = 0; i < num; i++) {
494*4882a593Smuzhiyun msg.address = msgs[i].addr;
495*4882a593Smuzhiyun drm_dp_i2c_msg_set_request(&msg, &msgs[i]);
496*4882a593Smuzhiyun /* Send a bare address packet to start the transaction.
497*4882a593Smuzhiyun * Zero sized messages specify an address only (bare
498*4882a593Smuzhiyun * address) transaction.
499*4882a593Smuzhiyun */
500*4882a593Smuzhiyun msg.buffer = NULL;
501*4882a593Smuzhiyun msg.size = 0;
502*4882a593Smuzhiyun err = drm_dp_i2c_do_msg(aux, &msg);
503*4882a593Smuzhiyun
504*4882a593Smuzhiyun /*
505*4882a593Smuzhiyun * Reset msg.request in case in case it got
506*4882a593Smuzhiyun * changed into a WRITE_STATUS_UPDATE.
507*4882a593Smuzhiyun */
508*4882a593Smuzhiyun drm_dp_i2c_msg_set_request(&msg, &msgs[i]);
509*4882a593Smuzhiyun
510*4882a593Smuzhiyun if (err < 0)
511*4882a593Smuzhiyun break;
512*4882a593Smuzhiyun /* We want each transaction to be as large as possible, but
513*4882a593Smuzhiyun * we'll go to smaller sizes if the hardware gives us a
514*4882a593Smuzhiyun * short reply.
515*4882a593Smuzhiyun */
516*4882a593Smuzhiyun transfer_size = DP_AUX_MAX_PAYLOAD_BYTES;
517*4882a593Smuzhiyun for (j = 0; j < msgs[i].len; j += msg.size) {
518*4882a593Smuzhiyun msg.buffer = msgs[i].buf + j;
519*4882a593Smuzhiyun msg.size = min(transfer_size, msgs[i].len - j);
520*4882a593Smuzhiyun
521*4882a593Smuzhiyun err = drm_dp_i2c_drain_msg(aux, &msg);
522*4882a593Smuzhiyun
523*4882a593Smuzhiyun /*
524*4882a593Smuzhiyun * Reset msg.request in case in case it got
525*4882a593Smuzhiyun * changed into a WRITE_STATUS_UPDATE.
526*4882a593Smuzhiyun */
527*4882a593Smuzhiyun drm_dp_i2c_msg_set_request(&msg, &msgs[i]);
528*4882a593Smuzhiyun
529*4882a593Smuzhiyun if (err < 0)
530*4882a593Smuzhiyun break;
531*4882a593Smuzhiyun transfer_size = err;
532*4882a593Smuzhiyun }
533*4882a593Smuzhiyun if (err < 0)
534*4882a593Smuzhiyun break;
535*4882a593Smuzhiyun }
536*4882a593Smuzhiyun if (err >= 0)
537*4882a593Smuzhiyun err = num;
538*4882a593Smuzhiyun /* Send a bare address packet to close out the transaction.
539*4882a593Smuzhiyun * Zero sized messages specify an address only (bare
540*4882a593Smuzhiyun * address) transaction.
541*4882a593Smuzhiyun */
542*4882a593Smuzhiyun msg.request &= ~DP_AUX_I2C_MOT;
543*4882a593Smuzhiyun msg.buffer = NULL;
544*4882a593Smuzhiyun msg.size = 0;
545*4882a593Smuzhiyun (void)drm_dp_i2c_do_msg(aux, &msg);
546*4882a593Smuzhiyun
547*4882a593Smuzhiyun return err;
548*4882a593Smuzhiyun }
549*4882a593Smuzhiyun
550