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/OK3568_Linux_fs/kernel/drivers/misc/habanalabs/include/gaudi/asic_reg/
H A Dgaudi_blocks.h16 #define mmNIC0_PHY0_BASE 0x0ull
17 #define NIC0_PHY0_MAX_OFFSET 0x9F13
18 #define mmMME0_ACC_BASE 0x7FFC020000ull
19 #define MME0_ACC_MAX_OFFSET 0x5C00
20 #define MME0_ACC_SECTION 0x20000
21 #define mmMME0_SBAB_BASE 0x7FFC040000ull
22 #define MME0_SBAB_MAX_OFFSET 0x5800
23 #define MME0_SBAB_SECTION 0x1000
24 #define mmMME0_PRTN_BASE 0x7FFC041000ull
25 #define MME0_PRTN_MAX_OFFSET 0x5000
[all …]
/OK3568_Linux_fs/kernel/drivers/net/dsa/mv88e6xxx/
H A Dglobal2.h16 /* Offset 0x00: Interrupt Source Register */
17 #define MV88E6XXX_G2_INT_SRC 0x00
18 #define MV88E6XXX_G2_INT_SRC_WDOG 0x8000
19 #define MV88E6XXX_G2_INT_SRC_JAM_LIMIT 0x4000
20 #define MV88E6XXX_G2_INT_SRC_DUPLEX_MISMATCH 0x2000
21 #define MV88E6XXX_G2_INT_SRC_WAKE_EVENT 0x1000
22 #define MV88E6352_G2_INT_SRC_SERDES 0x0800
23 #define MV88E6352_G2_INT_SRC_PHY 0x001f
24 #define MV88E6390_G2_INT_SRC_PHY 0x07fe
28 /* Offset 0x01: Interrupt Mask Register */
[all …]
H A Dport.h16 /* Offset 0x00: Port Status Register */
17 #define MV88E6XXX_PORT_STS 0x00
18 #define MV88E6XXX_PORT_STS_PAUSE_EN 0x8000
19 #define MV88E6XXX_PORT_STS_MY_PAUSE 0x4000
20 #define MV88E6XXX_PORT_STS_HD_FLOW 0x2000
21 #define MV88E6XXX_PORT_STS_PHY_DETECT 0x1000
22 #define MV88E6250_PORT_STS_LINK 0x1000
23 #define MV88E6250_PORT_STS_PORTMODE_MASK 0x0f00
24 #define MV88E6250_PORT_STS_PORTMODE_PHY_10_HALF 0x0800
25 #define MV88E6250_PORT_STS_PORTMODE_PHY_100_HALF 0x0900
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/ti/
H A Dk3-am654.dtsi13 #size-cells = <0>;
36 cpu0: cpu@0 {
38 reg = <0x000>;
41 i-cache-size = <0x8000>;
44 d-cache-size = <0x8000>;
52 reg = <0x001>;
55 i-cache-size = <0x8000>;
58 d-cache-size = <0x8000>;
66 reg = <0x100>;
69 i-cache-size = <0x8000>;
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/amazon/
H A Dalpine-v3.dtsi21 #size-cells = <0>;
23 cpu@0 {
26 reg = <0x0>;
28 d-cache-size = <0x8000>;
31 i-cache-size = <0xc000>;
40 reg = <0x1>;
42 d-cache-size = <0x8000>;
45 i-cache-size = <0xc000>;
54 reg = <0x2>;
56 d-cache-size = <0x8000>;
[all …]
/OK3568_Linux_fs/kernel/include/linux/mfd/wm8350/
H A Dcore.h27 #define WM8350_RESET_ID 0x00
28 #define WM8350_ID 0x01
29 #define WM8350_REVISION 0x02
30 #define WM8350_SYSTEM_CONTROL_1 0x03
31 #define WM8350_SYSTEM_CONTROL_2 0x04
32 #define WM8350_SYSTEM_HIBERNATE 0x05
33 #define WM8350_INTERFACE_CONTROL 0x06
34 #define WM8350_POWER_MGMT_1 0x08
35 #define WM8350_POWER_MGMT_2 0x09
36 #define WM8350_POWER_MGMT_3 0x0A
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/pci/
H A Dpci-msi.txt13 * Bits [2:0] are the Function number.
67 reg = <0xa 0x1>;
74 reg = <0xf 0x1>;
82 msi-map = <0x0 &msi_a 0x0 0x10000>,
95 reg = <0xa 0x1>;
102 reg = <0xf 0x1>;
110 msi-map = <0x0 &msi_a 0x0 0x100>,
111 msi-map-mask = <0xff>
124 reg = <0xa 0x1>;
131 reg = <0xf 0x1>;
[all …]
H A Dpci-iommu.txt13 * Bits [2:0] are the Function number.
56 reg = <0xa 0x1>;
62 reg = <0xf 0x1>;
70 iommu-map = <0x0 &iommu 0x0 0x10000>;
83 reg = <0xa 0x1>;
89 reg = <0xf 0x1>;
97 iommu-map = <0x0 &iommu 0x0 0x10000>;
98 iommu-map-mask = <0xfff8>;
111 reg = <0xa 0x1>;
117 reg = <0xf 0x1>;
[all …]
/OK3568_Linux_fs/kernel/include/linux/mfd/wm831x/
H A Dpmu.h14 * R16387 (0x4003) - Power State
16 #define WM831X_CHIP_ON 0x8000 /* CHIP_ON */
17 #define WM831X_CHIP_ON_MASK 0x8000 /* CHIP_ON */
20 #define WM831X_CHIP_SLP 0x4000 /* CHIP_SLP */
21 #define WM831X_CHIP_SLP_MASK 0x4000 /* CHIP_SLP */
24 #define WM831X_REF_LP 0x1000 /* REF_LP */
25 #define WM831X_REF_LP_MASK 0x1000 /* REF_LP */
28 #define WM831X_PWRSTATE_DLY_MASK 0x0C00 /* PWRSTATE_DLY - [11:10] */
31 #define WM831X_SWRST_DLY 0x0200 /* SWRST_DLY */
32 #define WM831X_SWRST_DLY_MASK 0x0200 /* SWRST_DLY */
[all …]
/OK3568_Linux_fs/kernel/drivers/net/ethernet/amd/
H A Dam79c961a.h9 /* use 0 for production, 1 for verification, >2 for debug. debug flags: */
15 #define NET_DEBUG 0
18 #define NET_UID 0
19 #define NET_RDP 0x10
20 #define NET_RAP 0x12
21 #define NET_RESET 0x14
22 #define NET_IDP 0x16
27 #define CSR0 0
28 #define CSR0_INIT 0x0001
29 #define CSR0_STRT 0x0002
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/arm/
H A Djuno-r2.dts37 #size-cells = <0>;
68 CPU_SLEEP_0: cpu-sleep-0 {
70 arm,psci-suspend-param = <0x0010000>;
77 CLUSTER_SLEEP_0: cluster-sleep-0 {
79 arm,psci-suspend-param = <0x1010000>;
87 A72_0: cpu@0 {
89 reg = <0x0 0x0>;
92 i-cache-size = <0xc000>;
95 d-cache-size = <0x8000>;
99 clocks = <&scpi_dvfs 0>;
[all …]
H A Djuno.dts36 #size-cells = <0>;
67 CPU_SLEEP_0: cpu-sleep-0 {
69 arm,psci-suspend-param = <0x0010000>;
76 CLUSTER_SLEEP_0: cluster-sleep-0 {
78 arm,psci-suspend-param = <0x1010000>;
86 A57_0: cpu@0 {
88 reg = <0x0 0x0>;
91 i-cache-size = <0xc000>;
94 d-cache-size = <0x8000>;
98 clocks = <&scpi_dvfs 0>;
[all …]
H A Djuno-r1.dts37 #size-cells = <0>;
68 CPU_SLEEP_0: cpu-sleep-0 {
70 arm,psci-suspend-param = <0x0010000>;
77 CLUSTER_SLEEP_0: cluster-sleep-0 {
79 arm,psci-suspend-param = <0x1010000>;
87 A57_0: cpu@0 {
89 reg = <0x0 0x0>;
92 i-cache-size = <0xc000>;
95 d-cache-size = <0x8000>;
99 clocks = <&scpi_dvfs 0>;
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dbcm2837.dtsi9 ranges = <0x7e000000 0x3f000000 0x1000000>,
10 <0x40000000 0x40000000 0x00001000>;
11 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
15 reg = <0x40000000 0x100>;
31 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, // PHYS_SECURE_PPI
40 #size-cells = <0>;
50 cpu0: cpu@0 {
53 reg = <0>;
55 cpu-release-addr = <0x0 0x000000d8>;
56 d-cache-size = <0x8000>;
[all …]
/OK3568_Linux_fs/u-boot/board/gdsys/common/
H A Dphy.c31 { MIICMD_SET, 22, 0x0000 },
32 { MIICMD_VERIFY_VALUE, 2, 0x0141, 0xffff },
33 { MIICMD_VERIFY_VALUE, 3, 0x0dd0, 0xfff0 },
40 { MIICMD_SET, 22, 0x00ff },
41 { MIICMD_SET, 17, 0x214b },
42 { MIICMD_SET, 16, 0x2144 },
43 { MIICMD_SET, 17, 0x0c28 },
44 { MIICMD_SET, 16, 0x2146 },
45 { MIICMD_SET, 17, 0xb233 },
46 { MIICMD_SET, 16, 0x214d },
[all …]
/OK3568_Linux_fs/buildroot/boot/mxs-bootlets/
H A Dbarebox_ivt.bd9 section (0) {
16 load ivt (entry = power_prep:_start) > 0x8000;
17 hab call 0x8000;
24 load ivt (entry = sdram_prep:_start) > 0x8000;
25 hab call 0x8000;
31 load ivt (entry = barebox:start) > 0x8000;
32 hab call 0x8000;
/OK3568_Linux_fs/kernel/include/linux/mfd/
H A Dwm8400-private.h16 #define WM8400_REGISTER_COUNT 0x55
28 #define WM8400_RESET_ID 0x00
29 #define WM8400_ID 0x01
30 #define WM8400_POWER_MANAGEMENT_1 0x02
31 #define WM8400_POWER_MANAGEMENT_2 0x03
32 #define WM8400_POWER_MANAGEMENT_3 0x04
33 #define WM8400_AUDIO_INTERFACE_1 0x05
34 #define WM8400_AUDIO_INTERFACE_2 0x06
35 #define WM8400_CLOCKING_1 0x07
36 #define WM8400_CLOCKING_2 0x08
[all …]
/OK3568_Linux_fs/kernel/drivers/mfd/
H A Dwm97xx-core.c23 #define WM9705_VENDOR_ID 0x574d4c05
24 #define WM9712_VENDOR_ID 0x574d4c12
25 #define WM9713_VENDOR_ID 0x574d4c13
26 #define WM97xx_VENDOR_ID_MASK 0xffffffff
42 case AC97_GPIO_CFG ... 0x5c: in wm97xx_readable_reg()
44 case 0x74 ... AC97_VENDOR_ID2: in wm97xx_readable_reg()
63 { 0x02, 0x8000 },
64 { 0x04, 0x8000 },
65 { 0x06, 0x8000 },
66 { 0x0a, 0x8000 },
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/gmc/
H A Dgmc_7_0_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MC_RD_ENABLE_MASK 0x30
36 #define MC_CONFIG__MC_RD_ENABLE__SHIFT 0x4
[all …]
H A Dgmc_8_2_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
[all …]
/OK3568_Linux_fs/kernel/drivers/net/ethernet/cirrus/
H A Dcs89x0.h18 #define PP_ChipID 0x0000 /* offset 0h -> Corp -ID */
22 #define PP_ISAIOB 0x0020 /* IO base address */
23 #define PP_CS8900_ISAINT 0x0022 /* ISA interrupt select */
24 #define PP_CS8920_ISAINT 0x0370 /* ISA interrupt select */
25 #define PP_CS8900_ISADMA 0x0024 /* ISA Rec DMA channel */
26 #define PP_CS8920_ISADMA 0x0374 /* ISA Rec DMA channel */
27 #define PP_ISASOF 0x0026 /* ISA DMA offset */
28 #define PP_DmaFrameCnt 0x0028 /* ISA DMA Frame count */
29 #define PP_DmaByteCnt 0x002A /* ISA DMA Byte count */
30 #define PP_CS8900_ISAMemB 0x002C /* Memory base */
[all …]
/OK3568_Linux_fs/kernel/drivers/pcmcia/
H A Dtcic.h33 #define TCIC_BASE 0x240
36 #define TCIC_DATA 0x00
37 #define TCIC_ADDR 0x02
38 #define TCIC_SCTRL 0x06
39 #define TCIC_SSTAT 0x07
40 #define TCIC_MODE 0x08
41 #define TCIC_PWR 0x09
42 #define TCIC_EDC 0x0A
43 #define TCIC_ICSR 0x0C
44 #define TCIC_IENA 0x0D
[all …]
/OK3568_Linux_fs/kernel/arch/mips/include/asm/mach-db1x00/
H A Dbcsr.h23 #define DB1000_BCSR_PHYS_ADDR 0x0E000000
24 #define DB1000_BCSR_HEXLED_OFS 0x01000000
26 #define DB1550_BCSR_PHYS_ADDR 0x0F000000
27 #define DB1550_BCSR_HEXLED_OFS 0x00400000
29 #define PB1550_BCSR_PHYS_ADDR 0x0F000000
30 #define PB1550_BCSR_HEXLED_OFS 0x00800000
32 #define DB1200_BCSR_PHYS_ADDR 0x19800000
33 #define DB1200_BCSR_HEXLED_OFS 0x00400000
35 #define PB1200_BCSR_PHYS_ADDR 0x0D800000
36 #define PB1200_BCSR_HEXLED_OFS 0x00400000
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/cpu/arm926ejs/mxs/
H A Dmxsimage.mx28.cfg2 SECTION 0x0 BOOTABLE
4 LOAD 0x1000 spl/u-boot-spl.bin
5 LOAD IVT 0x8000 0x1000
6 CALL HAB 0x8000 0x0
7 LOAD 0x40002000 u-boot.bin
8 LOAD IVT 0x8000 0x40002000
9 CALL HAB 0x8000 0x0
H A Du-boot-imx28.bd6 section (0) {
7 load u_boot_spl > 0x0000;
8 load ivt (entry = 0x0014) > 0x8000;
9 hab call 0x8000;
11 load u_boot > 0x40000100;
12 load ivt (entry = 0x40000100) > 0x8000;
13 hab call 0x8000;

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