1*4882a593Smuzhiyun#include "bcm283x.dtsi" 2*4882a593Smuzhiyun#include "bcm2835-common.dtsi" 3*4882a593Smuzhiyun#include "bcm2835-rpi-common.dtsi" 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun/ { 6*4882a593Smuzhiyun compatible = "brcm,bcm2837"; 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun soc { 9*4882a593Smuzhiyun ranges = <0x7e000000 0x3f000000 0x1000000>, 10*4882a593Smuzhiyun <0x40000000 0x40000000 0x00001000>; 11*4882a593Smuzhiyun dma-ranges = <0xc0000000 0x00000000 0x3f000000>; 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun local_intc: local_intc@40000000 { 14*4882a593Smuzhiyun compatible = "brcm,bcm2836-l1-intc"; 15*4882a593Smuzhiyun reg = <0x40000000 0x100>; 16*4882a593Smuzhiyun interrupt-controller; 17*4882a593Smuzhiyun #interrupt-cells = <2>; 18*4882a593Smuzhiyun interrupt-parent = <&local_intc>; 19*4882a593Smuzhiyun }; 20*4882a593Smuzhiyun }; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun arm-pmu { 23*4882a593Smuzhiyun compatible = "arm,cortex-a53-pmu"; 24*4882a593Smuzhiyun interrupt-parent = <&local_intc>; 25*4882a593Smuzhiyun interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun timer { 29*4882a593Smuzhiyun compatible = "arm,armv7-timer"; 30*4882a593Smuzhiyun interrupt-parent = <&local_intc>; 31*4882a593Smuzhiyun interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, // PHYS_SECURE_PPI 32*4882a593Smuzhiyun <1 IRQ_TYPE_LEVEL_HIGH>, // PHYS_NONSECURE_PPI 33*4882a593Smuzhiyun <3 IRQ_TYPE_LEVEL_HIGH>, // VIRT_PPI 34*4882a593Smuzhiyun <2 IRQ_TYPE_LEVEL_HIGH>; // HYP_PPI 35*4882a593Smuzhiyun always-on; 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun cpus: cpus { 39*4882a593Smuzhiyun #address-cells = <1>; 40*4882a593Smuzhiyun #size-cells = <0>; 41*4882a593Smuzhiyun enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* Source for d/i-cache-line-size and d/i-cache-sets 44*4882a593Smuzhiyun * https://developer.arm.com/documentation/ddi0500/e/level-1-memory-system 45*4882a593Smuzhiyun * /about-the-l1-memory-system?lang=en 46*4882a593Smuzhiyun * 47*4882a593Smuzhiyun * Source for d/i-cache-size 48*4882a593Smuzhiyun * https://magpi.raspberrypi.com/articles/raspberry-pi-3-specs-benchmarks 49*4882a593Smuzhiyun */ 50*4882a593Smuzhiyun cpu0: cpu@0 { 51*4882a593Smuzhiyun device_type = "cpu"; 52*4882a593Smuzhiyun compatible = "arm,cortex-a53"; 53*4882a593Smuzhiyun reg = <0>; 54*4882a593Smuzhiyun enable-method = "spin-table"; 55*4882a593Smuzhiyun cpu-release-addr = <0x0 0x000000d8>; 56*4882a593Smuzhiyun d-cache-size = <0x8000>; 57*4882a593Smuzhiyun d-cache-line-size = <64>; 58*4882a593Smuzhiyun d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set 59*4882a593Smuzhiyun i-cache-size = <0x8000>; 60*4882a593Smuzhiyun i-cache-line-size = <64>; 61*4882a593Smuzhiyun i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set 62*4882a593Smuzhiyun next-level-cache = <&l2>; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun cpu1: cpu@1 { 66*4882a593Smuzhiyun device_type = "cpu"; 67*4882a593Smuzhiyun compatible = "arm,cortex-a53"; 68*4882a593Smuzhiyun reg = <1>; 69*4882a593Smuzhiyun enable-method = "spin-table"; 70*4882a593Smuzhiyun cpu-release-addr = <0x0 0x000000e0>; 71*4882a593Smuzhiyun d-cache-size = <0x8000>; 72*4882a593Smuzhiyun d-cache-line-size = <64>; 73*4882a593Smuzhiyun d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set 74*4882a593Smuzhiyun i-cache-size = <0x8000>; 75*4882a593Smuzhiyun i-cache-line-size = <64>; 76*4882a593Smuzhiyun i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set 77*4882a593Smuzhiyun next-level-cache = <&l2>; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun cpu2: cpu@2 { 81*4882a593Smuzhiyun device_type = "cpu"; 82*4882a593Smuzhiyun compatible = "arm,cortex-a53"; 83*4882a593Smuzhiyun reg = <2>; 84*4882a593Smuzhiyun enable-method = "spin-table"; 85*4882a593Smuzhiyun cpu-release-addr = <0x0 0x000000e8>; 86*4882a593Smuzhiyun d-cache-size = <0x8000>; 87*4882a593Smuzhiyun d-cache-line-size = <64>; 88*4882a593Smuzhiyun d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set 89*4882a593Smuzhiyun i-cache-size = <0x8000>; 90*4882a593Smuzhiyun i-cache-line-size = <64>; 91*4882a593Smuzhiyun i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set 92*4882a593Smuzhiyun next-level-cache = <&l2>; 93*4882a593Smuzhiyun }; 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun cpu3: cpu@3 { 96*4882a593Smuzhiyun device_type = "cpu"; 97*4882a593Smuzhiyun compatible = "arm,cortex-a53"; 98*4882a593Smuzhiyun reg = <3>; 99*4882a593Smuzhiyun enable-method = "spin-table"; 100*4882a593Smuzhiyun cpu-release-addr = <0x0 0x000000f0>; 101*4882a593Smuzhiyun d-cache-size = <0x8000>; 102*4882a593Smuzhiyun d-cache-line-size = <64>; 103*4882a593Smuzhiyun d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set 104*4882a593Smuzhiyun i-cache-size = <0x8000>; 105*4882a593Smuzhiyun i-cache-line-size = <64>; 106*4882a593Smuzhiyun i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set 107*4882a593Smuzhiyun next-level-cache = <&l2>; 108*4882a593Smuzhiyun }; 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun /* Source for cache-line-size + cache-sets 111*4882a593Smuzhiyun * https://developer.arm.com/documentation/ddi0500 112*4882a593Smuzhiyun * /e/level-2-memory-system/about-the-l2-memory-system?lang=en 113*4882a593Smuzhiyun * Source for cache-size 114*4882a593Smuzhiyun * https://datasheets.raspberrypi.com/cm/cm1-and-cm3-datasheet.pdf 115*4882a593Smuzhiyun */ 116*4882a593Smuzhiyun l2: l2-cache0 { 117*4882a593Smuzhiyun compatible = "cache"; 118*4882a593Smuzhiyun cache-size = <0x80000>; 119*4882a593Smuzhiyun cache-line-size = <64>; 120*4882a593Smuzhiyun cache-sets = <512>; // 512KiB(size)/64(line-size)=8192ways/16-way set 121*4882a593Smuzhiyun cache-level = <2>; 122*4882a593Smuzhiyun }; 123*4882a593Smuzhiyun }; 124*4882a593Smuzhiyun}; 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun/* Make the BCM2835-style global interrupt controller be a child of the 127*4882a593Smuzhiyun * CPU-local interrupt controller. 128*4882a593Smuzhiyun */ 129*4882a593Smuzhiyun&intc { 130*4882a593Smuzhiyun compatible = "brcm,bcm2836-armctrl-ic"; 131*4882a593Smuzhiyun reg = <0x7e00b200 0x200>; 132*4882a593Smuzhiyun interrupt-parent = <&local_intc>; 133*4882a593Smuzhiyun interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; 134*4882a593Smuzhiyun}; 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun&cpu_thermal { 137*4882a593Smuzhiyun coefficients = <(-538) 412000>; 138*4882a593Smuzhiyun}; 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun/* enable thermal sensor with the correct compatible property set */ 141*4882a593Smuzhiyun&thermal { 142*4882a593Smuzhiyun compatible = "brcm,bcm2837-thermal"; 143*4882a593Smuzhiyun status = "okay"; 144*4882a593Smuzhiyun}; 145