1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * wm8400 private definitions. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2008 Wolfson Microelectronics plc 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __LINUX_MFD_WM8400_PRIV_H 9*4882a593Smuzhiyun #define __LINUX_MFD_WM8400_PRIV_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <linux/mfd/wm8400.h> 12*4882a593Smuzhiyun #include <linux/mutex.h> 13*4882a593Smuzhiyun #include <linux/platform_device.h> 14*4882a593Smuzhiyun #include <linux/regmap.h> 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define WM8400_REGISTER_COUNT 0x55 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun struct wm8400 { 19*4882a593Smuzhiyun struct device *dev; 20*4882a593Smuzhiyun struct regmap *regmap; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun struct platform_device regulators[6]; 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* 26*4882a593Smuzhiyun * Register values. 27*4882a593Smuzhiyun */ 28*4882a593Smuzhiyun #define WM8400_RESET_ID 0x00 29*4882a593Smuzhiyun #define WM8400_ID 0x01 30*4882a593Smuzhiyun #define WM8400_POWER_MANAGEMENT_1 0x02 31*4882a593Smuzhiyun #define WM8400_POWER_MANAGEMENT_2 0x03 32*4882a593Smuzhiyun #define WM8400_POWER_MANAGEMENT_3 0x04 33*4882a593Smuzhiyun #define WM8400_AUDIO_INTERFACE_1 0x05 34*4882a593Smuzhiyun #define WM8400_AUDIO_INTERFACE_2 0x06 35*4882a593Smuzhiyun #define WM8400_CLOCKING_1 0x07 36*4882a593Smuzhiyun #define WM8400_CLOCKING_2 0x08 37*4882a593Smuzhiyun #define WM8400_AUDIO_INTERFACE_3 0x09 38*4882a593Smuzhiyun #define WM8400_AUDIO_INTERFACE_4 0x0A 39*4882a593Smuzhiyun #define WM8400_DAC_CTRL 0x0B 40*4882a593Smuzhiyun #define WM8400_LEFT_DAC_DIGITAL_VOLUME 0x0C 41*4882a593Smuzhiyun #define WM8400_RIGHT_DAC_DIGITAL_VOLUME 0x0D 42*4882a593Smuzhiyun #define WM8400_DIGITAL_SIDE_TONE 0x0E 43*4882a593Smuzhiyun #define WM8400_ADC_CTRL 0x0F 44*4882a593Smuzhiyun #define WM8400_LEFT_ADC_DIGITAL_VOLUME 0x10 45*4882a593Smuzhiyun #define WM8400_RIGHT_ADC_DIGITAL_VOLUME 0x11 46*4882a593Smuzhiyun #define WM8400_GPIO_CTRL_1 0x12 47*4882a593Smuzhiyun #define WM8400_GPIO1_GPIO2 0x13 48*4882a593Smuzhiyun #define WM8400_GPIO3_GPIO4 0x14 49*4882a593Smuzhiyun #define WM8400_GPIO5_GPIO6 0x15 50*4882a593Smuzhiyun #define WM8400_GPIOCTRL_2 0x16 51*4882a593Smuzhiyun #define WM8400_GPIO_POL 0x17 52*4882a593Smuzhiyun #define WM8400_LEFT_LINE_INPUT_1_2_VOLUME 0x18 53*4882a593Smuzhiyun #define WM8400_LEFT_LINE_INPUT_3_4_VOLUME 0x19 54*4882a593Smuzhiyun #define WM8400_RIGHT_LINE_INPUT_1_2_VOLUME 0x1A 55*4882a593Smuzhiyun #define WM8400_RIGHT_LINE_INPUT_3_4_VOLUME 0x1B 56*4882a593Smuzhiyun #define WM8400_LEFT_OUTPUT_VOLUME 0x1C 57*4882a593Smuzhiyun #define WM8400_RIGHT_OUTPUT_VOLUME 0x1D 58*4882a593Smuzhiyun #define WM8400_LINE_OUTPUTS_VOLUME 0x1E 59*4882a593Smuzhiyun #define WM8400_OUT3_4_VOLUME 0x1F 60*4882a593Smuzhiyun #define WM8400_LEFT_OPGA_VOLUME 0x20 61*4882a593Smuzhiyun #define WM8400_RIGHT_OPGA_VOLUME 0x21 62*4882a593Smuzhiyun #define WM8400_SPEAKER_VOLUME 0x22 63*4882a593Smuzhiyun #define WM8400_CLASSD1 0x23 64*4882a593Smuzhiyun #define WM8400_CLASSD3 0x25 65*4882a593Smuzhiyun #define WM8400_INPUT_MIXER1 0x27 66*4882a593Smuzhiyun #define WM8400_INPUT_MIXER2 0x28 67*4882a593Smuzhiyun #define WM8400_INPUT_MIXER3 0x29 68*4882a593Smuzhiyun #define WM8400_INPUT_MIXER4 0x2A 69*4882a593Smuzhiyun #define WM8400_INPUT_MIXER5 0x2B 70*4882a593Smuzhiyun #define WM8400_INPUT_MIXER6 0x2C 71*4882a593Smuzhiyun #define WM8400_OUTPUT_MIXER1 0x2D 72*4882a593Smuzhiyun #define WM8400_OUTPUT_MIXER2 0x2E 73*4882a593Smuzhiyun #define WM8400_OUTPUT_MIXER3 0x2F 74*4882a593Smuzhiyun #define WM8400_OUTPUT_MIXER4 0x30 75*4882a593Smuzhiyun #define WM8400_OUTPUT_MIXER5 0x31 76*4882a593Smuzhiyun #define WM8400_OUTPUT_MIXER6 0x32 77*4882a593Smuzhiyun #define WM8400_OUT3_4_MIXER 0x33 78*4882a593Smuzhiyun #define WM8400_LINE_MIXER1 0x34 79*4882a593Smuzhiyun #define WM8400_LINE_MIXER2 0x35 80*4882a593Smuzhiyun #define WM8400_SPEAKER_MIXER 0x36 81*4882a593Smuzhiyun #define WM8400_ADDITIONAL_CONTROL 0x37 82*4882a593Smuzhiyun #define WM8400_ANTIPOP1 0x38 83*4882a593Smuzhiyun #define WM8400_ANTIPOP2 0x39 84*4882a593Smuzhiyun #define WM8400_MICBIAS 0x3A 85*4882a593Smuzhiyun #define WM8400_FLL_CONTROL_1 0x3C 86*4882a593Smuzhiyun #define WM8400_FLL_CONTROL_2 0x3D 87*4882a593Smuzhiyun #define WM8400_FLL_CONTROL_3 0x3E 88*4882a593Smuzhiyun #define WM8400_FLL_CONTROL_4 0x3F 89*4882a593Smuzhiyun #define WM8400_LDO1_CONTROL 0x41 90*4882a593Smuzhiyun #define WM8400_LDO2_CONTROL 0x42 91*4882a593Smuzhiyun #define WM8400_LDO3_CONTROL 0x43 92*4882a593Smuzhiyun #define WM8400_LDO4_CONTROL 0x44 93*4882a593Smuzhiyun #define WM8400_DCDC1_CONTROL_1 0x46 94*4882a593Smuzhiyun #define WM8400_DCDC1_CONTROL_2 0x47 95*4882a593Smuzhiyun #define WM8400_DCDC2_CONTROL_1 0x48 96*4882a593Smuzhiyun #define WM8400_DCDC2_CONTROL_2 0x49 97*4882a593Smuzhiyun #define WM8400_INTERFACE 0x4B 98*4882a593Smuzhiyun #define WM8400_PM_GENERAL 0x4C 99*4882a593Smuzhiyun #define WM8400_PM_SHUTDOWN_CONTROL 0x4E 100*4882a593Smuzhiyun #define WM8400_INTERRUPT_STATUS_1 0x4F 101*4882a593Smuzhiyun #define WM8400_INTERRUPT_STATUS_1_MASK 0x50 102*4882a593Smuzhiyun #define WM8400_INTERRUPT_LEVELS 0x51 103*4882a593Smuzhiyun #define WM8400_SHUTDOWN_REASON 0x52 104*4882a593Smuzhiyun #define WM8400_LINE_CIRCUITS 0x54 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun /* 107*4882a593Smuzhiyun * Field Definitions. 108*4882a593Smuzhiyun */ 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun /* 111*4882a593Smuzhiyun * R0 (0x00) - Reset/ID 112*4882a593Smuzhiyun */ 113*4882a593Smuzhiyun #define WM8400_SW_RESET_CHIP_ID_MASK 0xFFFF /* SW_RESET/CHIP_ID - [15:0] */ 114*4882a593Smuzhiyun #define WM8400_SW_RESET_CHIP_ID_SHIFT 0 /* SW_RESET/CHIP_ID - [15:0] */ 115*4882a593Smuzhiyun #define WM8400_SW_RESET_CHIP_ID_WIDTH 16 /* SW_RESET/CHIP_ID - [15:0] */ 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun /* 118*4882a593Smuzhiyun * R1 (0x01) - ID 119*4882a593Smuzhiyun */ 120*4882a593Smuzhiyun #define WM8400_CHIP_REV_MASK 0x7000 /* CHIP_REV - [14:12] */ 121*4882a593Smuzhiyun #define WM8400_CHIP_REV_SHIFT 12 /* CHIP_REV - [14:12] */ 122*4882a593Smuzhiyun #define WM8400_CHIP_REV_WIDTH 3 /* CHIP_REV - [14:12] */ 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun /* 125*4882a593Smuzhiyun * R18 (0x12) - GPIO CTRL 1 126*4882a593Smuzhiyun */ 127*4882a593Smuzhiyun #define WM8400_IRQ 0x1000 /* IRQ */ 128*4882a593Smuzhiyun #define WM8400_IRQ_MASK 0x1000 /* IRQ */ 129*4882a593Smuzhiyun #define WM8400_IRQ_SHIFT 12 /* IRQ */ 130*4882a593Smuzhiyun #define WM8400_IRQ_WIDTH 1 /* IRQ */ 131*4882a593Smuzhiyun #define WM8400_TEMPOK 0x0800 /* TEMPOK */ 132*4882a593Smuzhiyun #define WM8400_TEMPOK_MASK 0x0800 /* TEMPOK */ 133*4882a593Smuzhiyun #define WM8400_TEMPOK_SHIFT 11 /* TEMPOK */ 134*4882a593Smuzhiyun #define WM8400_TEMPOK_WIDTH 1 /* TEMPOK */ 135*4882a593Smuzhiyun #define WM8400_MIC1SHRT 0x0400 /* MIC1SHRT */ 136*4882a593Smuzhiyun #define WM8400_MIC1SHRT_MASK 0x0400 /* MIC1SHRT */ 137*4882a593Smuzhiyun #define WM8400_MIC1SHRT_SHIFT 10 /* MIC1SHRT */ 138*4882a593Smuzhiyun #define WM8400_MIC1SHRT_WIDTH 1 /* MIC1SHRT */ 139*4882a593Smuzhiyun #define WM8400_MIC1DET 0x0200 /* MIC1DET */ 140*4882a593Smuzhiyun #define WM8400_MIC1DET_MASK 0x0200 /* MIC1DET */ 141*4882a593Smuzhiyun #define WM8400_MIC1DET_SHIFT 9 /* MIC1DET */ 142*4882a593Smuzhiyun #define WM8400_MIC1DET_WIDTH 1 /* MIC1DET */ 143*4882a593Smuzhiyun #define WM8400_FLL_LCK 0x0100 /* FLL_LCK */ 144*4882a593Smuzhiyun #define WM8400_FLL_LCK_MASK 0x0100 /* FLL_LCK */ 145*4882a593Smuzhiyun #define WM8400_FLL_LCK_SHIFT 8 /* FLL_LCK */ 146*4882a593Smuzhiyun #define WM8400_FLL_LCK_WIDTH 1 /* FLL_LCK */ 147*4882a593Smuzhiyun #define WM8400_GPIO_STATUS_MASK 0x00FF /* GPIO_STATUS - [7:0] */ 148*4882a593Smuzhiyun #define WM8400_GPIO_STATUS_SHIFT 0 /* GPIO_STATUS - [7:0] */ 149*4882a593Smuzhiyun #define WM8400_GPIO_STATUS_WIDTH 8 /* GPIO_STATUS - [7:0] */ 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun /* 152*4882a593Smuzhiyun * R19 (0x13) - GPIO1 & GPIO2 153*4882a593Smuzhiyun */ 154*4882a593Smuzhiyun #define WM8400_GPIO2_DEB_ENA 0x8000 /* GPIO2_DEB_ENA */ 155*4882a593Smuzhiyun #define WM8400_GPIO2_DEB_ENA_MASK 0x8000 /* GPIO2_DEB_ENA */ 156*4882a593Smuzhiyun #define WM8400_GPIO2_DEB_ENA_SHIFT 15 /* GPIO2_DEB_ENA */ 157*4882a593Smuzhiyun #define WM8400_GPIO2_DEB_ENA_WIDTH 1 /* GPIO2_DEB_ENA */ 158*4882a593Smuzhiyun #define WM8400_GPIO2_IRQ_ENA 0x4000 /* GPIO2_IRQ_ENA */ 159*4882a593Smuzhiyun #define WM8400_GPIO2_IRQ_ENA_MASK 0x4000 /* GPIO2_IRQ_ENA */ 160*4882a593Smuzhiyun #define WM8400_GPIO2_IRQ_ENA_SHIFT 14 /* GPIO2_IRQ_ENA */ 161*4882a593Smuzhiyun #define WM8400_GPIO2_IRQ_ENA_WIDTH 1 /* GPIO2_IRQ_ENA */ 162*4882a593Smuzhiyun #define WM8400_GPIO2_PU 0x2000 /* GPIO2_PU */ 163*4882a593Smuzhiyun #define WM8400_GPIO2_PU_MASK 0x2000 /* GPIO2_PU */ 164*4882a593Smuzhiyun #define WM8400_GPIO2_PU_SHIFT 13 /* GPIO2_PU */ 165*4882a593Smuzhiyun #define WM8400_GPIO2_PU_WIDTH 1 /* GPIO2_PU */ 166*4882a593Smuzhiyun #define WM8400_GPIO2_PD 0x1000 /* GPIO2_PD */ 167*4882a593Smuzhiyun #define WM8400_GPIO2_PD_MASK 0x1000 /* GPIO2_PD */ 168*4882a593Smuzhiyun #define WM8400_GPIO2_PD_SHIFT 12 /* GPIO2_PD */ 169*4882a593Smuzhiyun #define WM8400_GPIO2_PD_WIDTH 1 /* GPIO2_PD */ 170*4882a593Smuzhiyun #define WM8400_GPIO2_SEL_MASK 0x0F00 /* GPIO2_SEL - [11:8] */ 171*4882a593Smuzhiyun #define WM8400_GPIO2_SEL_SHIFT 8 /* GPIO2_SEL - [11:8] */ 172*4882a593Smuzhiyun #define WM8400_GPIO2_SEL_WIDTH 4 /* GPIO2_SEL - [11:8] */ 173*4882a593Smuzhiyun #define WM8400_GPIO1_DEB_ENA 0x0080 /* GPIO1_DEB_ENA */ 174*4882a593Smuzhiyun #define WM8400_GPIO1_DEB_ENA_MASK 0x0080 /* GPIO1_DEB_ENA */ 175*4882a593Smuzhiyun #define WM8400_GPIO1_DEB_ENA_SHIFT 7 /* GPIO1_DEB_ENA */ 176*4882a593Smuzhiyun #define WM8400_GPIO1_DEB_ENA_WIDTH 1 /* GPIO1_DEB_ENA */ 177*4882a593Smuzhiyun #define WM8400_GPIO1_IRQ_ENA 0x0040 /* GPIO1_IRQ_ENA */ 178*4882a593Smuzhiyun #define WM8400_GPIO1_IRQ_ENA_MASK 0x0040 /* GPIO1_IRQ_ENA */ 179*4882a593Smuzhiyun #define WM8400_GPIO1_IRQ_ENA_SHIFT 6 /* GPIO1_IRQ_ENA */ 180*4882a593Smuzhiyun #define WM8400_GPIO1_IRQ_ENA_WIDTH 1 /* GPIO1_IRQ_ENA */ 181*4882a593Smuzhiyun #define WM8400_GPIO1_PU 0x0020 /* GPIO1_PU */ 182*4882a593Smuzhiyun #define WM8400_GPIO1_PU_MASK 0x0020 /* GPIO1_PU */ 183*4882a593Smuzhiyun #define WM8400_GPIO1_PU_SHIFT 5 /* GPIO1_PU */ 184*4882a593Smuzhiyun #define WM8400_GPIO1_PU_WIDTH 1 /* GPIO1_PU */ 185*4882a593Smuzhiyun #define WM8400_GPIO1_PD 0x0010 /* GPIO1_PD */ 186*4882a593Smuzhiyun #define WM8400_GPIO1_PD_MASK 0x0010 /* GPIO1_PD */ 187*4882a593Smuzhiyun #define WM8400_GPIO1_PD_SHIFT 4 /* GPIO1_PD */ 188*4882a593Smuzhiyun #define WM8400_GPIO1_PD_WIDTH 1 /* GPIO1_PD */ 189*4882a593Smuzhiyun #define WM8400_GPIO1_SEL_MASK 0x000F /* GPIO1_SEL - [3:0] */ 190*4882a593Smuzhiyun #define WM8400_GPIO1_SEL_SHIFT 0 /* GPIO1_SEL - [3:0] */ 191*4882a593Smuzhiyun #define WM8400_GPIO1_SEL_WIDTH 4 /* GPIO1_SEL - [3:0] */ 192*4882a593Smuzhiyun 193*4882a593Smuzhiyun /* 194*4882a593Smuzhiyun * R20 (0x14) - GPIO3 & GPIO4 195*4882a593Smuzhiyun */ 196*4882a593Smuzhiyun #define WM8400_GPIO4_DEB_ENA 0x8000 /* GPIO4_DEB_ENA */ 197*4882a593Smuzhiyun #define WM8400_GPIO4_DEB_ENA_MASK 0x8000 /* GPIO4_DEB_ENA */ 198*4882a593Smuzhiyun #define WM8400_GPIO4_DEB_ENA_SHIFT 15 /* GPIO4_DEB_ENA */ 199*4882a593Smuzhiyun #define WM8400_GPIO4_DEB_ENA_WIDTH 1 /* GPIO4_DEB_ENA */ 200*4882a593Smuzhiyun #define WM8400_GPIO4_IRQ_ENA 0x4000 /* GPIO4_IRQ_ENA */ 201*4882a593Smuzhiyun #define WM8400_GPIO4_IRQ_ENA_MASK 0x4000 /* GPIO4_IRQ_ENA */ 202*4882a593Smuzhiyun #define WM8400_GPIO4_IRQ_ENA_SHIFT 14 /* GPIO4_IRQ_ENA */ 203*4882a593Smuzhiyun #define WM8400_GPIO4_IRQ_ENA_WIDTH 1 /* GPIO4_IRQ_ENA */ 204*4882a593Smuzhiyun #define WM8400_GPIO4_PU 0x2000 /* GPIO4_PU */ 205*4882a593Smuzhiyun #define WM8400_GPIO4_PU_MASK 0x2000 /* GPIO4_PU */ 206*4882a593Smuzhiyun #define WM8400_GPIO4_PU_SHIFT 13 /* GPIO4_PU */ 207*4882a593Smuzhiyun #define WM8400_GPIO4_PU_WIDTH 1 /* GPIO4_PU */ 208*4882a593Smuzhiyun #define WM8400_GPIO4_PD 0x1000 /* GPIO4_PD */ 209*4882a593Smuzhiyun #define WM8400_GPIO4_PD_MASK 0x1000 /* GPIO4_PD */ 210*4882a593Smuzhiyun #define WM8400_GPIO4_PD_SHIFT 12 /* GPIO4_PD */ 211*4882a593Smuzhiyun #define WM8400_GPIO4_PD_WIDTH 1 /* GPIO4_PD */ 212*4882a593Smuzhiyun #define WM8400_GPIO4_SEL_MASK 0x0F00 /* GPIO4_SEL - [11:8] */ 213*4882a593Smuzhiyun #define WM8400_GPIO4_SEL_SHIFT 8 /* GPIO4_SEL - [11:8] */ 214*4882a593Smuzhiyun #define WM8400_GPIO4_SEL_WIDTH 4 /* GPIO4_SEL - [11:8] */ 215*4882a593Smuzhiyun #define WM8400_GPIO3_DEB_ENA 0x0080 /* GPIO3_DEB_ENA */ 216*4882a593Smuzhiyun #define WM8400_GPIO3_DEB_ENA_MASK 0x0080 /* GPIO3_DEB_ENA */ 217*4882a593Smuzhiyun #define WM8400_GPIO3_DEB_ENA_SHIFT 7 /* GPIO3_DEB_ENA */ 218*4882a593Smuzhiyun #define WM8400_GPIO3_DEB_ENA_WIDTH 1 /* GPIO3_DEB_ENA */ 219*4882a593Smuzhiyun #define WM8400_GPIO3_IRQ_ENA 0x0040 /* GPIO3_IRQ_ENA */ 220*4882a593Smuzhiyun #define WM8400_GPIO3_IRQ_ENA_MASK 0x0040 /* GPIO3_IRQ_ENA */ 221*4882a593Smuzhiyun #define WM8400_GPIO3_IRQ_ENA_SHIFT 6 /* GPIO3_IRQ_ENA */ 222*4882a593Smuzhiyun #define WM8400_GPIO3_IRQ_ENA_WIDTH 1 /* GPIO3_IRQ_ENA */ 223*4882a593Smuzhiyun #define WM8400_GPIO3_PU 0x0020 /* GPIO3_PU */ 224*4882a593Smuzhiyun #define WM8400_GPIO3_PU_MASK 0x0020 /* GPIO3_PU */ 225*4882a593Smuzhiyun #define WM8400_GPIO3_PU_SHIFT 5 /* GPIO3_PU */ 226*4882a593Smuzhiyun #define WM8400_GPIO3_PU_WIDTH 1 /* GPIO3_PU */ 227*4882a593Smuzhiyun #define WM8400_GPIO3_PD 0x0010 /* GPIO3_PD */ 228*4882a593Smuzhiyun #define WM8400_GPIO3_PD_MASK 0x0010 /* GPIO3_PD */ 229*4882a593Smuzhiyun #define WM8400_GPIO3_PD_SHIFT 4 /* GPIO3_PD */ 230*4882a593Smuzhiyun #define WM8400_GPIO3_PD_WIDTH 1 /* GPIO3_PD */ 231*4882a593Smuzhiyun #define WM8400_GPIO3_SEL_MASK 0x000F /* GPIO3_SEL - [3:0] */ 232*4882a593Smuzhiyun #define WM8400_GPIO3_SEL_SHIFT 0 /* GPIO3_SEL - [3:0] */ 233*4882a593Smuzhiyun #define WM8400_GPIO3_SEL_WIDTH 4 /* GPIO3_SEL - [3:0] */ 234*4882a593Smuzhiyun 235*4882a593Smuzhiyun /* 236*4882a593Smuzhiyun * R21 (0x15) - GPIO5 & GPIO6 237*4882a593Smuzhiyun */ 238*4882a593Smuzhiyun #define WM8400_GPIO6_DEB_ENA 0x8000 /* GPIO6_DEB_ENA */ 239*4882a593Smuzhiyun #define WM8400_GPIO6_DEB_ENA_MASK 0x8000 /* GPIO6_DEB_ENA */ 240*4882a593Smuzhiyun #define WM8400_GPIO6_DEB_ENA_SHIFT 15 /* GPIO6_DEB_ENA */ 241*4882a593Smuzhiyun #define WM8400_GPIO6_DEB_ENA_WIDTH 1 /* GPIO6_DEB_ENA */ 242*4882a593Smuzhiyun #define WM8400_GPIO6_IRQ_ENA 0x4000 /* GPIO6_IRQ_ENA */ 243*4882a593Smuzhiyun #define WM8400_GPIO6_IRQ_ENA_MASK 0x4000 /* GPIO6_IRQ_ENA */ 244*4882a593Smuzhiyun #define WM8400_GPIO6_IRQ_ENA_SHIFT 14 /* GPIO6_IRQ_ENA */ 245*4882a593Smuzhiyun #define WM8400_GPIO6_IRQ_ENA_WIDTH 1 /* GPIO6_IRQ_ENA */ 246*4882a593Smuzhiyun #define WM8400_GPIO6_PU 0x2000 /* GPIO6_PU */ 247*4882a593Smuzhiyun #define WM8400_GPIO6_PU_MASK 0x2000 /* GPIO6_PU */ 248*4882a593Smuzhiyun #define WM8400_GPIO6_PU_SHIFT 13 /* GPIO6_PU */ 249*4882a593Smuzhiyun #define WM8400_GPIO6_PU_WIDTH 1 /* GPIO6_PU */ 250*4882a593Smuzhiyun #define WM8400_GPIO6_PD 0x1000 /* GPIO6_PD */ 251*4882a593Smuzhiyun #define WM8400_GPIO6_PD_MASK 0x1000 /* GPIO6_PD */ 252*4882a593Smuzhiyun #define WM8400_GPIO6_PD_SHIFT 12 /* GPIO6_PD */ 253*4882a593Smuzhiyun #define WM8400_GPIO6_PD_WIDTH 1 /* GPIO6_PD */ 254*4882a593Smuzhiyun #define WM8400_GPIO6_SEL_MASK 0x0F00 /* GPIO6_SEL - [11:8] */ 255*4882a593Smuzhiyun #define WM8400_GPIO6_SEL_SHIFT 8 /* GPIO6_SEL - [11:8] */ 256*4882a593Smuzhiyun #define WM8400_GPIO6_SEL_WIDTH 4 /* GPIO6_SEL - [11:8] */ 257*4882a593Smuzhiyun #define WM8400_GPIO5_DEB_ENA 0x0080 /* GPIO5_DEB_ENA */ 258*4882a593Smuzhiyun #define WM8400_GPIO5_DEB_ENA_MASK 0x0080 /* GPIO5_DEB_ENA */ 259*4882a593Smuzhiyun #define WM8400_GPIO5_DEB_ENA_SHIFT 7 /* GPIO5_DEB_ENA */ 260*4882a593Smuzhiyun #define WM8400_GPIO5_DEB_ENA_WIDTH 1 /* GPIO5_DEB_ENA */ 261*4882a593Smuzhiyun #define WM8400_GPIO5_IRQ_ENA 0x0040 /* GPIO5_IRQ_ENA */ 262*4882a593Smuzhiyun #define WM8400_GPIO5_IRQ_ENA_MASK 0x0040 /* GPIO5_IRQ_ENA */ 263*4882a593Smuzhiyun #define WM8400_GPIO5_IRQ_ENA_SHIFT 6 /* GPIO5_IRQ_ENA */ 264*4882a593Smuzhiyun #define WM8400_GPIO5_IRQ_ENA_WIDTH 1 /* GPIO5_IRQ_ENA */ 265*4882a593Smuzhiyun #define WM8400_GPIO5_PU 0x0020 /* GPIO5_PU */ 266*4882a593Smuzhiyun #define WM8400_GPIO5_PU_MASK 0x0020 /* GPIO5_PU */ 267*4882a593Smuzhiyun #define WM8400_GPIO5_PU_SHIFT 5 /* GPIO5_PU */ 268*4882a593Smuzhiyun #define WM8400_GPIO5_PU_WIDTH 1 /* GPIO5_PU */ 269*4882a593Smuzhiyun #define WM8400_GPIO5_PD 0x0010 /* GPIO5_PD */ 270*4882a593Smuzhiyun #define WM8400_GPIO5_PD_MASK 0x0010 /* GPIO5_PD */ 271*4882a593Smuzhiyun #define WM8400_GPIO5_PD_SHIFT 4 /* GPIO5_PD */ 272*4882a593Smuzhiyun #define WM8400_GPIO5_PD_WIDTH 1 /* GPIO5_PD */ 273*4882a593Smuzhiyun #define WM8400_GPIO5_SEL_MASK 0x000F /* GPIO5_SEL - [3:0] */ 274*4882a593Smuzhiyun #define WM8400_GPIO5_SEL_SHIFT 0 /* GPIO5_SEL - [3:0] */ 275*4882a593Smuzhiyun #define WM8400_GPIO5_SEL_WIDTH 4 /* GPIO5_SEL - [3:0] */ 276*4882a593Smuzhiyun 277*4882a593Smuzhiyun /* 278*4882a593Smuzhiyun * R22 (0x16) - GPIOCTRL 2 279*4882a593Smuzhiyun */ 280*4882a593Smuzhiyun #define WM8400_TEMPOK_IRQ_ENA 0x0800 /* TEMPOK_IRQ_ENA */ 281*4882a593Smuzhiyun #define WM8400_TEMPOK_IRQ_ENA_MASK 0x0800 /* TEMPOK_IRQ_ENA */ 282*4882a593Smuzhiyun #define WM8400_TEMPOK_IRQ_ENA_SHIFT 11 /* TEMPOK_IRQ_ENA */ 283*4882a593Smuzhiyun #define WM8400_TEMPOK_IRQ_ENA_WIDTH 1 /* TEMPOK_IRQ_ENA */ 284*4882a593Smuzhiyun #define WM8400_MIC1SHRT_IRQ_ENA 0x0400 /* MIC1SHRT_IRQ_ENA */ 285*4882a593Smuzhiyun #define WM8400_MIC1SHRT_IRQ_ENA_MASK 0x0400 /* MIC1SHRT_IRQ_ENA */ 286*4882a593Smuzhiyun #define WM8400_MIC1SHRT_IRQ_ENA_SHIFT 10 /* MIC1SHRT_IRQ_ENA */ 287*4882a593Smuzhiyun #define WM8400_MIC1SHRT_IRQ_ENA_WIDTH 1 /* MIC1SHRT_IRQ_ENA */ 288*4882a593Smuzhiyun #define WM8400_MIC1DET_IRQ_ENA 0x0200 /* MIC1DET_IRQ_ENA */ 289*4882a593Smuzhiyun #define WM8400_MIC1DET_IRQ_ENA_MASK 0x0200 /* MIC1DET_IRQ_ENA */ 290*4882a593Smuzhiyun #define WM8400_MIC1DET_IRQ_ENA_SHIFT 9 /* MIC1DET_IRQ_ENA */ 291*4882a593Smuzhiyun #define WM8400_MIC1DET_IRQ_ENA_WIDTH 1 /* MIC1DET_IRQ_ENA */ 292*4882a593Smuzhiyun #define WM8400_FLL_LCK_IRQ_ENA 0x0100 /* FLL_LCK_IRQ_ENA */ 293*4882a593Smuzhiyun #define WM8400_FLL_LCK_IRQ_ENA_MASK 0x0100 /* FLL_LCK_IRQ_ENA */ 294*4882a593Smuzhiyun #define WM8400_FLL_LCK_IRQ_ENA_SHIFT 8 /* FLL_LCK_IRQ_ENA */ 295*4882a593Smuzhiyun #define WM8400_FLL_LCK_IRQ_ENA_WIDTH 1 /* FLL_LCK_IRQ_ENA */ 296*4882a593Smuzhiyun #define WM8400_GPI8_DEB_ENA 0x0080 /* GPI8_DEB_ENA */ 297*4882a593Smuzhiyun #define WM8400_GPI8_DEB_ENA_MASK 0x0080 /* GPI8_DEB_ENA */ 298*4882a593Smuzhiyun #define WM8400_GPI8_DEB_ENA_SHIFT 7 /* GPI8_DEB_ENA */ 299*4882a593Smuzhiyun #define WM8400_GPI8_DEB_ENA_WIDTH 1 /* GPI8_DEB_ENA */ 300*4882a593Smuzhiyun #define WM8400_GPI8_IRQ_ENA 0x0040 /* GPI8_IRQ_ENA */ 301*4882a593Smuzhiyun #define WM8400_GPI8_IRQ_ENA_MASK 0x0040 /* GPI8_IRQ_ENA */ 302*4882a593Smuzhiyun #define WM8400_GPI8_IRQ_ENA_SHIFT 6 /* GPI8_IRQ_ENA */ 303*4882a593Smuzhiyun #define WM8400_GPI8_IRQ_ENA_WIDTH 1 /* GPI8_IRQ_ENA */ 304*4882a593Smuzhiyun #define WM8400_GPI8_ENA 0x0010 /* GPI8_ENA */ 305*4882a593Smuzhiyun #define WM8400_GPI8_ENA_MASK 0x0010 /* GPI8_ENA */ 306*4882a593Smuzhiyun #define WM8400_GPI8_ENA_SHIFT 4 /* GPI8_ENA */ 307*4882a593Smuzhiyun #define WM8400_GPI8_ENA_WIDTH 1 /* GPI8_ENA */ 308*4882a593Smuzhiyun #define WM8400_GPI7_DEB_ENA 0x0008 /* GPI7_DEB_ENA */ 309*4882a593Smuzhiyun #define WM8400_GPI7_DEB_ENA_MASK 0x0008 /* GPI7_DEB_ENA */ 310*4882a593Smuzhiyun #define WM8400_GPI7_DEB_ENA_SHIFT 3 /* GPI7_DEB_ENA */ 311*4882a593Smuzhiyun #define WM8400_GPI7_DEB_ENA_WIDTH 1 /* GPI7_DEB_ENA */ 312*4882a593Smuzhiyun #define WM8400_GPI7_IRQ_ENA 0x0004 /* GPI7_IRQ_ENA */ 313*4882a593Smuzhiyun #define WM8400_GPI7_IRQ_ENA_MASK 0x0004 /* GPI7_IRQ_ENA */ 314*4882a593Smuzhiyun #define WM8400_GPI7_IRQ_ENA_SHIFT 2 /* GPI7_IRQ_ENA */ 315*4882a593Smuzhiyun #define WM8400_GPI7_IRQ_ENA_WIDTH 1 /* GPI7_IRQ_ENA */ 316*4882a593Smuzhiyun #define WM8400_GPI7_ENA 0x0001 /* GPI7_ENA */ 317*4882a593Smuzhiyun #define WM8400_GPI7_ENA_MASK 0x0001 /* GPI7_ENA */ 318*4882a593Smuzhiyun #define WM8400_GPI7_ENA_SHIFT 0 /* GPI7_ENA */ 319*4882a593Smuzhiyun #define WM8400_GPI7_ENA_WIDTH 1 /* GPI7_ENA */ 320*4882a593Smuzhiyun 321*4882a593Smuzhiyun /* 322*4882a593Smuzhiyun * R23 (0x17) - GPIO_POL 323*4882a593Smuzhiyun */ 324*4882a593Smuzhiyun #define WM8400_IRQ_INV 0x1000 /* IRQ_INV */ 325*4882a593Smuzhiyun #define WM8400_IRQ_INV_MASK 0x1000 /* IRQ_INV */ 326*4882a593Smuzhiyun #define WM8400_IRQ_INV_SHIFT 12 /* IRQ_INV */ 327*4882a593Smuzhiyun #define WM8400_IRQ_INV_WIDTH 1 /* IRQ_INV */ 328*4882a593Smuzhiyun #define WM8400_TEMPOK_POL 0x0800 /* TEMPOK_POL */ 329*4882a593Smuzhiyun #define WM8400_TEMPOK_POL_MASK 0x0800 /* TEMPOK_POL */ 330*4882a593Smuzhiyun #define WM8400_TEMPOK_POL_SHIFT 11 /* TEMPOK_POL */ 331*4882a593Smuzhiyun #define WM8400_TEMPOK_POL_WIDTH 1 /* TEMPOK_POL */ 332*4882a593Smuzhiyun #define WM8400_MIC1SHRT_POL 0x0400 /* MIC1SHRT_POL */ 333*4882a593Smuzhiyun #define WM8400_MIC1SHRT_POL_MASK 0x0400 /* MIC1SHRT_POL */ 334*4882a593Smuzhiyun #define WM8400_MIC1SHRT_POL_SHIFT 10 /* MIC1SHRT_POL */ 335*4882a593Smuzhiyun #define WM8400_MIC1SHRT_POL_WIDTH 1 /* MIC1SHRT_POL */ 336*4882a593Smuzhiyun #define WM8400_MIC1DET_POL 0x0200 /* MIC1DET_POL */ 337*4882a593Smuzhiyun #define WM8400_MIC1DET_POL_MASK 0x0200 /* MIC1DET_POL */ 338*4882a593Smuzhiyun #define WM8400_MIC1DET_POL_SHIFT 9 /* MIC1DET_POL */ 339*4882a593Smuzhiyun #define WM8400_MIC1DET_POL_WIDTH 1 /* MIC1DET_POL */ 340*4882a593Smuzhiyun #define WM8400_FLL_LCK_POL 0x0100 /* FLL_LCK_POL */ 341*4882a593Smuzhiyun #define WM8400_FLL_LCK_POL_MASK 0x0100 /* FLL_LCK_POL */ 342*4882a593Smuzhiyun #define WM8400_FLL_LCK_POL_SHIFT 8 /* FLL_LCK_POL */ 343*4882a593Smuzhiyun #define WM8400_FLL_LCK_POL_WIDTH 1 /* FLL_LCK_POL */ 344*4882a593Smuzhiyun #define WM8400_GPIO_POL_MASK 0x00FF /* GPIO_POL - [7:0] */ 345*4882a593Smuzhiyun #define WM8400_GPIO_POL_SHIFT 0 /* GPIO_POL - [7:0] */ 346*4882a593Smuzhiyun #define WM8400_GPIO_POL_WIDTH 8 /* GPIO_POL - [7:0] */ 347*4882a593Smuzhiyun 348*4882a593Smuzhiyun /* 349*4882a593Smuzhiyun * R65 (0x41) - LDO 1 Control 350*4882a593Smuzhiyun */ 351*4882a593Smuzhiyun #define WM8400_LDO1_ENA 0x8000 /* LDO1_ENA */ 352*4882a593Smuzhiyun #define WM8400_LDO1_ENA_MASK 0x8000 /* LDO1_ENA */ 353*4882a593Smuzhiyun #define WM8400_LDO1_ENA_SHIFT 15 /* LDO1_ENA */ 354*4882a593Smuzhiyun #define WM8400_LDO1_ENA_WIDTH 1 /* LDO1_ENA */ 355*4882a593Smuzhiyun #define WM8400_LDO1_SWI 0x4000 /* LDO1_SWI */ 356*4882a593Smuzhiyun #define WM8400_LDO1_SWI_MASK 0x4000 /* LDO1_SWI */ 357*4882a593Smuzhiyun #define WM8400_LDO1_SWI_SHIFT 14 /* LDO1_SWI */ 358*4882a593Smuzhiyun #define WM8400_LDO1_SWI_WIDTH 1 /* LDO1_SWI */ 359*4882a593Smuzhiyun #define WM8400_LDO1_OPFLT 0x1000 /* LDO1_OPFLT */ 360*4882a593Smuzhiyun #define WM8400_LDO1_OPFLT_MASK 0x1000 /* LDO1_OPFLT */ 361*4882a593Smuzhiyun #define WM8400_LDO1_OPFLT_SHIFT 12 /* LDO1_OPFLT */ 362*4882a593Smuzhiyun #define WM8400_LDO1_OPFLT_WIDTH 1 /* LDO1_OPFLT */ 363*4882a593Smuzhiyun #define WM8400_LDO1_ERRACT 0x0800 /* LDO1_ERRACT */ 364*4882a593Smuzhiyun #define WM8400_LDO1_ERRACT_MASK 0x0800 /* LDO1_ERRACT */ 365*4882a593Smuzhiyun #define WM8400_LDO1_ERRACT_SHIFT 11 /* LDO1_ERRACT */ 366*4882a593Smuzhiyun #define WM8400_LDO1_ERRACT_WIDTH 1 /* LDO1_ERRACT */ 367*4882a593Smuzhiyun #define WM8400_LDO1_HIB_MODE 0x0400 /* LDO1_HIB_MODE */ 368*4882a593Smuzhiyun #define WM8400_LDO1_HIB_MODE_MASK 0x0400 /* LDO1_HIB_MODE */ 369*4882a593Smuzhiyun #define WM8400_LDO1_HIB_MODE_SHIFT 10 /* LDO1_HIB_MODE */ 370*4882a593Smuzhiyun #define WM8400_LDO1_HIB_MODE_WIDTH 1 /* LDO1_HIB_MODE */ 371*4882a593Smuzhiyun #define WM8400_LDO1_VIMG_MASK 0x03E0 /* LDO1_VIMG - [9:5] */ 372*4882a593Smuzhiyun #define WM8400_LDO1_VIMG_SHIFT 5 /* LDO1_VIMG - [9:5] */ 373*4882a593Smuzhiyun #define WM8400_LDO1_VIMG_WIDTH 5 /* LDO1_VIMG - [9:5] */ 374*4882a593Smuzhiyun #define WM8400_LDO1_VSEL_MASK 0x001F /* LDO1_VSEL - [4:0] */ 375*4882a593Smuzhiyun #define WM8400_LDO1_VSEL_SHIFT 0 /* LDO1_VSEL - [4:0] */ 376*4882a593Smuzhiyun #define WM8400_LDO1_VSEL_WIDTH 5 /* LDO1_VSEL - [4:0] */ 377*4882a593Smuzhiyun 378*4882a593Smuzhiyun /* 379*4882a593Smuzhiyun * R66 (0x42) - LDO 2 Control 380*4882a593Smuzhiyun */ 381*4882a593Smuzhiyun #define WM8400_LDO2_ENA 0x8000 /* LDO2_ENA */ 382*4882a593Smuzhiyun #define WM8400_LDO2_ENA_MASK 0x8000 /* LDO2_ENA */ 383*4882a593Smuzhiyun #define WM8400_LDO2_ENA_SHIFT 15 /* LDO2_ENA */ 384*4882a593Smuzhiyun #define WM8400_LDO2_ENA_WIDTH 1 /* LDO2_ENA */ 385*4882a593Smuzhiyun #define WM8400_LDO2_SWI 0x4000 /* LDO2_SWI */ 386*4882a593Smuzhiyun #define WM8400_LDO2_SWI_MASK 0x4000 /* LDO2_SWI */ 387*4882a593Smuzhiyun #define WM8400_LDO2_SWI_SHIFT 14 /* LDO2_SWI */ 388*4882a593Smuzhiyun #define WM8400_LDO2_SWI_WIDTH 1 /* LDO2_SWI */ 389*4882a593Smuzhiyun #define WM8400_LDO2_OPFLT 0x1000 /* LDO2_OPFLT */ 390*4882a593Smuzhiyun #define WM8400_LDO2_OPFLT_MASK 0x1000 /* LDO2_OPFLT */ 391*4882a593Smuzhiyun #define WM8400_LDO2_OPFLT_SHIFT 12 /* LDO2_OPFLT */ 392*4882a593Smuzhiyun #define WM8400_LDO2_OPFLT_WIDTH 1 /* LDO2_OPFLT */ 393*4882a593Smuzhiyun #define WM8400_LDO2_ERRACT 0x0800 /* LDO2_ERRACT */ 394*4882a593Smuzhiyun #define WM8400_LDO2_ERRACT_MASK 0x0800 /* LDO2_ERRACT */ 395*4882a593Smuzhiyun #define WM8400_LDO2_ERRACT_SHIFT 11 /* LDO2_ERRACT */ 396*4882a593Smuzhiyun #define WM8400_LDO2_ERRACT_WIDTH 1 /* LDO2_ERRACT */ 397*4882a593Smuzhiyun #define WM8400_LDO2_HIB_MODE 0x0400 /* LDO2_HIB_MODE */ 398*4882a593Smuzhiyun #define WM8400_LDO2_HIB_MODE_MASK 0x0400 /* LDO2_HIB_MODE */ 399*4882a593Smuzhiyun #define WM8400_LDO2_HIB_MODE_SHIFT 10 /* LDO2_HIB_MODE */ 400*4882a593Smuzhiyun #define WM8400_LDO2_HIB_MODE_WIDTH 1 /* LDO2_HIB_MODE */ 401*4882a593Smuzhiyun #define WM8400_LDO2_VIMG_MASK 0x03E0 /* LDO2_VIMG - [9:5] */ 402*4882a593Smuzhiyun #define WM8400_LDO2_VIMG_SHIFT 5 /* LDO2_VIMG - [9:5] */ 403*4882a593Smuzhiyun #define WM8400_LDO2_VIMG_WIDTH 5 /* LDO2_VIMG - [9:5] */ 404*4882a593Smuzhiyun #define WM8400_LDO2_VSEL_MASK 0x001F /* LDO2_VSEL - [4:0] */ 405*4882a593Smuzhiyun #define WM8400_LDO2_VSEL_SHIFT 0 /* LDO2_VSEL - [4:0] */ 406*4882a593Smuzhiyun #define WM8400_LDO2_VSEL_WIDTH 5 /* LDO2_VSEL - [4:0] */ 407*4882a593Smuzhiyun 408*4882a593Smuzhiyun /* 409*4882a593Smuzhiyun * R67 (0x43) - LDO 3 Control 410*4882a593Smuzhiyun */ 411*4882a593Smuzhiyun #define WM8400_LDO3_ENA 0x8000 /* LDO3_ENA */ 412*4882a593Smuzhiyun #define WM8400_LDO3_ENA_MASK 0x8000 /* LDO3_ENA */ 413*4882a593Smuzhiyun #define WM8400_LDO3_ENA_SHIFT 15 /* LDO3_ENA */ 414*4882a593Smuzhiyun #define WM8400_LDO3_ENA_WIDTH 1 /* LDO3_ENA */ 415*4882a593Smuzhiyun #define WM8400_LDO3_SWI 0x4000 /* LDO3_SWI */ 416*4882a593Smuzhiyun #define WM8400_LDO3_SWI_MASK 0x4000 /* LDO3_SWI */ 417*4882a593Smuzhiyun #define WM8400_LDO3_SWI_SHIFT 14 /* LDO3_SWI */ 418*4882a593Smuzhiyun #define WM8400_LDO3_SWI_WIDTH 1 /* LDO3_SWI */ 419*4882a593Smuzhiyun #define WM8400_LDO3_OPFLT 0x1000 /* LDO3_OPFLT */ 420*4882a593Smuzhiyun #define WM8400_LDO3_OPFLT_MASK 0x1000 /* LDO3_OPFLT */ 421*4882a593Smuzhiyun #define WM8400_LDO3_OPFLT_SHIFT 12 /* LDO3_OPFLT */ 422*4882a593Smuzhiyun #define WM8400_LDO3_OPFLT_WIDTH 1 /* LDO3_OPFLT */ 423*4882a593Smuzhiyun #define WM8400_LDO3_ERRACT 0x0800 /* LDO3_ERRACT */ 424*4882a593Smuzhiyun #define WM8400_LDO3_ERRACT_MASK 0x0800 /* LDO3_ERRACT */ 425*4882a593Smuzhiyun #define WM8400_LDO3_ERRACT_SHIFT 11 /* LDO3_ERRACT */ 426*4882a593Smuzhiyun #define WM8400_LDO3_ERRACT_WIDTH 1 /* LDO3_ERRACT */ 427*4882a593Smuzhiyun #define WM8400_LDO3_HIB_MODE 0x0400 /* LDO3_HIB_MODE */ 428*4882a593Smuzhiyun #define WM8400_LDO3_HIB_MODE_MASK 0x0400 /* LDO3_HIB_MODE */ 429*4882a593Smuzhiyun #define WM8400_LDO3_HIB_MODE_SHIFT 10 /* LDO3_HIB_MODE */ 430*4882a593Smuzhiyun #define WM8400_LDO3_HIB_MODE_WIDTH 1 /* LDO3_HIB_MODE */ 431*4882a593Smuzhiyun #define WM8400_LDO3_VIMG_MASK 0x03E0 /* LDO3_VIMG - [9:5] */ 432*4882a593Smuzhiyun #define WM8400_LDO3_VIMG_SHIFT 5 /* LDO3_VIMG - [9:5] */ 433*4882a593Smuzhiyun #define WM8400_LDO3_VIMG_WIDTH 5 /* LDO3_VIMG - [9:5] */ 434*4882a593Smuzhiyun #define WM8400_LDO3_VSEL_MASK 0x001F /* LDO3_VSEL - [4:0] */ 435*4882a593Smuzhiyun #define WM8400_LDO3_VSEL_SHIFT 0 /* LDO3_VSEL - [4:0] */ 436*4882a593Smuzhiyun #define WM8400_LDO3_VSEL_WIDTH 5 /* LDO3_VSEL - [4:0] */ 437*4882a593Smuzhiyun 438*4882a593Smuzhiyun /* 439*4882a593Smuzhiyun * R68 (0x44) - LDO 4 Control 440*4882a593Smuzhiyun */ 441*4882a593Smuzhiyun #define WM8400_LDO4_ENA 0x8000 /* LDO4_ENA */ 442*4882a593Smuzhiyun #define WM8400_LDO4_ENA_MASK 0x8000 /* LDO4_ENA */ 443*4882a593Smuzhiyun #define WM8400_LDO4_ENA_SHIFT 15 /* LDO4_ENA */ 444*4882a593Smuzhiyun #define WM8400_LDO4_ENA_WIDTH 1 /* LDO4_ENA */ 445*4882a593Smuzhiyun #define WM8400_LDO4_SWI 0x4000 /* LDO4_SWI */ 446*4882a593Smuzhiyun #define WM8400_LDO4_SWI_MASK 0x4000 /* LDO4_SWI */ 447*4882a593Smuzhiyun #define WM8400_LDO4_SWI_SHIFT 14 /* LDO4_SWI */ 448*4882a593Smuzhiyun #define WM8400_LDO4_SWI_WIDTH 1 /* LDO4_SWI */ 449*4882a593Smuzhiyun #define WM8400_LDO4_OPFLT 0x1000 /* LDO4_OPFLT */ 450*4882a593Smuzhiyun #define WM8400_LDO4_OPFLT_MASK 0x1000 /* LDO4_OPFLT */ 451*4882a593Smuzhiyun #define WM8400_LDO4_OPFLT_SHIFT 12 /* LDO4_OPFLT */ 452*4882a593Smuzhiyun #define WM8400_LDO4_OPFLT_WIDTH 1 /* LDO4_OPFLT */ 453*4882a593Smuzhiyun #define WM8400_LDO4_ERRACT 0x0800 /* LDO4_ERRACT */ 454*4882a593Smuzhiyun #define WM8400_LDO4_ERRACT_MASK 0x0800 /* LDO4_ERRACT */ 455*4882a593Smuzhiyun #define WM8400_LDO4_ERRACT_SHIFT 11 /* LDO4_ERRACT */ 456*4882a593Smuzhiyun #define WM8400_LDO4_ERRACT_WIDTH 1 /* LDO4_ERRACT */ 457*4882a593Smuzhiyun #define WM8400_LDO4_HIB_MODE 0x0400 /* LDO4_HIB_MODE */ 458*4882a593Smuzhiyun #define WM8400_LDO4_HIB_MODE_MASK 0x0400 /* LDO4_HIB_MODE */ 459*4882a593Smuzhiyun #define WM8400_LDO4_HIB_MODE_SHIFT 10 /* LDO4_HIB_MODE */ 460*4882a593Smuzhiyun #define WM8400_LDO4_HIB_MODE_WIDTH 1 /* LDO4_HIB_MODE */ 461*4882a593Smuzhiyun #define WM8400_LDO4_VIMG_MASK 0x03E0 /* LDO4_VIMG - [9:5] */ 462*4882a593Smuzhiyun #define WM8400_LDO4_VIMG_SHIFT 5 /* LDO4_VIMG - [9:5] */ 463*4882a593Smuzhiyun #define WM8400_LDO4_VIMG_WIDTH 5 /* LDO4_VIMG - [9:5] */ 464*4882a593Smuzhiyun #define WM8400_LDO4_VSEL_MASK 0x001F /* LDO4_VSEL - [4:0] */ 465*4882a593Smuzhiyun #define WM8400_LDO4_VSEL_SHIFT 0 /* LDO4_VSEL - [4:0] */ 466*4882a593Smuzhiyun #define WM8400_LDO4_VSEL_WIDTH 5 /* LDO4_VSEL - [4:0] */ 467*4882a593Smuzhiyun 468*4882a593Smuzhiyun /* 469*4882a593Smuzhiyun * R70 (0x46) - DCDC1 Control 1 470*4882a593Smuzhiyun */ 471*4882a593Smuzhiyun #define WM8400_DC1_ENA 0x8000 /* DC1_ENA */ 472*4882a593Smuzhiyun #define WM8400_DC1_ENA_MASK 0x8000 /* DC1_ENA */ 473*4882a593Smuzhiyun #define WM8400_DC1_ENA_SHIFT 15 /* DC1_ENA */ 474*4882a593Smuzhiyun #define WM8400_DC1_ENA_WIDTH 1 /* DC1_ENA */ 475*4882a593Smuzhiyun #define WM8400_DC1_ACTIVE 0x4000 /* DC1_ACTIVE */ 476*4882a593Smuzhiyun #define WM8400_DC1_ACTIVE_MASK 0x4000 /* DC1_ACTIVE */ 477*4882a593Smuzhiyun #define WM8400_DC1_ACTIVE_SHIFT 14 /* DC1_ACTIVE */ 478*4882a593Smuzhiyun #define WM8400_DC1_ACTIVE_WIDTH 1 /* DC1_ACTIVE */ 479*4882a593Smuzhiyun #define WM8400_DC1_SLEEP 0x2000 /* DC1_SLEEP */ 480*4882a593Smuzhiyun #define WM8400_DC1_SLEEP_MASK 0x2000 /* DC1_SLEEP */ 481*4882a593Smuzhiyun #define WM8400_DC1_SLEEP_SHIFT 13 /* DC1_SLEEP */ 482*4882a593Smuzhiyun #define WM8400_DC1_SLEEP_WIDTH 1 /* DC1_SLEEP */ 483*4882a593Smuzhiyun #define WM8400_DC1_OPFLT 0x1000 /* DC1_OPFLT */ 484*4882a593Smuzhiyun #define WM8400_DC1_OPFLT_MASK 0x1000 /* DC1_OPFLT */ 485*4882a593Smuzhiyun #define WM8400_DC1_OPFLT_SHIFT 12 /* DC1_OPFLT */ 486*4882a593Smuzhiyun #define WM8400_DC1_OPFLT_WIDTH 1 /* DC1_OPFLT */ 487*4882a593Smuzhiyun #define WM8400_DC1_ERRACT 0x0800 /* DC1_ERRACT */ 488*4882a593Smuzhiyun #define WM8400_DC1_ERRACT_MASK 0x0800 /* DC1_ERRACT */ 489*4882a593Smuzhiyun #define WM8400_DC1_ERRACT_SHIFT 11 /* DC1_ERRACT */ 490*4882a593Smuzhiyun #define WM8400_DC1_ERRACT_WIDTH 1 /* DC1_ERRACT */ 491*4882a593Smuzhiyun #define WM8400_DC1_HIB_MODE 0x0400 /* DC1_HIB_MODE */ 492*4882a593Smuzhiyun #define WM8400_DC1_HIB_MODE_MASK 0x0400 /* DC1_HIB_MODE */ 493*4882a593Smuzhiyun #define WM8400_DC1_HIB_MODE_SHIFT 10 /* DC1_HIB_MODE */ 494*4882a593Smuzhiyun #define WM8400_DC1_HIB_MODE_WIDTH 1 /* DC1_HIB_MODE */ 495*4882a593Smuzhiyun #define WM8400_DC1_SOFTST_MASK 0x0300 /* DC1_SOFTST - [9:8] */ 496*4882a593Smuzhiyun #define WM8400_DC1_SOFTST_SHIFT 8 /* DC1_SOFTST - [9:8] */ 497*4882a593Smuzhiyun #define WM8400_DC1_SOFTST_WIDTH 2 /* DC1_SOFTST - [9:8] */ 498*4882a593Smuzhiyun #define WM8400_DC1_OV_PROT 0x0080 /* DC1_OV_PROT */ 499*4882a593Smuzhiyun #define WM8400_DC1_OV_PROT_MASK 0x0080 /* DC1_OV_PROT */ 500*4882a593Smuzhiyun #define WM8400_DC1_OV_PROT_SHIFT 7 /* DC1_OV_PROT */ 501*4882a593Smuzhiyun #define WM8400_DC1_OV_PROT_WIDTH 1 /* DC1_OV_PROT */ 502*4882a593Smuzhiyun #define WM8400_DC1_VSEL_MASK 0x007F /* DC1_VSEL - [6:0] */ 503*4882a593Smuzhiyun #define WM8400_DC1_VSEL_SHIFT 0 /* DC1_VSEL - [6:0] */ 504*4882a593Smuzhiyun #define WM8400_DC1_VSEL_WIDTH 7 /* DC1_VSEL - [6:0] */ 505*4882a593Smuzhiyun 506*4882a593Smuzhiyun /* 507*4882a593Smuzhiyun * R71 (0x47) - DCDC1 Control 2 508*4882a593Smuzhiyun */ 509*4882a593Smuzhiyun #define WM8400_DC1_FRC_PWM 0x2000 /* DC1_FRC_PWM */ 510*4882a593Smuzhiyun #define WM8400_DC1_FRC_PWM_MASK 0x2000 /* DC1_FRC_PWM */ 511*4882a593Smuzhiyun #define WM8400_DC1_FRC_PWM_SHIFT 13 /* DC1_FRC_PWM */ 512*4882a593Smuzhiyun #define WM8400_DC1_FRC_PWM_WIDTH 1 /* DC1_FRC_PWM */ 513*4882a593Smuzhiyun #define WM8400_DC1_STBY_LIM_MASK 0x0300 /* DC1_STBY_LIM - [9:8] */ 514*4882a593Smuzhiyun #define WM8400_DC1_STBY_LIM_SHIFT 8 /* DC1_STBY_LIM - [9:8] */ 515*4882a593Smuzhiyun #define WM8400_DC1_STBY_LIM_WIDTH 2 /* DC1_STBY_LIM - [9:8] */ 516*4882a593Smuzhiyun #define WM8400_DC1_ACT_LIM 0x0080 /* DC1_ACT_LIM */ 517*4882a593Smuzhiyun #define WM8400_DC1_ACT_LIM_MASK 0x0080 /* DC1_ACT_LIM */ 518*4882a593Smuzhiyun #define WM8400_DC1_ACT_LIM_SHIFT 7 /* DC1_ACT_LIM */ 519*4882a593Smuzhiyun #define WM8400_DC1_ACT_LIM_WIDTH 1 /* DC1_ACT_LIM */ 520*4882a593Smuzhiyun #define WM8400_DC1_VIMG_MASK 0x007F /* DC1_VIMG - [6:0] */ 521*4882a593Smuzhiyun #define WM8400_DC1_VIMG_SHIFT 0 /* DC1_VIMG - [6:0] */ 522*4882a593Smuzhiyun #define WM8400_DC1_VIMG_WIDTH 7 /* DC1_VIMG - [6:0] */ 523*4882a593Smuzhiyun 524*4882a593Smuzhiyun /* 525*4882a593Smuzhiyun * R72 (0x48) - DCDC2 Control 1 526*4882a593Smuzhiyun */ 527*4882a593Smuzhiyun #define WM8400_DC2_ENA 0x8000 /* DC2_ENA */ 528*4882a593Smuzhiyun #define WM8400_DC2_ENA_MASK 0x8000 /* DC2_ENA */ 529*4882a593Smuzhiyun #define WM8400_DC2_ENA_SHIFT 15 /* DC2_ENA */ 530*4882a593Smuzhiyun #define WM8400_DC2_ENA_WIDTH 1 /* DC2_ENA */ 531*4882a593Smuzhiyun #define WM8400_DC2_ACTIVE 0x4000 /* DC2_ACTIVE */ 532*4882a593Smuzhiyun #define WM8400_DC2_ACTIVE_MASK 0x4000 /* DC2_ACTIVE */ 533*4882a593Smuzhiyun #define WM8400_DC2_ACTIVE_SHIFT 14 /* DC2_ACTIVE */ 534*4882a593Smuzhiyun #define WM8400_DC2_ACTIVE_WIDTH 1 /* DC2_ACTIVE */ 535*4882a593Smuzhiyun #define WM8400_DC2_SLEEP 0x2000 /* DC2_SLEEP */ 536*4882a593Smuzhiyun #define WM8400_DC2_SLEEP_MASK 0x2000 /* DC2_SLEEP */ 537*4882a593Smuzhiyun #define WM8400_DC2_SLEEP_SHIFT 13 /* DC2_SLEEP */ 538*4882a593Smuzhiyun #define WM8400_DC2_SLEEP_WIDTH 1 /* DC2_SLEEP */ 539*4882a593Smuzhiyun #define WM8400_DC2_OPFLT 0x1000 /* DC2_OPFLT */ 540*4882a593Smuzhiyun #define WM8400_DC2_OPFLT_MASK 0x1000 /* DC2_OPFLT */ 541*4882a593Smuzhiyun #define WM8400_DC2_OPFLT_SHIFT 12 /* DC2_OPFLT */ 542*4882a593Smuzhiyun #define WM8400_DC2_OPFLT_WIDTH 1 /* DC2_OPFLT */ 543*4882a593Smuzhiyun #define WM8400_DC2_ERRACT 0x0800 /* DC2_ERRACT */ 544*4882a593Smuzhiyun #define WM8400_DC2_ERRACT_MASK 0x0800 /* DC2_ERRACT */ 545*4882a593Smuzhiyun #define WM8400_DC2_ERRACT_SHIFT 11 /* DC2_ERRACT */ 546*4882a593Smuzhiyun #define WM8400_DC2_ERRACT_WIDTH 1 /* DC2_ERRACT */ 547*4882a593Smuzhiyun #define WM8400_DC2_HIB_MODE 0x0400 /* DC2_HIB_MODE */ 548*4882a593Smuzhiyun #define WM8400_DC2_HIB_MODE_MASK 0x0400 /* DC2_HIB_MODE */ 549*4882a593Smuzhiyun #define WM8400_DC2_HIB_MODE_SHIFT 10 /* DC2_HIB_MODE */ 550*4882a593Smuzhiyun #define WM8400_DC2_HIB_MODE_WIDTH 1 /* DC2_HIB_MODE */ 551*4882a593Smuzhiyun #define WM8400_DC2_SOFTST_MASK 0x0300 /* DC2_SOFTST - [9:8] */ 552*4882a593Smuzhiyun #define WM8400_DC2_SOFTST_SHIFT 8 /* DC2_SOFTST - [9:8] */ 553*4882a593Smuzhiyun #define WM8400_DC2_SOFTST_WIDTH 2 /* DC2_SOFTST - [9:8] */ 554*4882a593Smuzhiyun #define WM8400_DC2_OV_PROT 0x0080 /* DC2_OV_PROT */ 555*4882a593Smuzhiyun #define WM8400_DC2_OV_PROT_MASK 0x0080 /* DC2_OV_PROT */ 556*4882a593Smuzhiyun #define WM8400_DC2_OV_PROT_SHIFT 7 /* DC2_OV_PROT */ 557*4882a593Smuzhiyun #define WM8400_DC2_OV_PROT_WIDTH 1 /* DC2_OV_PROT */ 558*4882a593Smuzhiyun #define WM8400_DC2_VSEL_MASK 0x007F /* DC2_VSEL - [6:0] */ 559*4882a593Smuzhiyun #define WM8400_DC2_VSEL_SHIFT 0 /* DC2_VSEL - [6:0] */ 560*4882a593Smuzhiyun #define WM8400_DC2_VSEL_WIDTH 7 /* DC2_VSEL - [6:0] */ 561*4882a593Smuzhiyun 562*4882a593Smuzhiyun /* 563*4882a593Smuzhiyun * R73 (0x49) - DCDC2 Control 2 564*4882a593Smuzhiyun */ 565*4882a593Smuzhiyun #define WM8400_DC2_FRC_PWM 0x2000 /* DC2_FRC_PWM */ 566*4882a593Smuzhiyun #define WM8400_DC2_FRC_PWM_MASK 0x2000 /* DC2_FRC_PWM */ 567*4882a593Smuzhiyun #define WM8400_DC2_FRC_PWM_SHIFT 13 /* DC2_FRC_PWM */ 568*4882a593Smuzhiyun #define WM8400_DC2_FRC_PWM_WIDTH 1 /* DC2_FRC_PWM */ 569*4882a593Smuzhiyun #define WM8400_DC2_STBY_LIM_MASK 0x0300 /* DC2_STBY_LIM - [9:8] */ 570*4882a593Smuzhiyun #define WM8400_DC2_STBY_LIM_SHIFT 8 /* DC2_STBY_LIM - [9:8] */ 571*4882a593Smuzhiyun #define WM8400_DC2_STBY_LIM_WIDTH 2 /* DC2_STBY_LIM - [9:8] */ 572*4882a593Smuzhiyun #define WM8400_DC2_ACT_LIM 0x0080 /* DC2_ACT_LIM */ 573*4882a593Smuzhiyun #define WM8400_DC2_ACT_LIM_MASK 0x0080 /* DC2_ACT_LIM */ 574*4882a593Smuzhiyun #define WM8400_DC2_ACT_LIM_SHIFT 7 /* DC2_ACT_LIM */ 575*4882a593Smuzhiyun #define WM8400_DC2_ACT_LIM_WIDTH 1 /* DC2_ACT_LIM */ 576*4882a593Smuzhiyun #define WM8400_DC2_VIMG_MASK 0x007F /* DC2_VIMG - [6:0] */ 577*4882a593Smuzhiyun #define WM8400_DC2_VIMG_SHIFT 0 /* DC2_VIMG - [6:0] */ 578*4882a593Smuzhiyun #define WM8400_DC2_VIMG_WIDTH 7 /* DC2_VIMG - [6:0] */ 579*4882a593Smuzhiyun 580*4882a593Smuzhiyun /* 581*4882a593Smuzhiyun * R75 (0x4B) - Interface 582*4882a593Smuzhiyun */ 583*4882a593Smuzhiyun #define WM8400_AUTOINC 0x0008 /* AUTOINC */ 584*4882a593Smuzhiyun #define WM8400_AUTOINC_MASK 0x0008 /* AUTOINC */ 585*4882a593Smuzhiyun #define WM8400_AUTOINC_SHIFT 3 /* AUTOINC */ 586*4882a593Smuzhiyun #define WM8400_AUTOINC_WIDTH 1 /* AUTOINC */ 587*4882a593Smuzhiyun #define WM8400_ARA_ENA 0x0004 /* ARA_ENA */ 588*4882a593Smuzhiyun #define WM8400_ARA_ENA_MASK 0x0004 /* ARA_ENA */ 589*4882a593Smuzhiyun #define WM8400_ARA_ENA_SHIFT 2 /* ARA_ENA */ 590*4882a593Smuzhiyun #define WM8400_ARA_ENA_WIDTH 1 /* ARA_ENA */ 591*4882a593Smuzhiyun #define WM8400_SPI_CFG 0x0002 /* SPI_CFG */ 592*4882a593Smuzhiyun #define WM8400_SPI_CFG_MASK 0x0002 /* SPI_CFG */ 593*4882a593Smuzhiyun #define WM8400_SPI_CFG_SHIFT 1 /* SPI_CFG */ 594*4882a593Smuzhiyun #define WM8400_SPI_CFG_WIDTH 1 /* SPI_CFG */ 595*4882a593Smuzhiyun 596*4882a593Smuzhiyun /* 597*4882a593Smuzhiyun * R76 (0x4C) - PM GENERAL 598*4882a593Smuzhiyun */ 599*4882a593Smuzhiyun #define WM8400_CODEC_SOFTST 0x8000 /* CODEC_SOFTST */ 600*4882a593Smuzhiyun #define WM8400_CODEC_SOFTST_MASK 0x8000 /* CODEC_SOFTST */ 601*4882a593Smuzhiyun #define WM8400_CODEC_SOFTST_SHIFT 15 /* CODEC_SOFTST */ 602*4882a593Smuzhiyun #define WM8400_CODEC_SOFTST_WIDTH 1 /* CODEC_SOFTST */ 603*4882a593Smuzhiyun #define WM8400_CODEC_SOFTSD 0x4000 /* CODEC_SOFTSD */ 604*4882a593Smuzhiyun #define WM8400_CODEC_SOFTSD_MASK 0x4000 /* CODEC_SOFTSD */ 605*4882a593Smuzhiyun #define WM8400_CODEC_SOFTSD_SHIFT 14 /* CODEC_SOFTSD */ 606*4882a593Smuzhiyun #define WM8400_CODEC_SOFTSD_WIDTH 1 /* CODEC_SOFTSD */ 607*4882a593Smuzhiyun #define WM8400_CHIP_SOFTSD 0x2000 /* CHIP_SOFTSD */ 608*4882a593Smuzhiyun #define WM8400_CHIP_SOFTSD_MASK 0x2000 /* CHIP_SOFTSD */ 609*4882a593Smuzhiyun #define WM8400_CHIP_SOFTSD_SHIFT 13 /* CHIP_SOFTSD */ 610*4882a593Smuzhiyun #define WM8400_CHIP_SOFTSD_WIDTH 1 /* CHIP_SOFTSD */ 611*4882a593Smuzhiyun #define WM8400_DSLEEP1_POL 0x0008 /* DSLEEP1_POL */ 612*4882a593Smuzhiyun #define WM8400_DSLEEP1_POL_MASK 0x0008 /* DSLEEP1_POL */ 613*4882a593Smuzhiyun #define WM8400_DSLEEP1_POL_SHIFT 3 /* DSLEEP1_POL */ 614*4882a593Smuzhiyun #define WM8400_DSLEEP1_POL_WIDTH 1 /* DSLEEP1_POL */ 615*4882a593Smuzhiyun #define WM8400_DSLEEP2_POL 0x0004 /* DSLEEP2_POL */ 616*4882a593Smuzhiyun #define WM8400_DSLEEP2_POL_MASK 0x0004 /* DSLEEP2_POL */ 617*4882a593Smuzhiyun #define WM8400_DSLEEP2_POL_SHIFT 2 /* DSLEEP2_POL */ 618*4882a593Smuzhiyun #define WM8400_DSLEEP2_POL_WIDTH 1 /* DSLEEP2_POL */ 619*4882a593Smuzhiyun #define WM8400_PWR_STATE_MASK 0x0003 /* PWR_STATE - [1:0] */ 620*4882a593Smuzhiyun #define WM8400_PWR_STATE_SHIFT 0 /* PWR_STATE - [1:0] */ 621*4882a593Smuzhiyun #define WM8400_PWR_STATE_WIDTH 2 /* PWR_STATE - [1:0] */ 622*4882a593Smuzhiyun 623*4882a593Smuzhiyun /* 624*4882a593Smuzhiyun * R78 (0x4E) - PM Shutdown Control 625*4882a593Smuzhiyun */ 626*4882a593Smuzhiyun #define WM8400_CHIP_GT150_ERRACT 0x0200 /* CHIP_GT150_ERRACT */ 627*4882a593Smuzhiyun #define WM8400_CHIP_GT150_ERRACT_MASK 0x0200 /* CHIP_GT150_ERRACT */ 628*4882a593Smuzhiyun #define WM8400_CHIP_GT150_ERRACT_SHIFT 9 /* CHIP_GT150_ERRACT */ 629*4882a593Smuzhiyun #define WM8400_CHIP_GT150_ERRACT_WIDTH 1 /* CHIP_GT150_ERRACT */ 630*4882a593Smuzhiyun #define WM8400_CHIP_GT115_ERRACT 0x0100 /* CHIP_GT115_ERRACT */ 631*4882a593Smuzhiyun #define WM8400_CHIP_GT115_ERRACT_MASK 0x0100 /* CHIP_GT115_ERRACT */ 632*4882a593Smuzhiyun #define WM8400_CHIP_GT115_ERRACT_SHIFT 8 /* CHIP_GT115_ERRACT */ 633*4882a593Smuzhiyun #define WM8400_CHIP_GT115_ERRACT_WIDTH 1 /* CHIP_GT115_ERRACT */ 634*4882a593Smuzhiyun #define WM8400_LINE_CMP_ERRACT 0x0080 /* LINE_CMP_ERRACT */ 635*4882a593Smuzhiyun #define WM8400_LINE_CMP_ERRACT_MASK 0x0080 /* LINE_CMP_ERRACT */ 636*4882a593Smuzhiyun #define WM8400_LINE_CMP_ERRACT_SHIFT 7 /* LINE_CMP_ERRACT */ 637*4882a593Smuzhiyun #define WM8400_LINE_CMP_ERRACT_WIDTH 1 /* LINE_CMP_ERRACT */ 638*4882a593Smuzhiyun #define WM8400_UVLO_ERRACT 0x0040 /* UVLO_ERRACT */ 639*4882a593Smuzhiyun #define WM8400_UVLO_ERRACT_MASK 0x0040 /* UVLO_ERRACT */ 640*4882a593Smuzhiyun #define WM8400_UVLO_ERRACT_SHIFT 6 /* UVLO_ERRACT */ 641*4882a593Smuzhiyun #define WM8400_UVLO_ERRACT_WIDTH 1 /* UVLO_ERRACT */ 642*4882a593Smuzhiyun 643*4882a593Smuzhiyun /* 644*4882a593Smuzhiyun * R79 (0x4F) - Interrupt Status 1 645*4882a593Smuzhiyun */ 646*4882a593Smuzhiyun #define WM8400_MICD_CINT 0x8000 /* MICD_CINT */ 647*4882a593Smuzhiyun #define WM8400_MICD_CINT_MASK 0x8000 /* MICD_CINT */ 648*4882a593Smuzhiyun #define WM8400_MICD_CINT_SHIFT 15 /* MICD_CINT */ 649*4882a593Smuzhiyun #define WM8400_MICD_CINT_WIDTH 1 /* MICD_CINT */ 650*4882a593Smuzhiyun #define WM8400_MICSCD_CINT 0x4000 /* MICSCD_CINT */ 651*4882a593Smuzhiyun #define WM8400_MICSCD_CINT_MASK 0x4000 /* MICSCD_CINT */ 652*4882a593Smuzhiyun #define WM8400_MICSCD_CINT_SHIFT 14 /* MICSCD_CINT */ 653*4882a593Smuzhiyun #define WM8400_MICSCD_CINT_WIDTH 1 /* MICSCD_CINT */ 654*4882a593Smuzhiyun #define WM8400_JDL_CINT 0x2000 /* JDL_CINT */ 655*4882a593Smuzhiyun #define WM8400_JDL_CINT_MASK 0x2000 /* JDL_CINT */ 656*4882a593Smuzhiyun #define WM8400_JDL_CINT_SHIFT 13 /* JDL_CINT */ 657*4882a593Smuzhiyun #define WM8400_JDL_CINT_WIDTH 1 /* JDL_CINT */ 658*4882a593Smuzhiyun #define WM8400_JDR_CINT 0x1000 /* JDR_CINT */ 659*4882a593Smuzhiyun #define WM8400_JDR_CINT_MASK 0x1000 /* JDR_CINT */ 660*4882a593Smuzhiyun #define WM8400_JDR_CINT_SHIFT 12 /* JDR_CINT */ 661*4882a593Smuzhiyun #define WM8400_JDR_CINT_WIDTH 1 /* JDR_CINT */ 662*4882a593Smuzhiyun #define WM8400_CODEC_SEQ_END_EINT 0x0800 /* CODEC_SEQ_END_EINT */ 663*4882a593Smuzhiyun #define WM8400_CODEC_SEQ_END_EINT_MASK 0x0800 /* CODEC_SEQ_END_EINT */ 664*4882a593Smuzhiyun #define WM8400_CODEC_SEQ_END_EINT_SHIFT 11 /* CODEC_SEQ_END_EINT */ 665*4882a593Smuzhiyun #define WM8400_CODEC_SEQ_END_EINT_WIDTH 1 /* CODEC_SEQ_END_EINT */ 666*4882a593Smuzhiyun #define WM8400_CDEL_TO_EINT 0x0400 /* CDEL_TO_EINT */ 667*4882a593Smuzhiyun #define WM8400_CDEL_TO_EINT_MASK 0x0400 /* CDEL_TO_EINT */ 668*4882a593Smuzhiyun #define WM8400_CDEL_TO_EINT_SHIFT 10 /* CDEL_TO_EINT */ 669*4882a593Smuzhiyun #define WM8400_CDEL_TO_EINT_WIDTH 1 /* CDEL_TO_EINT */ 670*4882a593Smuzhiyun #define WM8400_CHIP_GT150_EINT 0x0200 /* CHIP_GT150_EINT */ 671*4882a593Smuzhiyun #define WM8400_CHIP_GT150_EINT_MASK 0x0200 /* CHIP_GT150_EINT */ 672*4882a593Smuzhiyun #define WM8400_CHIP_GT150_EINT_SHIFT 9 /* CHIP_GT150_EINT */ 673*4882a593Smuzhiyun #define WM8400_CHIP_GT150_EINT_WIDTH 1 /* CHIP_GT150_EINT */ 674*4882a593Smuzhiyun #define WM8400_CHIP_GT115_EINT 0x0100 /* CHIP_GT115_EINT */ 675*4882a593Smuzhiyun #define WM8400_CHIP_GT115_EINT_MASK 0x0100 /* CHIP_GT115_EINT */ 676*4882a593Smuzhiyun #define WM8400_CHIP_GT115_EINT_SHIFT 8 /* CHIP_GT115_EINT */ 677*4882a593Smuzhiyun #define WM8400_CHIP_GT115_EINT_WIDTH 1 /* CHIP_GT115_EINT */ 678*4882a593Smuzhiyun #define WM8400_LINE_CMP_EINT 0x0080 /* LINE_CMP_EINT */ 679*4882a593Smuzhiyun #define WM8400_LINE_CMP_EINT_MASK 0x0080 /* LINE_CMP_EINT */ 680*4882a593Smuzhiyun #define WM8400_LINE_CMP_EINT_SHIFT 7 /* LINE_CMP_EINT */ 681*4882a593Smuzhiyun #define WM8400_LINE_CMP_EINT_WIDTH 1 /* LINE_CMP_EINT */ 682*4882a593Smuzhiyun #define WM8400_UVLO_EINT 0x0040 /* UVLO_EINT */ 683*4882a593Smuzhiyun #define WM8400_UVLO_EINT_MASK 0x0040 /* UVLO_EINT */ 684*4882a593Smuzhiyun #define WM8400_UVLO_EINT_SHIFT 6 /* UVLO_EINT */ 685*4882a593Smuzhiyun #define WM8400_UVLO_EINT_WIDTH 1 /* UVLO_EINT */ 686*4882a593Smuzhiyun #define WM8400_DC2_UV_EINT 0x0020 /* DC2_UV_EINT */ 687*4882a593Smuzhiyun #define WM8400_DC2_UV_EINT_MASK 0x0020 /* DC2_UV_EINT */ 688*4882a593Smuzhiyun #define WM8400_DC2_UV_EINT_SHIFT 5 /* DC2_UV_EINT */ 689*4882a593Smuzhiyun #define WM8400_DC2_UV_EINT_WIDTH 1 /* DC2_UV_EINT */ 690*4882a593Smuzhiyun #define WM8400_DC1_UV_EINT 0x0010 /* DC1_UV_EINT */ 691*4882a593Smuzhiyun #define WM8400_DC1_UV_EINT_MASK 0x0010 /* DC1_UV_EINT */ 692*4882a593Smuzhiyun #define WM8400_DC1_UV_EINT_SHIFT 4 /* DC1_UV_EINT */ 693*4882a593Smuzhiyun #define WM8400_DC1_UV_EINT_WIDTH 1 /* DC1_UV_EINT */ 694*4882a593Smuzhiyun #define WM8400_LDO4_UV_EINT 0x0008 /* LDO4_UV_EINT */ 695*4882a593Smuzhiyun #define WM8400_LDO4_UV_EINT_MASK 0x0008 /* LDO4_UV_EINT */ 696*4882a593Smuzhiyun #define WM8400_LDO4_UV_EINT_SHIFT 3 /* LDO4_UV_EINT */ 697*4882a593Smuzhiyun #define WM8400_LDO4_UV_EINT_WIDTH 1 /* LDO4_UV_EINT */ 698*4882a593Smuzhiyun #define WM8400_LDO3_UV_EINT 0x0004 /* LDO3_UV_EINT */ 699*4882a593Smuzhiyun #define WM8400_LDO3_UV_EINT_MASK 0x0004 /* LDO3_UV_EINT */ 700*4882a593Smuzhiyun #define WM8400_LDO3_UV_EINT_SHIFT 2 /* LDO3_UV_EINT */ 701*4882a593Smuzhiyun #define WM8400_LDO3_UV_EINT_WIDTH 1 /* LDO3_UV_EINT */ 702*4882a593Smuzhiyun #define WM8400_LDO2_UV_EINT 0x0002 /* LDO2_UV_EINT */ 703*4882a593Smuzhiyun #define WM8400_LDO2_UV_EINT_MASK 0x0002 /* LDO2_UV_EINT */ 704*4882a593Smuzhiyun #define WM8400_LDO2_UV_EINT_SHIFT 1 /* LDO2_UV_EINT */ 705*4882a593Smuzhiyun #define WM8400_LDO2_UV_EINT_WIDTH 1 /* LDO2_UV_EINT */ 706*4882a593Smuzhiyun #define WM8400_LDO1_UV_EINT 0x0001 /* LDO1_UV_EINT */ 707*4882a593Smuzhiyun #define WM8400_LDO1_UV_EINT_MASK 0x0001 /* LDO1_UV_EINT */ 708*4882a593Smuzhiyun #define WM8400_LDO1_UV_EINT_SHIFT 0 /* LDO1_UV_EINT */ 709*4882a593Smuzhiyun #define WM8400_LDO1_UV_EINT_WIDTH 1 /* LDO1_UV_EINT */ 710*4882a593Smuzhiyun 711*4882a593Smuzhiyun /* 712*4882a593Smuzhiyun * R80 (0x50) - Interrupt Status 1 Mask 713*4882a593Smuzhiyun */ 714*4882a593Smuzhiyun #define WM8400_IM_MICD_CINT 0x8000 /* IM_MICD_CINT */ 715*4882a593Smuzhiyun #define WM8400_IM_MICD_CINT_MASK 0x8000 /* IM_MICD_CINT */ 716*4882a593Smuzhiyun #define WM8400_IM_MICD_CINT_SHIFT 15 /* IM_MICD_CINT */ 717*4882a593Smuzhiyun #define WM8400_IM_MICD_CINT_WIDTH 1 /* IM_MICD_CINT */ 718*4882a593Smuzhiyun #define WM8400_IM_MICSCD_CINT 0x4000 /* IM_MICSCD_CINT */ 719*4882a593Smuzhiyun #define WM8400_IM_MICSCD_CINT_MASK 0x4000 /* IM_MICSCD_CINT */ 720*4882a593Smuzhiyun #define WM8400_IM_MICSCD_CINT_SHIFT 14 /* IM_MICSCD_CINT */ 721*4882a593Smuzhiyun #define WM8400_IM_MICSCD_CINT_WIDTH 1 /* IM_MICSCD_CINT */ 722*4882a593Smuzhiyun #define WM8400_IM_JDL_CINT 0x2000 /* IM_JDL_CINT */ 723*4882a593Smuzhiyun #define WM8400_IM_JDL_CINT_MASK 0x2000 /* IM_JDL_CINT */ 724*4882a593Smuzhiyun #define WM8400_IM_JDL_CINT_SHIFT 13 /* IM_JDL_CINT */ 725*4882a593Smuzhiyun #define WM8400_IM_JDL_CINT_WIDTH 1 /* IM_JDL_CINT */ 726*4882a593Smuzhiyun #define WM8400_IM_JDR_CINT 0x1000 /* IM_JDR_CINT */ 727*4882a593Smuzhiyun #define WM8400_IM_JDR_CINT_MASK 0x1000 /* IM_JDR_CINT */ 728*4882a593Smuzhiyun #define WM8400_IM_JDR_CINT_SHIFT 12 /* IM_JDR_CINT */ 729*4882a593Smuzhiyun #define WM8400_IM_JDR_CINT_WIDTH 1 /* IM_JDR_CINT */ 730*4882a593Smuzhiyun #define WM8400_IM_CODEC_SEQ_END_EINT 0x0800 /* IM_CODEC_SEQ_END_EINT */ 731*4882a593Smuzhiyun #define WM8400_IM_CODEC_SEQ_END_EINT_MASK 0x0800 /* IM_CODEC_SEQ_END_EINT */ 732*4882a593Smuzhiyun #define WM8400_IM_CODEC_SEQ_END_EINT_SHIFT 11 /* IM_CODEC_SEQ_END_EINT */ 733*4882a593Smuzhiyun #define WM8400_IM_CODEC_SEQ_END_EINT_WIDTH 1 /* IM_CODEC_SEQ_END_EINT */ 734*4882a593Smuzhiyun #define WM8400_IM_CDEL_TO_EINT 0x0400 /* IM_CDEL_TO_EINT */ 735*4882a593Smuzhiyun #define WM8400_IM_CDEL_TO_EINT_MASK 0x0400 /* IM_CDEL_TO_EINT */ 736*4882a593Smuzhiyun #define WM8400_IM_CDEL_TO_EINT_SHIFT 10 /* IM_CDEL_TO_EINT */ 737*4882a593Smuzhiyun #define WM8400_IM_CDEL_TO_EINT_WIDTH 1 /* IM_CDEL_TO_EINT */ 738*4882a593Smuzhiyun #define WM8400_IM_CHIP_GT150_EINT 0x0200 /* IM_CHIP_GT150_EINT */ 739*4882a593Smuzhiyun #define WM8400_IM_CHIP_GT150_EINT_MASK 0x0200 /* IM_CHIP_GT150_EINT */ 740*4882a593Smuzhiyun #define WM8400_IM_CHIP_GT150_EINT_SHIFT 9 /* IM_CHIP_GT150_EINT */ 741*4882a593Smuzhiyun #define WM8400_IM_CHIP_GT150_EINT_WIDTH 1 /* IM_CHIP_GT150_EINT */ 742*4882a593Smuzhiyun #define WM8400_IM_CHIP_GT115_EINT 0x0100 /* IM_CHIP_GT115_EINT */ 743*4882a593Smuzhiyun #define WM8400_IM_CHIP_GT115_EINT_MASK 0x0100 /* IM_CHIP_GT115_EINT */ 744*4882a593Smuzhiyun #define WM8400_IM_CHIP_GT115_EINT_SHIFT 8 /* IM_CHIP_GT115_EINT */ 745*4882a593Smuzhiyun #define WM8400_IM_CHIP_GT115_EINT_WIDTH 1 /* IM_CHIP_GT115_EINT */ 746*4882a593Smuzhiyun #define WM8400_IM_LINE_CMP_EINT 0x0080 /* IM_LINE_CMP_EINT */ 747*4882a593Smuzhiyun #define WM8400_IM_LINE_CMP_EINT_MASK 0x0080 /* IM_LINE_CMP_EINT */ 748*4882a593Smuzhiyun #define WM8400_IM_LINE_CMP_EINT_SHIFT 7 /* IM_LINE_CMP_EINT */ 749*4882a593Smuzhiyun #define WM8400_IM_LINE_CMP_EINT_WIDTH 1 /* IM_LINE_CMP_EINT */ 750*4882a593Smuzhiyun #define WM8400_IM_UVLO_EINT 0x0040 /* IM_UVLO_EINT */ 751*4882a593Smuzhiyun #define WM8400_IM_UVLO_EINT_MASK 0x0040 /* IM_UVLO_EINT */ 752*4882a593Smuzhiyun #define WM8400_IM_UVLO_EINT_SHIFT 6 /* IM_UVLO_EINT */ 753*4882a593Smuzhiyun #define WM8400_IM_UVLO_EINT_WIDTH 1 /* IM_UVLO_EINT */ 754*4882a593Smuzhiyun #define WM8400_IM_DC2_UV_EINT 0x0020 /* IM_DC2_UV_EINT */ 755*4882a593Smuzhiyun #define WM8400_IM_DC2_UV_EINT_MASK 0x0020 /* IM_DC2_UV_EINT */ 756*4882a593Smuzhiyun #define WM8400_IM_DC2_UV_EINT_SHIFT 5 /* IM_DC2_UV_EINT */ 757*4882a593Smuzhiyun #define WM8400_IM_DC2_UV_EINT_WIDTH 1 /* IM_DC2_UV_EINT */ 758*4882a593Smuzhiyun #define WM8400_IM_DC1_UV_EINT 0x0010 /* IM_DC1_UV_EINT */ 759*4882a593Smuzhiyun #define WM8400_IM_DC1_UV_EINT_MASK 0x0010 /* IM_DC1_UV_EINT */ 760*4882a593Smuzhiyun #define WM8400_IM_DC1_UV_EINT_SHIFT 4 /* IM_DC1_UV_EINT */ 761*4882a593Smuzhiyun #define WM8400_IM_DC1_UV_EINT_WIDTH 1 /* IM_DC1_UV_EINT */ 762*4882a593Smuzhiyun #define WM8400_IM_LDO4_UV_EINT 0x0008 /* IM_LDO4_UV_EINT */ 763*4882a593Smuzhiyun #define WM8400_IM_LDO4_UV_EINT_MASK 0x0008 /* IM_LDO4_UV_EINT */ 764*4882a593Smuzhiyun #define WM8400_IM_LDO4_UV_EINT_SHIFT 3 /* IM_LDO4_UV_EINT */ 765*4882a593Smuzhiyun #define WM8400_IM_LDO4_UV_EINT_WIDTH 1 /* IM_LDO4_UV_EINT */ 766*4882a593Smuzhiyun #define WM8400_IM_LDO3_UV_EINT 0x0004 /* IM_LDO3_UV_EINT */ 767*4882a593Smuzhiyun #define WM8400_IM_LDO3_UV_EINT_MASK 0x0004 /* IM_LDO3_UV_EINT */ 768*4882a593Smuzhiyun #define WM8400_IM_LDO3_UV_EINT_SHIFT 2 /* IM_LDO3_UV_EINT */ 769*4882a593Smuzhiyun #define WM8400_IM_LDO3_UV_EINT_WIDTH 1 /* IM_LDO3_UV_EINT */ 770*4882a593Smuzhiyun #define WM8400_IM_LDO2_UV_EINT 0x0002 /* IM_LDO2_UV_EINT */ 771*4882a593Smuzhiyun #define WM8400_IM_LDO2_UV_EINT_MASK 0x0002 /* IM_LDO2_UV_EINT */ 772*4882a593Smuzhiyun #define WM8400_IM_LDO2_UV_EINT_SHIFT 1 /* IM_LDO2_UV_EINT */ 773*4882a593Smuzhiyun #define WM8400_IM_LDO2_UV_EINT_WIDTH 1 /* IM_LDO2_UV_EINT */ 774*4882a593Smuzhiyun #define WM8400_IM_LDO1_UV_EINT 0x0001 /* IM_LDO1_UV_EINT */ 775*4882a593Smuzhiyun #define WM8400_IM_LDO1_UV_EINT_MASK 0x0001 /* IM_LDO1_UV_EINT */ 776*4882a593Smuzhiyun #define WM8400_IM_LDO1_UV_EINT_SHIFT 0 /* IM_LDO1_UV_EINT */ 777*4882a593Smuzhiyun #define WM8400_IM_LDO1_UV_EINT_WIDTH 1 /* IM_LDO1_UV_EINT */ 778*4882a593Smuzhiyun 779*4882a593Smuzhiyun /* 780*4882a593Smuzhiyun * R81 (0x51) - Interrupt Levels 781*4882a593Smuzhiyun */ 782*4882a593Smuzhiyun #define WM8400_MICD_LVL 0x8000 /* MICD_LVL */ 783*4882a593Smuzhiyun #define WM8400_MICD_LVL_MASK 0x8000 /* MICD_LVL */ 784*4882a593Smuzhiyun #define WM8400_MICD_LVL_SHIFT 15 /* MICD_LVL */ 785*4882a593Smuzhiyun #define WM8400_MICD_LVL_WIDTH 1 /* MICD_LVL */ 786*4882a593Smuzhiyun #define WM8400_MICSCD_LVL 0x4000 /* MICSCD_LVL */ 787*4882a593Smuzhiyun #define WM8400_MICSCD_LVL_MASK 0x4000 /* MICSCD_LVL */ 788*4882a593Smuzhiyun #define WM8400_MICSCD_LVL_SHIFT 14 /* MICSCD_LVL */ 789*4882a593Smuzhiyun #define WM8400_MICSCD_LVL_WIDTH 1 /* MICSCD_LVL */ 790*4882a593Smuzhiyun #define WM8400_JDL_LVL 0x2000 /* JDL_LVL */ 791*4882a593Smuzhiyun #define WM8400_JDL_LVL_MASK 0x2000 /* JDL_LVL */ 792*4882a593Smuzhiyun #define WM8400_JDL_LVL_SHIFT 13 /* JDL_LVL */ 793*4882a593Smuzhiyun #define WM8400_JDL_LVL_WIDTH 1 /* JDL_LVL */ 794*4882a593Smuzhiyun #define WM8400_JDR_LVL 0x1000 /* JDR_LVL */ 795*4882a593Smuzhiyun #define WM8400_JDR_LVL_MASK 0x1000 /* JDR_LVL */ 796*4882a593Smuzhiyun #define WM8400_JDR_LVL_SHIFT 12 /* JDR_LVL */ 797*4882a593Smuzhiyun #define WM8400_JDR_LVL_WIDTH 1 /* JDR_LVL */ 798*4882a593Smuzhiyun #define WM8400_CODEC_SEQ_END_LVL 0x0800 /* CODEC_SEQ_END_LVL */ 799*4882a593Smuzhiyun #define WM8400_CODEC_SEQ_END_LVL_MASK 0x0800 /* CODEC_SEQ_END_LVL */ 800*4882a593Smuzhiyun #define WM8400_CODEC_SEQ_END_LVL_SHIFT 11 /* CODEC_SEQ_END_LVL */ 801*4882a593Smuzhiyun #define WM8400_CODEC_SEQ_END_LVL_WIDTH 1 /* CODEC_SEQ_END_LVL */ 802*4882a593Smuzhiyun #define WM8400_CDEL_TO_LVL 0x0400 /* CDEL_TO_LVL */ 803*4882a593Smuzhiyun #define WM8400_CDEL_TO_LVL_MASK 0x0400 /* CDEL_TO_LVL */ 804*4882a593Smuzhiyun #define WM8400_CDEL_TO_LVL_SHIFT 10 /* CDEL_TO_LVL */ 805*4882a593Smuzhiyun #define WM8400_CDEL_TO_LVL_WIDTH 1 /* CDEL_TO_LVL */ 806*4882a593Smuzhiyun #define WM8400_CHIP_GT150_LVL 0x0200 /* CHIP_GT150_LVL */ 807*4882a593Smuzhiyun #define WM8400_CHIP_GT150_LVL_MASK 0x0200 /* CHIP_GT150_LVL */ 808*4882a593Smuzhiyun #define WM8400_CHIP_GT150_LVL_SHIFT 9 /* CHIP_GT150_LVL */ 809*4882a593Smuzhiyun #define WM8400_CHIP_GT150_LVL_WIDTH 1 /* CHIP_GT150_LVL */ 810*4882a593Smuzhiyun #define WM8400_CHIP_GT115_LVL 0x0100 /* CHIP_GT115_LVL */ 811*4882a593Smuzhiyun #define WM8400_CHIP_GT115_LVL_MASK 0x0100 /* CHIP_GT115_LVL */ 812*4882a593Smuzhiyun #define WM8400_CHIP_GT115_LVL_SHIFT 8 /* CHIP_GT115_LVL */ 813*4882a593Smuzhiyun #define WM8400_CHIP_GT115_LVL_WIDTH 1 /* CHIP_GT115_LVL */ 814*4882a593Smuzhiyun #define WM8400_LINE_CMP_LVL 0x0080 /* LINE_CMP_LVL */ 815*4882a593Smuzhiyun #define WM8400_LINE_CMP_LVL_MASK 0x0080 /* LINE_CMP_LVL */ 816*4882a593Smuzhiyun #define WM8400_LINE_CMP_LVL_SHIFT 7 /* LINE_CMP_LVL */ 817*4882a593Smuzhiyun #define WM8400_LINE_CMP_LVL_WIDTH 1 /* LINE_CMP_LVL */ 818*4882a593Smuzhiyun #define WM8400_UVLO_LVL 0x0040 /* UVLO_LVL */ 819*4882a593Smuzhiyun #define WM8400_UVLO_LVL_MASK 0x0040 /* UVLO_LVL */ 820*4882a593Smuzhiyun #define WM8400_UVLO_LVL_SHIFT 6 /* UVLO_LVL */ 821*4882a593Smuzhiyun #define WM8400_UVLO_LVL_WIDTH 1 /* UVLO_LVL */ 822*4882a593Smuzhiyun #define WM8400_DC2_UV_LVL 0x0020 /* DC2_UV_LVL */ 823*4882a593Smuzhiyun #define WM8400_DC2_UV_LVL_MASK 0x0020 /* DC2_UV_LVL */ 824*4882a593Smuzhiyun #define WM8400_DC2_UV_LVL_SHIFT 5 /* DC2_UV_LVL */ 825*4882a593Smuzhiyun #define WM8400_DC2_UV_LVL_WIDTH 1 /* DC2_UV_LVL */ 826*4882a593Smuzhiyun #define WM8400_DC1_UV_LVL 0x0010 /* DC1_UV_LVL */ 827*4882a593Smuzhiyun #define WM8400_DC1_UV_LVL_MASK 0x0010 /* DC1_UV_LVL */ 828*4882a593Smuzhiyun #define WM8400_DC1_UV_LVL_SHIFT 4 /* DC1_UV_LVL */ 829*4882a593Smuzhiyun #define WM8400_DC1_UV_LVL_WIDTH 1 /* DC1_UV_LVL */ 830*4882a593Smuzhiyun #define WM8400_LDO4_UV_LVL 0x0008 /* LDO4_UV_LVL */ 831*4882a593Smuzhiyun #define WM8400_LDO4_UV_LVL_MASK 0x0008 /* LDO4_UV_LVL */ 832*4882a593Smuzhiyun #define WM8400_LDO4_UV_LVL_SHIFT 3 /* LDO4_UV_LVL */ 833*4882a593Smuzhiyun #define WM8400_LDO4_UV_LVL_WIDTH 1 /* LDO4_UV_LVL */ 834*4882a593Smuzhiyun #define WM8400_LDO3_UV_LVL 0x0004 /* LDO3_UV_LVL */ 835*4882a593Smuzhiyun #define WM8400_LDO3_UV_LVL_MASK 0x0004 /* LDO3_UV_LVL */ 836*4882a593Smuzhiyun #define WM8400_LDO3_UV_LVL_SHIFT 2 /* LDO3_UV_LVL */ 837*4882a593Smuzhiyun #define WM8400_LDO3_UV_LVL_WIDTH 1 /* LDO3_UV_LVL */ 838*4882a593Smuzhiyun #define WM8400_LDO2_UV_LVL 0x0002 /* LDO2_UV_LVL */ 839*4882a593Smuzhiyun #define WM8400_LDO2_UV_LVL_MASK 0x0002 /* LDO2_UV_LVL */ 840*4882a593Smuzhiyun #define WM8400_LDO2_UV_LVL_SHIFT 1 /* LDO2_UV_LVL */ 841*4882a593Smuzhiyun #define WM8400_LDO2_UV_LVL_WIDTH 1 /* LDO2_UV_LVL */ 842*4882a593Smuzhiyun #define WM8400_LDO1_UV_LVL 0x0001 /* LDO1_UV_LVL */ 843*4882a593Smuzhiyun #define WM8400_LDO1_UV_LVL_MASK 0x0001 /* LDO1_UV_LVL */ 844*4882a593Smuzhiyun #define WM8400_LDO1_UV_LVL_SHIFT 0 /* LDO1_UV_LVL */ 845*4882a593Smuzhiyun #define WM8400_LDO1_UV_LVL_WIDTH 1 /* LDO1_UV_LVL */ 846*4882a593Smuzhiyun 847*4882a593Smuzhiyun /* 848*4882a593Smuzhiyun * R82 (0x52) - Shutdown Reason 849*4882a593Smuzhiyun */ 850*4882a593Smuzhiyun #define WM8400_SDR_CHIP_SOFTSD 0x2000 /* SDR_CHIP_SOFTSD */ 851*4882a593Smuzhiyun #define WM8400_SDR_CHIP_SOFTSD_MASK 0x2000 /* SDR_CHIP_SOFTSD */ 852*4882a593Smuzhiyun #define WM8400_SDR_CHIP_SOFTSD_SHIFT 13 /* SDR_CHIP_SOFTSD */ 853*4882a593Smuzhiyun #define WM8400_SDR_CHIP_SOFTSD_WIDTH 1 /* SDR_CHIP_SOFTSD */ 854*4882a593Smuzhiyun #define WM8400_SDR_NPDN 0x0800 /* SDR_NPDN */ 855*4882a593Smuzhiyun #define WM8400_SDR_NPDN_MASK 0x0800 /* SDR_NPDN */ 856*4882a593Smuzhiyun #define WM8400_SDR_NPDN_SHIFT 11 /* SDR_NPDN */ 857*4882a593Smuzhiyun #define WM8400_SDR_NPDN_WIDTH 1 /* SDR_NPDN */ 858*4882a593Smuzhiyun #define WM8400_SDR_CHIP_GT150 0x0200 /* SDR_CHIP_GT150 */ 859*4882a593Smuzhiyun #define WM8400_SDR_CHIP_GT150_MASK 0x0200 /* SDR_CHIP_GT150 */ 860*4882a593Smuzhiyun #define WM8400_SDR_CHIP_GT150_SHIFT 9 /* SDR_CHIP_GT150 */ 861*4882a593Smuzhiyun #define WM8400_SDR_CHIP_GT150_WIDTH 1 /* SDR_CHIP_GT150 */ 862*4882a593Smuzhiyun #define WM8400_SDR_CHIP_GT115 0x0100 /* SDR_CHIP_GT115 */ 863*4882a593Smuzhiyun #define WM8400_SDR_CHIP_GT115_MASK 0x0100 /* SDR_CHIP_GT115 */ 864*4882a593Smuzhiyun #define WM8400_SDR_CHIP_GT115_SHIFT 8 /* SDR_CHIP_GT115 */ 865*4882a593Smuzhiyun #define WM8400_SDR_CHIP_GT115_WIDTH 1 /* SDR_CHIP_GT115 */ 866*4882a593Smuzhiyun #define WM8400_SDR_LINE_CMP 0x0080 /* SDR_LINE_CMP */ 867*4882a593Smuzhiyun #define WM8400_SDR_LINE_CMP_MASK 0x0080 /* SDR_LINE_CMP */ 868*4882a593Smuzhiyun #define WM8400_SDR_LINE_CMP_SHIFT 7 /* SDR_LINE_CMP */ 869*4882a593Smuzhiyun #define WM8400_SDR_LINE_CMP_WIDTH 1 /* SDR_LINE_CMP */ 870*4882a593Smuzhiyun #define WM8400_SDR_UVLO 0x0040 /* SDR_UVLO */ 871*4882a593Smuzhiyun #define WM8400_SDR_UVLO_MASK 0x0040 /* SDR_UVLO */ 872*4882a593Smuzhiyun #define WM8400_SDR_UVLO_SHIFT 6 /* SDR_UVLO */ 873*4882a593Smuzhiyun #define WM8400_SDR_UVLO_WIDTH 1 /* SDR_UVLO */ 874*4882a593Smuzhiyun #define WM8400_SDR_DC2_UV 0x0020 /* SDR_DC2_UV */ 875*4882a593Smuzhiyun #define WM8400_SDR_DC2_UV_MASK 0x0020 /* SDR_DC2_UV */ 876*4882a593Smuzhiyun #define WM8400_SDR_DC2_UV_SHIFT 5 /* SDR_DC2_UV */ 877*4882a593Smuzhiyun #define WM8400_SDR_DC2_UV_WIDTH 1 /* SDR_DC2_UV */ 878*4882a593Smuzhiyun #define WM8400_SDR_DC1_UV 0x0010 /* SDR_DC1_UV */ 879*4882a593Smuzhiyun #define WM8400_SDR_DC1_UV_MASK 0x0010 /* SDR_DC1_UV */ 880*4882a593Smuzhiyun #define WM8400_SDR_DC1_UV_SHIFT 4 /* SDR_DC1_UV */ 881*4882a593Smuzhiyun #define WM8400_SDR_DC1_UV_WIDTH 1 /* SDR_DC1_UV */ 882*4882a593Smuzhiyun #define WM8400_SDR_LDO4_UV 0x0008 /* SDR_LDO4_UV */ 883*4882a593Smuzhiyun #define WM8400_SDR_LDO4_UV_MASK 0x0008 /* SDR_LDO4_UV */ 884*4882a593Smuzhiyun #define WM8400_SDR_LDO4_UV_SHIFT 3 /* SDR_LDO4_UV */ 885*4882a593Smuzhiyun #define WM8400_SDR_LDO4_UV_WIDTH 1 /* SDR_LDO4_UV */ 886*4882a593Smuzhiyun #define WM8400_SDR_LDO3_UV 0x0004 /* SDR_LDO3_UV */ 887*4882a593Smuzhiyun #define WM8400_SDR_LDO3_UV_MASK 0x0004 /* SDR_LDO3_UV */ 888*4882a593Smuzhiyun #define WM8400_SDR_LDO3_UV_SHIFT 2 /* SDR_LDO3_UV */ 889*4882a593Smuzhiyun #define WM8400_SDR_LDO3_UV_WIDTH 1 /* SDR_LDO3_UV */ 890*4882a593Smuzhiyun #define WM8400_SDR_LDO2_UV 0x0002 /* SDR_LDO2_UV */ 891*4882a593Smuzhiyun #define WM8400_SDR_LDO2_UV_MASK 0x0002 /* SDR_LDO2_UV */ 892*4882a593Smuzhiyun #define WM8400_SDR_LDO2_UV_SHIFT 1 /* SDR_LDO2_UV */ 893*4882a593Smuzhiyun #define WM8400_SDR_LDO2_UV_WIDTH 1 /* SDR_LDO2_UV */ 894*4882a593Smuzhiyun #define WM8400_SDR_LDO1_UV 0x0001 /* SDR_LDO1_UV */ 895*4882a593Smuzhiyun #define WM8400_SDR_LDO1_UV_MASK 0x0001 /* SDR_LDO1_UV */ 896*4882a593Smuzhiyun #define WM8400_SDR_LDO1_UV_SHIFT 0 /* SDR_LDO1_UV */ 897*4882a593Smuzhiyun #define WM8400_SDR_LDO1_UV_WIDTH 1 /* SDR_LDO1_UV */ 898*4882a593Smuzhiyun 899*4882a593Smuzhiyun /* 900*4882a593Smuzhiyun * R84 (0x54) - Line Circuits 901*4882a593Smuzhiyun */ 902*4882a593Smuzhiyun #define WM8400_BG_LINE_COMP 0x8000 /* BG_LINE_COMP */ 903*4882a593Smuzhiyun #define WM8400_BG_LINE_COMP_MASK 0x8000 /* BG_LINE_COMP */ 904*4882a593Smuzhiyun #define WM8400_BG_LINE_COMP_SHIFT 15 /* BG_LINE_COMP */ 905*4882a593Smuzhiyun #define WM8400_BG_LINE_COMP_WIDTH 1 /* BG_LINE_COMP */ 906*4882a593Smuzhiyun #define WM8400_LINE_CMP_VTHI_MASK 0x00F0 /* LINE_CMP_VTHI - [7:4] */ 907*4882a593Smuzhiyun #define WM8400_LINE_CMP_VTHI_SHIFT 4 /* LINE_CMP_VTHI - [7:4] */ 908*4882a593Smuzhiyun #define WM8400_LINE_CMP_VTHI_WIDTH 4 /* LINE_CMP_VTHI - [7:4] */ 909*4882a593Smuzhiyun #define WM8400_LINE_CMP_VTHD_MASK 0x000F /* LINE_CMP_VTHD - [3:0] */ 910*4882a593Smuzhiyun #define WM8400_LINE_CMP_VTHD_SHIFT 0 /* LINE_CMP_VTHD - [3:0] */ 911*4882a593Smuzhiyun #define WM8400_LINE_CMP_VTHD_WIDTH 4 /* LINE_CMP_VTHD - [3:0] */ 912*4882a593Smuzhiyun 913*4882a593Smuzhiyun #endif 914