1*4882a593SmuzhiyunThis document describes the generic device tree binding for describing the 2*4882a593Smuzhiyunrelationship between PCI devices and MSI controllers. 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunEach PCI device under a root complex is uniquely identified by its Requester ID 5*4882a593Smuzhiyun(AKA RID). A Requester ID is a triplet of a Bus number, Device number, and 6*4882a593SmuzhiyunFunction number. 7*4882a593Smuzhiyun 8*4882a593SmuzhiyunFor the purpose of this document, when treated as a numeric value, a RID is 9*4882a593Smuzhiyunformatted such that: 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun* Bits [15:8] are the Bus number. 12*4882a593Smuzhiyun* Bits [7:3] are the Device number. 13*4882a593Smuzhiyun* Bits [2:0] are the Function number. 14*4882a593Smuzhiyun* Any other bits required for padding must be zero. 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunMSIs may be distinguished in part through the use of sideband data accompanying 17*4882a593Smuzhiyunwrites. In the case of PCI devices, this sideband data may be derived from the 18*4882a593SmuzhiyunRequester ID. A mechanism is required to associate a device with both the MSI 19*4882a593Smuzhiyuncontrollers it can address, and the sideband data that will be associated with 20*4882a593Smuzhiyunits writes to those controllers. 21*4882a593Smuzhiyun 22*4882a593SmuzhiyunFor generic MSI bindings, see 23*4882a593SmuzhiyunDocumentation/devicetree/bindings/interrupt-controller/msi.txt. 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun 26*4882a593SmuzhiyunPCI root complex 27*4882a593Smuzhiyun================ 28*4882a593Smuzhiyun 29*4882a593SmuzhiyunOptional properties 30*4882a593Smuzhiyun------------------- 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun- msi-map: Maps a Requester ID to an MSI controller and associated 33*4882a593Smuzhiyun msi-specifier data. The property is an arbitrary number of tuples of 34*4882a593Smuzhiyun (rid-base,msi-controller,msi-base,length), where: 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun * rid-base is a single cell describing the first RID matched by the entry. 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun * msi-controller is a single phandle to an MSI controller 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun * msi-base is an msi-specifier describing the msi-specifier produced for the 41*4882a593Smuzhiyun first RID matched by the entry. 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun * length is a single cell describing how many consecutive RIDs are matched 44*4882a593Smuzhiyun following the rid-base. 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun Any RID r in the interval [rid-base, rid-base + length) is associated with 47*4882a593Smuzhiyun the listed msi-controller, with the msi-specifier (r - rid-base + msi-base). 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun- msi-map-mask: A mask to be applied to each Requester ID prior to being mapped 50*4882a593Smuzhiyun to an msi-specifier per the msi-map property. 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun- msi-parent: Describes the MSI parent of the root complex itself. Where 53*4882a593Smuzhiyun the root complex and MSI controller do not pass sideband data with MSI 54*4882a593Smuzhiyun writes, this property may be used to describe the MSI controller(s) 55*4882a593Smuzhiyun used by PCI devices under the root complex, if defined as such in the 56*4882a593Smuzhiyun binding for the root complex. 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun 59*4882a593SmuzhiyunExample (1) 60*4882a593Smuzhiyun=========== 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun/ { 63*4882a593Smuzhiyun #address-cells = <1>; 64*4882a593Smuzhiyun #size-cells = <1>; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun msi: msi-controller@a { 67*4882a593Smuzhiyun reg = <0xa 0x1>; 68*4882a593Smuzhiyun compatible = "vendor,some-controller"; 69*4882a593Smuzhiyun msi-controller; 70*4882a593Smuzhiyun #msi-cells = <1>; 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun pci: pci@f { 74*4882a593Smuzhiyun reg = <0xf 0x1>; 75*4882a593Smuzhiyun compatible = "vendor,pcie-root-complex"; 76*4882a593Smuzhiyun device_type = "pci"; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun /* 79*4882a593Smuzhiyun * The sideband data provided to the MSI controller is 80*4882a593Smuzhiyun * the RID, identity-mapped. 81*4882a593Smuzhiyun */ 82*4882a593Smuzhiyun msi-map = <0x0 &msi_a 0x0 0x10000>, 83*4882a593Smuzhiyun }; 84*4882a593Smuzhiyun}; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun 87*4882a593SmuzhiyunExample (2) 88*4882a593Smuzhiyun=========== 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun/ { 91*4882a593Smuzhiyun #address-cells = <1>; 92*4882a593Smuzhiyun #size-cells = <1>; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun msi: msi-controller@a { 95*4882a593Smuzhiyun reg = <0xa 0x1>; 96*4882a593Smuzhiyun compatible = "vendor,some-controller"; 97*4882a593Smuzhiyun msi-controller; 98*4882a593Smuzhiyun #msi-cells = <1>; 99*4882a593Smuzhiyun }; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun pci: pci@f { 102*4882a593Smuzhiyun reg = <0xf 0x1>; 103*4882a593Smuzhiyun compatible = "vendor,pcie-root-complex"; 104*4882a593Smuzhiyun device_type = "pci"; 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun /* 107*4882a593Smuzhiyun * The sideband data provided to the MSI controller is 108*4882a593Smuzhiyun * the RID, masked to only the device and function bits. 109*4882a593Smuzhiyun */ 110*4882a593Smuzhiyun msi-map = <0x0 &msi_a 0x0 0x100>, 111*4882a593Smuzhiyun msi-map-mask = <0xff> 112*4882a593Smuzhiyun }; 113*4882a593Smuzhiyun}; 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun 116*4882a593SmuzhiyunExample (3) 117*4882a593Smuzhiyun=========== 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun/ { 120*4882a593Smuzhiyun #address-cells = <1>; 121*4882a593Smuzhiyun #size-cells = <1>; 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun msi: msi-controller@a { 124*4882a593Smuzhiyun reg = <0xa 0x1>; 125*4882a593Smuzhiyun compatible = "vendor,some-controller"; 126*4882a593Smuzhiyun msi-controller; 127*4882a593Smuzhiyun #msi-cells = <1>; 128*4882a593Smuzhiyun }; 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun pci: pci@f { 131*4882a593Smuzhiyun reg = <0xf 0x1>; 132*4882a593Smuzhiyun compatible = "vendor,pcie-root-complex"; 133*4882a593Smuzhiyun device_type = "pci"; 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun /* 136*4882a593Smuzhiyun * The sideband data provided to the MSI controller is 137*4882a593Smuzhiyun * the RID, but the high bit of the bus number is 138*4882a593Smuzhiyun * ignored. 139*4882a593Smuzhiyun */ 140*4882a593Smuzhiyun msi-map = <0x0000 &msi 0x0000 0x8000>, 141*4882a593Smuzhiyun <0x8000 &msi 0x0000 0x8000>; 142*4882a593Smuzhiyun }; 143*4882a593Smuzhiyun}; 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun 146*4882a593SmuzhiyunExample (4) 147*4882a593Smuzhiyun=========== 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun/ { 150*4882a593Smuzhiyun #address-cells = <1>; 151*4882a593Smuzhiyun #size-cells = <1>; 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun msi: msi-controller@a { 154*4882a593Smuzhiyun reg = <0xa 0x1>; 155*4882a593Smuzhiyun compatible = "vendor,some-controller"; 156*4882a593Smuzhiyun msi-controller; 157*4882a593Smuzhiyun #msi-cells = <1>; 158*4882a593Smuzhiyun }; 159*4882a593Smuzhiyun 160*4882a593Smuzhiyun pci: pci@f { 161*4882a593Smuzhiyun reg = <0xf 0x1>; 162*4882a593Smuzhiyun compatible = "vendor,pcie-root-complex"; 163*4882a593Smuzhiyun device_type = "pci"; 164*4882a593Smuzhiyun 165*4882a593Smuzhiyun /* 166*4882a593Smuzhiyun * The sideband data provided to the MSI controller is 167*4882a593Smuzhiyun * the RID, but the high bit of the bus number is 168*4882a593Smuzhiyun * negated. 169*4882a593Smuzhiyun */ 170*4882a593Smuzhiyun msi-map = <0x0000 &msi 0x8000 0x8000>, 171*4882a593Smuzhiyun <0x8000 &msi 0x0000 0x8000>; 172*4882a593Smuzhiyun }; 173*4882a593Smuzhiyun}; 174*4882a593Smuzhiyun 175*4882a593Smuzhiyun 176*4882a593SmuzhiyunExample (5) 177*4882a593Smuzhiyun=========== 178*4882a593Smuzhiyun 179*4882a593Smuzhiyun/ { 180*4882a593Smuzhiyun #address-cells = <1>; 181*4882a593Smuzhiyun #size-cells = <1>; 182*4882a593Smuzhiyun 183*4882a593Smuzhiyun msi_a: msi-controller@a { 184*4882a593Smuzhiyun reg = <0xa 0x1>; 185*4882a593Smuzhiyun compatible = "vendor,some-controller"; 186*4882a593Smuzhiyun msi-controller; 187*4882a593Smuzhiyun #msi-cells = <1>; 188*4882a593Smuzhiyun }; 189*4882a593Smuzhiyun 190*4882a593Smuzhiyun msi_b: msi-controller@b { 191*4882a593Smuzhiyun reg = <0xb 0x1>; 192*4882a593Smuzhiyun compatible = "vendor,some-controller"; 193*4882a593Smuzhiyun msi-controller; 194*4882a593Smuzhiyun #msi-cells = <1>; 195*4882a593Smuzhiyun }; 196*4882a593Smuzhiyun 197*4882a593Smuzhiyun msi_c: msi-controller@c { 198*4882a593Smuzhiyun reg = <0xc 0x1>; 199*4882a593Smuzhiyun compatible = "vendor,some-controller"; 200*4882a593Smuzhiyun msi-controller; 201*4882a593Smuzhiyun #msi-cells = <1>; 202*4882a593Smuzhiyun }; 203*4882a593Smuzhiyun 204*4882a593Smuzhiyun pci: pci@f { 205*4882a593Smuzhiyun reg = <0xf 0x1>; 206*4882a593Smuzhiyun compatible = "vendor,pcie-root-complex"; 207*4882a593Smuzhiyun device_type = "pci"; 208*4882a593Smuzhiyun 209*4882a593Smuzhiyun /* 210*4882a593Smuzhiyun * The sideband data provided to MSI controller a is the 211*4882a593Smuzhiyun * RID, but the high bit of the bus number is negated. 212*4882a593Smuzhiyun * The sideband data provided to MSI controller b is the 213*4882a593Smuzhiyun * RID, identity-mapped. 214*4882a593Smuzhiyun * MSI controller c is not addressable. 215*4882a593Smuzhiyun */ 216*4882a593Smuzhiyun msi-map = <0x0000 &msi_a 0x8000 0x08000>, 217*4882a593Smuzhiyun <0x8000 &msi_a 0x0000 0x08000>, 218*4882a593Smuzhiyun <0x0000 &msi_b 0x0000 0x10000>; 219*4882a593Smuzhiyun }; 220*4882a593Smuzhiyun}; 221