1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Wolfson WM97xx -- Core device
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2017 Robert Jarzmik
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Features:
8*4882a593Smuzhiyun * - an AC97 audio codec
9*4882a593Smuzhiyun * - a touchscreen driver
10*4882a593Smuzhiyun * - a GPIO block
11*4882a593Smuzhiyun */
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include <linux/device.h>
14*4882a593Smuzhiyun #include <linux/mfd/core.h>
15*4882a593Smuzhiyun #include <linux/mfd/wm97xx.h>
16*4882a593Smuzhiyun #include <linux/module.h>
17*4882a593Smuzhiyun #include <linux/regmap.h>
18*4882a593Smuzhiyun #include <linux/slab.h>
19*4882a593Smuzhiyun #include <linux/wm97xx.h>
20*4882a593Smuzhiyun #include <sound/ac97/codec.h>
21*4882a593Smuzhiyun #include <sound/ac97/compat.h>
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #define WM9705_VENDOR_ID 0x574d4c05
24*4882a593Smuzhiyun #define WM9712_VENDOR_ID 0x574d4c12
25*4882a593Smuzhiyun #define WM9713_VENDOR_ID 0x574d4c13
26*4882a593Smuzhiyun #define WM97xx_VENDOR_ID_MASK 0xffffffff
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun struct wm97xx_priv {
29*4882a593Smuzhiyun struct regmap *regmap;
30*4882a593Smuzhiyun struct snd_ac97 *ac97;
31*4882a593Smuzhiyun struct device *dev;
32*4882a593Smuzhiyun struct wm97xx_platform_data codec_pdata;
33*4882a593Smuzhiyun };
34*4882a593Smuzhiyun
wm97xx_readable_reg(struct device * dev,unsigned int reg)35*4882a593Smuzhiyun static bool wm97xx_readable_reg(struct device *dev, unsigned int reg)
36*4882a593Smuzhiyun {
37*4882a593Smuzhiyun switch (reg) {
38*4882a593Smuzhiyun case AC97_RESET ... AC97_PCM_SURR_DAC_RATE:
39*4882a593Smuzhiyun case AC97_PCM_LR_ADC_RATE:
40*4882a593Smuzhiyun case AC97_CENTER_LFE_MASTER:
41*4882a593Smuzhiyun case AC97_SPDIF ... AC97_LINE1_LEVEL:
42*4882a593Smuzhiyun case AC97_GPIO_CFG ... 0x5c:
43*4882a593Smuzhiyun case AC97_CODEC_CLASS_REV ... AC97_PCI_SID:
44*4882a593Smuzhiyun case 0x74 ... AC97_VENDOR_ID2:
45*4882a593Smuzhiyun return true;
46*4882a593Smuzhiyun default:
47*4882a593Smuzhiyun return false;
48*4882a593Smuzhiyun }
49*4882a593Smuzhiyun }
50*4882a593Smuzhiyun
wm97xx_writeable_reg(struct device * dev,unsigned int reg)51*4882a593Smuzhiyun static bool wm97xx_writeable_reg(struct device *dev, unsigned int reg)
52*4882a593Smuzhiyun {
53*4882a593Smuzhiyun switch (reg) {
54*4882a593Smuzhiyun case AC97_VENDOR_ID1:
55*4882a593Smuzhiyun case AC97_VENDOR_ID2:
56*4882a593Smuzhiyun return false;
57*4882a593Smuzhiyun default:
58*4882a593Smuzhiyun return wm97xx_readable_reg(dev, reg);
59*4882a593Smuzhiyun }
60*4882a593Smuzhiyun }
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun static const struct reg_default wm9705_reg_defaults[] = {
63*4882a593Smuzhiyun { 0x02, 0x8000 },
64*4882a593Smuzhiyun { 0x04, 0x8000 },
65*4882a593Smuzhiyun { 0x06, 0x8000 },
66*4882a593Smuzhiyun { 0x0a, 0x8000 },
67*4882a593Smuzhiyun { 0x0c, 0x8008 },
68*4882a593Smuzhiyun { 0x0e, 0x8008 },
69*4882a593Smuzhiyun { 0x10, 0x8808 },
70*4882a593Smuzhiyun { 0x12, 0x8808 },
71*4882a593Smuzhiyun { 0x14, 0x8808 },
72*4882a593Smuzhiyun { 0x16, 0x8808 },
73*4882a593Smuzhiyun { 0x18, 0x8808 },
74*4882a593Smuzhiyun { 0x1a, 0x0000 },
75*4882a593Smuzhiyun { 0x1c, 0x8000 },
76*4882a593Smuzhiyun { 0x20, 0x0000 },
77*4882a593Smuzhiyun { 0x22, 0x0000 },
78*4882a593Smuzhiyun { 0x26, 0x000f },
79*4882a593Smuzhiyun { 0x28, 0x0605 },
80*4882a593Smuzhiyun { 0x2a, 0x0000 },
81*4882a593Smuzhiyun { 0x2c, 0xbb80 },
82*4882a593Smuzhiyun { 0x32, 0xbb80 },
83*4882a593Smuzhiyun { 0x34, 0x2000 },
84*4882a593Smuzhiyun { 0x5a, 0x0000 },
85*4882a593Smuzhiyun { 0x5c, 0x0000 },
86*4882a593Smuzhiyun { 0x72, 0x0808 },
87*4882a593Smuzhiyun { 0x74, 0x0000 },
88*4882a593Smuzhiyun { 0x76, 0x0006 },
89*4882a593Smuzhiyun { 0x78, 0x0000 },
90*4882a593Smuzhiyun { 0x7a, 0x0000 },
91*4882a593Smuzhiyun };
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun static const struct regmap_config wm9705_regmap_config = {
94*4882a593Smuzhiyun .reg_bits = 16,
95*4882a593Smuzhiyun .reg_stride = 2,
96*4882a593Smuzhiyun .val_bits = 16,
97*4882a593Smuzhiyun .max_register = 0x7e,
98*4882a593Smuzhiyun .cache_type = REGCACHE_RBTREE,
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun .reg_defaults = wm9705_reg_defaults,
101*4882a593Smuzhiyun .num_reg_defaults = ARRAY_SIZE(wm9705_reg_defaults),
102*4882a593Smuzhiyun .volatile_reg = regmap_ac97_default_volatile,
103*4882a593Smuzhiyun .readable_reg = wm97xx_readable_reg,
104*4882a593Smuzhiyun .writeable_reg = wm97xx_writeable_reg,
105*4882a593Smuzhiyun };
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun static struct mfd_cell wm9705_cells[] = {
108*4882a593Smuzhiyun { .name = "wm9705-codec", },
109*4882a593Smuzhiyun { .name = "wm97xx-ts", },
110*4882a593Smuzhiyun };
111*4882a593Smuzhiyun
wm9712_volatile_reg(struct device * dev,unsigned int reg)112*4882a593Smuzhiyun static bool wm9712_volatile_reg(struct device *dev, unsigned int reg)
113*4882a593Smuzhiyun {
114*4882a593Smuzhiyun switch (reg) {
115*4882a593Smuzhiyun case AC97_REC_GAIN:
116*4882a593Smuzhiyun return true;
117*4882a593Smuzhiyun default:
118*4882a593Smuzhiyun return regmap_ac97_default_volatile(dev, reg);
119*4882a593Smuzhiyun }
120*4882a593Smuzhiyun }
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun static const struct reg_default wm9712_reg_defaults[] = {
123*4882a593Smuzhiyun { 0x02, 0x8000 },
124*4882a593Smuzhiyun { 0x04, 0x8000 },
125*4882a593Smuzhiyun { 0x06, 0x8000 },
126*4882a593Smuzhiyun { 0x08, 0x0f0f },
127*4882a593Smuzhiyun { 0x0a, 0xaaa0 },
128*4882a593Smuzhiyun { 0x0c, 0xc008 },
129*4882a593Smuzhiyun { 0x0e, 0x6808 },
130*4882a593Smuzhiyun { 0x10, 0xe808 },
131*4882a593Smuzhiyun { 0x12, 0xaaa0 },
132*4882a593Smuzhiyun { 0x14, 0xad00 },
133*4882a593Smuzhiyun { 0x16, 0x8000 },
134*4882a593Smuzhiyun { 0x18, 0xe808 },
135*4882a593Smuzhiyun { 0x1a, 0x3000 },
136*4882a593Smuzhiyun { 0x1c, 0x8000 },
137*4882a593Smuzhiyun { 0x20, 0x0000 },
138*4882a593Smuzhiyun { 0x22, 0x0000 },
139*4882a593Smuzhiyun { 0x26, 0x000f },
140*4882a593Smuzhiyun { 0x28, 0x0605 },
141*4882a593Smuzhiyun { 0x2a, 0x0410 },
142*4882a593Smuzhiyun { 0x2c, 0xbb80 },
143*4882a593Smuzhiyun { 0x2e, 0xbb80 },
144*4882a593Smuzhiyun { 0x32, 0xbb80 },
145*4882a593Smuzhiyun { 0x34, 0x2000 },
146*4882a593Smuzhiyun { 0x4c, 0xf83e },
147*4882a593Smuzhiyun { 0x4e, 0xffff },
148*4882a593Smuzhiyun { 0x50, 0x0000 },
149*4882a593Smuzhiyun { 0x52, 0x0000 },
150*4882a593Smuzhiyun { 0x56, 0xf83e },
151*4882a593Smuzhiyun { 0x58, 0x0008 },
152*4882a593Smuzhiyun { 0x5c, 0x0000 },
153*4882a593Smuzhiyun { 0x60, 0xb032 },
154*4882a593Smuzhiyun { 0x62, 0x3e00 },
155*4882a593Smuzhiyun { 0x64, 0x0000 },
156*4882a593Smuzhiyun { 0x76, 0x0006 },
157*4882a593Smuzhiyun { 0x78, 0x0001 },
158*4882a593Smuzhiyun { 0x7a, 0x0000 },
159*4882a593Smuzhiyun };
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun static const struct regmap_config wm9712_regmap_config = {
162*4882a593Smuzhiyun .reg_bits = 16,
163*4882a593Smuzhiyun .reg_stride = 2,
164*4882a593Smuzhiyun .val_bits = 16,
165*4882a593Smuzhiyun .max_register = 0x7e,
166*4882a593Smuzhiyun .cache_type = REGCACHE_RBTREE,
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun .reg_defaults = wm9712_reg_defaults,
169*4882a593Smuzhiyun .num_reg_defaults = ARRAY_SIZE(wm9712_reg_defaults),
170*4882a593Smuzhiyun .volatile_reg = wm9712_volatile_reg,
171*4882a593Smuzhiyun .readable_reg = wm97xx_readable_reg,
172*4882a593Smuzhiyun .writeable_reg = wm97xx_writeable_reg,
173*4882a593Smuzhiyun };
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun static struct mfd_cell wm9712_cells[] = {
176*4882a593Smuzhiyun { .name = "wm9712-codec", },
177*4882a593Smuzhiyun { .name = "wm97xx-ts", },
178*4882a593Smuzhiyun };
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun static const struct reg_default wm9713_reg_defaults[] = {
181*4882a593Smuzhiyun { 0x02, 0x8080 }, /* Speaker Output Volume */
182*4882a593Smuzhiyun { 0x04, 0x8080 }, /* Headphone Output Volume */
183*4882a593Smuzhiyun { 0x06, 0x8080 }, /* Out3/OUT4 Volume */
184*4882a593Smuzhiyun { 0x08, 0xc880 }, /* Mono Volume */
185*4882a593Smuzhiyun { 0x0a, 0xe808 }, /* LINEIN Volume */
186*4882a593Smuzhiyun { 0x0c, 0xe808 }, /* DAC PGA Volume */
187*4882a593Smuzhiyun { 0x0e, 0x0808 }, /* MIC PGA Volume */
188*4882a593Smuzhiyun { 0x10, 0x00da }, /* MIC Routing Control */
189*4882a593Smuzhiyun { 0x12, 0x8000 }, /* Record PGA Volume */
190*4882a593Smuzhiyun { 0x14, 0xd600 }, /* Record Routing */
191*4882a593Smuzhiyun { 0x16, 0xaaa0 }, /* PCBEEP Volume */
192*4882a593Smuzhiyun { 0x18, 0xaaa0 }, /* VxDAC Volume */
193*4882a593Smuzhiyun { 0x1a, 0xaaa0 }, /* AUXDAC Volume */
194*4882a593Smuzhiyun { 0x1c, 0x0000 }, /* Output PGA Mux */
195*4882a593Smuzhiyun { 0x1e, 0x0000 }, /* DAC 3D control */
196*4882a593Smuzhiyun { 0x20, 0x0f0f }, /* DAC Tone Control*/
197*4882a593Smuzhiyun { 0x22, 0x0040 }, /* MIC Input Select & Bias */
198*4882a593Smuzhiyun { 0x24, 0x0000 }, /* Output Volume Mapping & Jack */
199*4882a593Smuzhiyun { 0x26, 0x7f00 }, /* Powerdown Ctrl/Stat*/
200*4882a593Smuzhiyun { 0x28, 0x0405 }, /* Extended Audio ID */
201*4882a593Smuzhiyun { 0x2a, 0x0410 }, /* Extended Audio Start/Ctrl */
202*4882a593Smuzhiyun { 0x2c, 0xbb80 }, /* Audio DACs Sample Rate */
203*4882a593Smuzhiyun { 0x2e, 0xbb80 }, /* AUXDAC Sample Rate */
204*4882a593Smuzhiyun { 0x32, 0xbb80 }, /* Audio ADCs Sample Rate */
205*4882a593Smuzhiyun { 0x36, 0x4523 }, /* PCM codec control */
206*4882a593Smuzhiyun { 0x3a, 0x2000 }, /* SPDIF control */
207*4882a593Smuzhiyun { 0x3c, 0xfdff }, /* Powerdown 1 */
208*4882a593Smuzhiyun { 0x3e, 0xffff }, /* Powerdown 2 */
209*4882a593Smuzhiyun { 0x40, 0x0000 }, /* General Purpose */
210*4882a593Smuzhiyun { 0x42, 0x0000 }, /* Fast Power-Up Control */
211*4882a593Smuzhiyun { 0x44, 0x0080 }, /* MCLK/PLL Control */
212*4882a593Smuzhiyun { 0x46, 0x0000 }, /* MCLK/PLL Control */
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun { 0x4c, 0xfffe }, /* GPIO Pin Configuration */
215*4882a593Smuzhiyun { 0x4e, 0xffff }, /* GPIO Pin Polarity / Type */
216*4882a593Smuzhiyun { 0x50, 0x0000 }, /* GPIO Pin Sticky */
217*4882a593Smuzhiyun { 0x52, 0x0000 }, /* GPIO Pin Wake-Up */
218*4882a593Smuzhiyun /* GPIO Pin Status */
219*4882a593Smuzhiyun { 0x56, 0xfffe }, /* GPIO Pin Sharing */
220*4882a593Smuzhiyun { 0x58, 0x4000 }, /* GPIO PullUp/PullDown */
221*4882a593Smuzhiyun { 0x5a, 0x0000 }, /* Additional Functions 1 */
222*4882a593Smuzhiyun { 0x5c, 0x0000 }, /* Additional Functions 2 */
223*4882a593Smuzhiyun { 0x60, 0xb032 }, /* ALC Control */
224*4882a593Smuzhiyun { 0x62, 0x3e00 }, /* ALC / Noise Gate Control */
225*4882a593Smuzhiyun { 0x64, 0x0000 }, /* AUXDAC input control */
226*4882a593Smuzhiyun { 0x74, 0x0000 }, /* Digitiser Reg 1 */
227*4882a593Smuzhiyun { 0x76, 0x0006 }, /* Digitiser Reg 2 */
228*4882a593Smuzhiyun { 0x78, 0x0001 }, /* Digitiser Reg 3 */
229*4882a593Smuzhiyun { 0x7a, 0x0000 }, /* Digitiser Read Back */
230*4882a593Smuzhiyun };
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun static const struct regmap_config wm9713_regmap_config = {
233*4882a593Smuzhiyun .reg_bits = 16,
234*4882a593Smuzhiyun .reg_stride = 2,
235*4882a593Smuzhiyun .val_bits = 16,
236*4882a593Smuzhiyun .max_register = 0x7e,
237*4882a593Smuzhiyun .cache_type = REGCACHE_RBTREE,
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun .reg_defaults = wm9713_reg_defaults,
240*4882a593Smuzhiyun .num_reg_defaults = ARRAY_SIZE(wm9713_reg_defaults),
241*4882a593Smuzhiyun .volatile_reg = regmap_ac97_default_volatile,
242*4882a593Smuzhiyun .readable_reg = wm97xx_readable_reg,
243*4882a593Smuzhiyun .writeable_reg = wm97xx_writeable_reg,
244*4882a593Smuzhiyun };
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun static struct mfd_cell wm9713_cells[] = {
247*4882a593Smuzhiyun { .name = "wm9713-codec", },
248*4882a593Smuzhiyun { .name = "wm97xx-ts", },
249*4882a593Smuzhiyun };
250*4882a593Smuzhiyun
wm97xx_ac97_probe(struct ac97_codec_device * adev)251*4882a593Smuzhiyun static int wm97xx_ac97_probe(struct ac97_codec_device *adev)
252*4882a593Smuzhiyun {
253*4882a593Smuzhiyun struct wm97xx_priv *wm97xx;
254*4882a593Smuzhiyun const struct regmap_config *config;
255*4882a593Smuzhiyun struct wm97xx_platform_data *codec_pdata;
256*4882a593Smuzhiyun struct mfd_cell *cells;
257*4882a593Smuzhiyun int ret = -ENODEV, nb_cells, i;
258*4882a593Smuzhiyun struct wm97xx_pdata *pdata = snd_ac97_codec_get_platdata(adev);
259*4882a593Smuzhiyun
260*4882a593Smuzhiyun wm97xx = devm_kzalloc(ac97_codec_dev2dev(adev),
261*4882a593Smuzhiyun sizeof(*wm97xx), GFP_KERNEL);
262*4882a593Smuzhiyun if (!wm97xx)
263*4882a593Smuzhiyun return -ENOMEM;
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun wm97xx->dev = ac97_codec_dev2dev(adev);
266*4882a593Smuzhiyun wm97xx->ac97 = snd_ac97_compat_alloc(adev);
267*4882a593Smuzhiyun if (IS_ERR(wm97xx->ac97))
268*4882a593Smuzhiyun return PTR_ERR(wm97xx->ac97);
269*4882a593Smuzhiyun
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun ac97_set_drvdata(adev, wm97xx);
272*4882a593Smuzhiyun dev_info(wm97xx->dev, "wm97xx core found, id=0x%x\n",
273*4882a593Smuzhiyun adev->vendor_id);
274*4882a593Smuzhiyun
275*4882a593Smuzhiyun codec_pdata = &wm97xx->codec_pdata;
276*4882a593Smuzhiyun codec_pdata->ac97 = wm97xx->ac97;
277*4882a593Smuzhiyun codec_pdata->batt_pdata = pdata ? pdata->batt_pdata : NULL;
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun switch (adev->vendor_id) {
280*4882a593Smuzhiyun case WM9705_VENDOR_ID:
281*4882a593Smuzhiyun config = &wm9705_regmap_config;
282*4882a593Smuzhiyun cells = wm9705_cells;
283*4882a593Smuzhiyun nb_cells = ARRAY_SIZE(wm9705_cells);
284*4882a593Smuzhiyun break;
285*4882a593Smuzhiyun case WM9712_VENDOR_ID:
286*4882a593Smuzhiyun config = &wm9712_regmap_config;
287*4882a593Smuzhiyun cells = wm9712_cells;
288*4882a593Smuzhiyun nb_cells = ARRAY_SIZE(wm9712_cells);
289*4882a593Smuzhiyun break;
290*4882a593Smuzhiyun case WM9713_VENDOR_ID:
291*4882a593Smuzhiyun config = &wm9713_regmap_config;
292*4882a593Smuzhiyun cells = wm9713_cells;
293*4882a593Smuzhiyun nb_cells = ARRAY_SIZE(wm9713_cells);
294*4882a593Smuzhiyun break;
295*4882a593Smuzhiyun default:
296*4882a593Smuzhiyun goto err_free_compat;
297*4882a593Smuzhiyun }
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun for (i = 0; i < nb_cells; i++) {
300*4882a593Smuzhiyun cells[i].platform_data = codec_pdata;
301*4882a593Smuzhiyun cells[i].pdata_size = sizeof(*codec_pdata);
302*4882a593Smuzhiyun }
303*4882a593Smuzhiyun
304*4882a593Smuzhiyun codec_pdata->regmap = devm_regmap_init_ac97(wm97xx->ac97, config);
305*4882a593Smuzhiyun if (IS_ERR(codec_pdata->regmap)) {
306*4882a593Smuzhiyun ret = PTR_ERR(codec_pdata->regmap);
307*4882a593Smuzhiyun goto err_free_compat;
308*4882a593Smuzhiyun }
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun ret = devm_mfd_add_devices(wm97xx->dev, PLATFORM_DEVID_NONE,
311*4882a593Smuzhiyun cells, nb_cells, NULL, 0, NULL);
312*4882a593Smuzhiyun if (ret)
313*4882a593Smuzhiyun goto err_free_compat;
314*4882a593Smuzhiyun
315*4882a593Smuzhiyun return ret;
316*4882a593Smuzhiyun
317*4882a593Smuzhiyun err_free_compat:
318*4882a593Smuzhiyun snd_ac97_compat_release(wm97xx->ac97);
319*4882a593Smuzhiyun return ret;
320*4882a593Smuzhiyun }
321*4882a593Smuzhiyun
wm97xx_ac97_remove(struct ac97_codec_device * adev)322*4882a593Smuzhiyun static int wm97xx_ac97_remove(struct ac97_codec_device *adev)
323*4882a593Smuzhiyun {
324*4882a593Smuzhiyun struct wm97xx_priv *wm97xx = ac97_get_drvdata(adev);
325*4882a593Smuzhiyun
326*4882a593Smuzhiyun snd_ac97_compat_release(wm97xx->ac97);
327*4882a593Smuzhiyun
328*4882a593Smuzhiyun return 0;
329*4882a593Smuzhiyun }
330*4882a593Smuzhiyun
331*4882a593Smuzhiyun static const struct ac97_id wm97xx_ac97_ids[] = {
332*4882a593Smuzhiyun { .id = WM9705_VENDOR_ID, .mask = WM97xx_VENDOR_ID_MASK },
333*4882a593Smuzhiyun { .id = WM9712_VENDOR_ID, .mask = WM97xx_VENDOR_ID_MASK },
334*4882a593Smuzhiyun { .id = WM9713_VENDOR_ID, .mask = WM97xx_VENDOR_ID_MASK },
335*4882a593Smuzhiyun { }
336*4882a593Smuzhiyun };
337*4882a593Smuzhiyun
338*4882a593Smuzhiyun static struct ac97_codec_driver wm97xx_ac97_driver = {
339*4882a593Smuzhiyun .driver = {
340*4882a593Smuzhiyun .name = "wm97xx-core",
341*4882a593Smuzhiyun },
342*4882a593Smuzhiyun .probe = wm97xx_ac97_probe,
343*4882a593Smuzhiyun .remove = wm97xx_ac97_remove,
344*4882a593Smuzhiyun .id_table = wm97xx_ac97_ids,
345*4882a593Smuzhiyun };
346*4882a593Smuzhiyun
wm97xx_module_init(void)347*4882a593Smuzhiyun static int __init wm97xx_module_init(void)
348*4882a593Smuzhiyun {
349*4882a593Smuzhiyun return snd_ac97_codec_driver_register(&wm97xx_ac97_driver);
350*4882a593Smuzhiyun }
351*4882a593Smuzhiyun module_init(wm97xx_module_init);
352*4882a593Smuzhiyun
wm97xx_module_exit(void)353*4882a593Smuzhiyun static void __exit wm97xx_module_exit(void)
354*4882a593Smuzhiyun {
355*4882a593Smuzhiyun snd_ac97_codec_driver_unregister(&wm97xx_ac97_driver);
356*4882a593Smuzhiyun }
357*4882a593Smuzhiyun module_exit(wm97xx_module_exit);
358*4882a593Smuzhiyun
359*4882a593Smuzhiyun MODULE_DESCRIPTION("WM9712, WM9713 core driver");
360*4882a593Smuzhiyun MODULE_AUTHOR("Robert Jarzmik <robert.jarzmik@free.fr>");
361*4882a593Smuzhiyun MODULE_LICENSE("GPL");
362*4882a593Smuzhiyun
363