1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Device Tree Source for AM6 SoC family in Quad core configuration 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun#include "k3-am65.dtsi" 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun/ { 11*4882a593Smuzhiyun cpus { 12*4882a593Smuzhiyun #address-cells = <1>; 13*4882a593Smuzhiyun #size-cells = <0>; 14*4882a593Smuzhiyun cpu-map { 15*4882a593Smuzhiyun cluster0: cluster0 { 16*4882a593Smuzhiyun core0 { 17*4882a593Smuzhiyun cpu = <&cpu0>; 18*4882a593Smuzhiyun }; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun core1 { 21*4882a593Smuzhiyun cpu = <&cpu1>; 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun cluster1: cluster1 { 26*4882a593Smuzhiyun core0 { 27*4882a593Smuzhiyun cpu = <&cpu2>; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun core1 { 31*4882a593Smuzhiyun cpu = <&cpu3>; 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun cpu0: cpu@0 { 37*4882a593Smuzhiyun compatible = "arm,cortex-a53"; 38*4882a593Smuzhiyun reg = <0x000>; 39*4882a593Smuzhiyun device_type = "cpu"; 40*4882a593Smuzhiyun enable-method = "psci"; 41*4882a593Smuzhiyun i-cache-size = <0x8000>; 42*4882a593Smuzhiyun i-cache-line-size = <64>; 43*4882a593Smuzhiyun i-cache-sets = <256>; 44*4882a593Smuzhiyun d-cache-size = <0x8000>; 45*4882a593Smuzhiyun d-cache-line-size = <64>; 46*4882a593Smuzhiyun d-cache-sets = <128>; 47*4882a593Smuzhiyun next-level-cache = <&L2_0>; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun cpu1: cpu@1 { 51*4882a593Smuzhiyun compatible = "arm,cortex-a53"; 52*4882a593Smuzhiyun reg = <0x001>; 53*4882a593Smuzhiyun device_type = "cpu"; 54*4882a593Smuzhiyun enable-method = "psci"; 55*4882a593Smuzhiyun i-cache-size = <0x8000>; 56*4882a593Smuzhiyun i-cache-line-size = <64>; 57*4882a593Smuzhiyun i-cache-sets = <256>; 58*4882a593Smuzhiyun d-cache-size = <0x8000>; 59*4882a593Smuzhiyun d-cache-line-size = <64>; 60*4882a593Smuzhiyun d-cache-sets = <128>; 61*4882a593Smuzhiyun next-level-cache = <&L2_0>; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun cpu2: cpu@100 { 65*4882a593Smuzhiyun compatible = "arm,cortex-a53"; 66*4882a593Smuzhiyun reg = <0x100>; 67*4882a593Smuzhiyun device_type = "cpu"; 68*4882a593Smuzhiyun enable-method = "psci"; 69*4882a593Smuzhiyun i-cache-size = <0x8000>; 70*4882a593Smuzhiyun i-cache-line-size = <64>; 71*4882a593Smuzhiyun i-cache-sets = <256>; 72*4882a593Smuzhiyun d-cache-size = <0x8000>; 73*4882a593Smuzhiyun d-cache-line-size = <64>; 74*4882a593Smuzhiyun d-cache-sets = <128>; 75*4882a593Smuzhiyun next-level-cache = <&L2_1>; 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun cpu3: cpu@101 { 79*4882a593Smuzhiyun compatible = "arm,cortex-a53"; 80*4882a593Smuzhiyun reg = <0x101>; 81*4882a593Smuzhiyun device_type = "cpu"; 82*4882a593Smuzhiyun enable-method = "psci"; 83*4882a593Smuzhiyun i-cache-size = <0x8000>; 84*4882a593Smuzhiyun i-cache-line-size = <64>; 85*4882a593Smuzhiyun i-cache-sets = <256>; 86*4882a593Smuzhiyun d-cache-size = <0x8000>; 87*4882a593Smuzhiyun d-cache-line-size = <64>; 88*4882a593Smuzhiyun d-cache-sets = <128>; 89*4882a593Smuzhiyun next-level-cache = <&L2_1>; 90*4882a593Smuzhiyun }; 91*4882a593Smuzhiyun }; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun L2_0: l2-cache0 { 94*4882a593Smuzhiyun compatible = "cache"; 95*4882a593Smuzhiyun cache-level = <2>; 96*4882a593Smuzhiyun cache-size = <0x80000>; 97*4882a593Smuzhiyun cache-line-size = <64>; 98*4882a593Smuzhiyun cache-sets = <512>; 99*4882a593Smuzhiyun next-level-cache = <&msmc_l3>; 100*4882a593Smuzhiyun }; 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun L2_1: l2-cache1 { 103*4882a593Smuzhiyun compatible = "cache"; 104*4882a593Smuzhiyun cache-level = <2>; 105*4882a593Smuzhiyun cache-size = <0x80000>; 106*4882a593Smuzhiyun cache-line-size = <64>; 107*4882a593Smuzhiyun cache-sets = <512>; 108*4882a593Smuzhiyun next-level-cache = <&msmc_l3>; 109*4882a593Smuzhiyun }; 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun msmc_l3: l3-cache0 { 112*4882a593Smuzhiyun compatible = "cache"; 113*4882a593Smuzhiyun cache-level = <3>; 114*4882a593Smuzhiyun }; 115*4882a593Smuzhiyun}; 116