1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * linux/drivers/net/ethernet/amd/am79c961a.h 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _LINUX_am79c961a_H 7*4882a593Smuzhiyun #define _LINUX_am79c961a_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* use 0 for production, 1 for verification, >2 for debug. debug flags: */ 10*4882a593Smuzhiyun #define DEBUG_TX 2 11*4882a593Smuzhiyun #define DEBUG_RX 4 12*4882a593Smuzhiyun #define DEBUG_INT 8 13*4882a593Smuzhiyun #define DEBUG_IC 16 14*4882a593Smuzhiyun #ifndef NET_DEBUG 15*4882a593Smuzhiyun #define NET_DEBUG 0 16*4882a593Smuzhiyun #endif 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define NET_UID 0 19*4882a593Smuzhiyun #define NET_RDP 0x10 20*4882a593Smuzhiyun #define NET_RAP 0x12 21*4882a593Smuzhiyun #define NET_RESET 0x14 22*4882a593Smuzhiyun #define NET_IDP 0x16 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* 25*4882a593Smuzhiyun * RAP registers 26*4882a593Smuzhiyun */ 27*4882a593Smuzhiyun #define CSR0 0 28*4882a593Smuzhiyun #define CSR0_INIT 0x0001 29*4882a593Smuzhiyun #define CSR0_STRT 0x0002 30*4882a593Smuzhiyun #define CSR0_STOP 0x0004 31*4882a593Smuzhiyun #define CSR0_TDMD 0x0008 32*4882a593Smuzhiyun #define CSR0_TXON 0x0010 33*4882a593Smuzhiyun #define CSR0_RXON 0x0020 34*4882a593Smuzhiyun #define CSR0_IENA 0x0040 35*4882a593Smuzhiyun #define CSR0_INTR 0x0080 36*4882a593Smuzhiyun #define CSR0_IDON 0x0100 37*4882a593Smuzhiyun #define CSR0_TINT 0x0200 38*4882a593Smuzhiyun #define CSR0_RINT 0x0400 39*4882a593Smuzhiyun #define CSR0_MERR 0x0800 40*4882a593Smuzhiyun #define CSR0_MISS 0x1000 41*4882a593Smuzhiyun #define CSR0_CERR 0x2000 42*4882a593Smuzhiyun #define CSR0_BABL 0x4000 43*4882a593Smuzhiyun #define CSR0_ERR 0x8000 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define CSR3 3 46*4882a593Smuzhiyun #define CSR3_EMBA 0x0008 47*4882a593Smuzhiyun #define CSR3_DXMT2PD 0x0010 48*4882a593Smuzhiyun #define CSR3_LAPPEN 0x0020 49*4882a593Smuzhiyun #define CSR3_DXSUFLO 0x0040 50*4882a593Smuzhiyun #define CSR3_IDONM 0x0100 51*4882a593Smuzhiyun #define CSR3_TINTM 0x0200 52*4882a593Smuzhiyun #define CSR3_RINTM 0x0400 53*4882a593Smuzhiyun #define CSR3_MERRM 0x0800 54*4882a593Smuzhiyun #define CSR3_MISSM 0x1000 55*4882a593Smuzhiyun #define CSR3_BABLM 0x4000 56*4882a593Smuzhiyun #define CSR3_MASKALL 0x5F00 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #define CSR4 4 59*4882a593Smuzhiyun #define CSR4_JABM 0x0001 60*4882a593Smuzhiyun #define CSR4_JAB 0x0002 61*4882a593Smuzhiyun #define CSR4_TXSTRTM 0x0004 62*4882a593Smuzhiyun #define CSR4_TXSTRT 0x0008 63*4882a593Smuzhiyun #define CSR4_RCVCCOM 0x0010 64*4882a593Smuzhiyun #define CSR4_RCVCCO 0x0020 65*4882a593Smuzhiyun #define CSR4_MFCOM 0x0100 66*4882a593Smuzhiyun #define CSR4_MFCO 0x0200 67*4882a593Smuzhiyun #define CSR4_ASTRP_RCV 0x0400 68*4882a593Smuzhiyun #define CSR4_APAD_XMIT 0x0800 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun #define CTRL1 5 71*4882a593Smuzhiyun #define CTRL1_SPND 0x0001 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #define LADRL 8 74*4882a593Smuzhiyun #define LADRM1 9 75*4882a593Smuzhiyun #define LADRM2 10 76*4882a593Smuzhiyun #define LADRH 11 77*4882a593Smuzhiyun #define PADRL 12 78*4882a593Smuzhiyun #define PADRM 13 79*4882a593Smuzhiyun #define PADRH 14 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun #define MODE 15 82*4882a593Smuzhiyun #define MODE_DISRX 0x0001 83*4882a593Smuzhiyun #define MODE_DISTX 0x0002 84*4882a593Smuzhiyun #define MODE_LOOP 0x0004 85*4882a593Smuzhiyun #define MODE_DTCRC 0x0008 86*4882a593Smuzhiyun #define MODE_COLL 0x0010 87*4882a593Smuzhiyun #define MODE_DRETRY 0x0020 88*4882a593Smuzhiyun #define MODE_INTLOOP 0x0040 89*4882a593Smuzhiyun #define MODE_PORT_AUI 0x0000 90*4882a593Smuzhiyun #define MODE_PORT_10BT 0x0080 91*4882a593Smuzhiyun #define MODE_DRXPA 0x2000 92*4882a593Smuzhiyun #define MODE_DRXBA 0x4000 93*4882a593Smuzhiyun #define MODE_PROMISC 0x8000 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun #define BASERXL 24 96*4882a593Smuzhiyun #define BASERXH 25 97*4882a593Smuzhiyun #define BASETXL 30 98*4882a593Smuzhiyun #define BASETXH 31 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun #define POLLINT 47 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun #define SIZERXR 76 103*4882a593Smuzhiyun #define SIZETXR 78 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun #define CSR_MFC 112 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun #define RMD_ENP 0x0100 108*4882a593Smuzhiyun #define RMD_STP 0x0200 109*4882a593Smuzhiyun #define RMD_CRC 0x0800 110*4882a593Smuzhiyun #define RMD_FRAM 0x2000 111*4882a593Smuzhiyun #define RMD_ERR 0x4000 112*4882a593Smuzhiyun #define RMD_OWN 0x8000 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun #define TMD_ENP 0x0100 115*4882a593Smuzhiyun #define TMD_STP 0x0200 116*4882a593Smuzhiyun #define TMD_MORE 0x1000 117*4882a593Smuzhiyun #define TMD_ERR 0x4000 118*4882a593Smuzhiyun #define TMD_OWN 0x8000 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun #define TST_RTRY 0x0400 121*4882a593Smuzhiyun #define TST_LCAR 0x0800 122*4882a593Smuzhiyun #define TST_LCOL 0x1000 123*4882a593Smuzhiyun #define TST_UFLO 0x4000 124*4882a593Smuzhiyun #define TST_BUFF 0x8000 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun #define ISALED0 0x0004 127*4882a593Smuzhiyun #define ISALED0_LNKST 0x8000 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun struct dev_priv { 130*4882a593Smuzhiyun unsigned long rxbuffer[RX_BUFFERS]; 131*4882a593Smuzhiyun unsigned long txbuffer[TX_BUFFERS]; 132*4882a593Smuzhiyun unsigned char txhead; 133*4882a593Smuzhiyun unsigned char txtail; 134*4882a593Smuzhiyun unsigned char rxhead; 135*4882a593Smuzhiyun unsigned char rxtail; 136*4882a593Smuzhiyun unsigned long rxhdr; 137*4882a593Smuzhiyun unsigned long txhdr; 138*4882a593Smuzhiyun spinlock_t chip_lock; 139*4882a593Smuzhiyun struct timer_list timer; 140*4882a593Smuzhiyun struct net_device *dev; 141*4882a593Smuzhiyun }; 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun #endif 144