xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/pci/pci-iommu.txt (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593SmuzhiyunThis document describes the generic device tree binding for describing the
2*4882a593Smuzhiyunrelationship between PCI(e) devices and IOMMU(s).
3*4882a593Smuzhiyun
4*4882a593SmuzhiyunEach PCI(e) device under a root complex is uniquely identified by its Requester
5*4882a593SmuzhiyunID (AKA RID). A Requester ID is a triplet of a Bus number, Device number, and
6*4882a593SmuzhiyunFunction number.
7*4882a593Smuzhiyun
8*4882a593SmuzhiyunFor the purpose of this document, when treated as a numeric value, a RID is
9*4882a593Smuzhiyunformatted such that:
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun* Bits [15:8] are the Bus number.
12*4882a593Smuzhiyun* Bits [7:3] are the Device number.
13*4882a593Smuzhiyun* Bits [2:0] are the Function number.
14*4882a593Smuzhiyun* Any other bits required for padding must be zero.
15*4882a593Smuzhiyun
16*4882a593SmuzhiyunIOMMUs may distinguish PCI devices through sideband data derived from the
17*4882a593SmuzhiyunRequester ID. While a given PCI device can only master through one IOMMU, a
18*4882a593Smuzhiyunroot complex may split masters across a set of IOMMUs (e.g. with one IOMMU per
19*4882a593Smuzhiyunbus).
20*4882a593Smuzhiyun
21*4882a593SmuzhiyunThe generic 'iommus' property is insufficient to describe this relationship,
22*4882a593Smuzhiyunand a mechanism is required to map from a PCI device to its IOMMU and sideband
23*4882a593Smuzhiyundata.
24*4882a593Smuzhiyun
25*4882a593SmuzhiyunFor generic IOMMU bindings, see
26*4882a593SmuzhiyunDocumentation/devicetree/bindings/iommu/iommu.txt.
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun
29*4882a593SmuzhiyunPCI root complex
30*4882a593Smuzhiyun================
31*4882a593Smuzhiyun
32*4882a593SmuzhiyunOptional properties
33*4882a593Smuzhiyun-------------------
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun- iommu-map: Maps a Requester ID to an IOMMU and associated IOMMU specifier
36*4882a593Smuzhiyun  data.
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun  The property is an arbitrary number of tuples of
39*4882a593Smuzhiyun  (rid-base,iommu,iommu-base,length).
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun  Any RID r in the interval [rid-base, rid-base + length) is associated with
42*4882a593Smuzhiyun  the listed IOMMU, with the IOMMU specifier (r - rid-base + iommu-base).
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun- iommu-map-mask: A mask to be applied to each Requester ID prior to being
45*4882a593Smuzhiyun  mapped to an IOMMU specifier per the iommu-map property.
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun
48*4882a593SmuzhiyunExample (1)
49*4882a593Smuzhiyun===========
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun/ {
52*4882a593Smuzhiyun	#address-cells = <1>;
53*4882a593Smuzhiyun	#size-cells = <1>;
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun	iommu: iommu@a {
56*4882a593Smuzhiyun		reg = <0xa 0x1>;
57*4882a593Smuzhiyun		compatible = "vendor,some-iommu";
58*4882a593Smuzhiyun		#iommu-cells = <1>;
59*4882a593Smuzhiyun	};
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun	pci: pci@f {
62*4882a593Smuzhiyun		reg = <0xf 0x1>;
63*4882a593Smuzhiyun		compatible = "vendor,pcie-root-complex";
64*4882a593Smuzhiyun		device_type = "pci";
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun		/*
67*4882a593Smuzhiyun		 * The sideband data provided to the IOMMU is the RID,
68*4882a593Smuzhiyun		 * identity-mapped.
69*4882a593Smuzhiyun		 */
70*4882a593Smuzhiyun		iommu-map = <0x0 &iommu 0x0 0x10000>;
71*4882a593Smuzhiyun	};
72*4882a593Smuzhiyun};
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun
75*4882a593SmuzhiyunExample (2)
76*4882a593Smuzhiyun===========
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun/ {
79*4882a593Smuzhiyun	#address-cells = <1>;
80*4882a593Smuzhiyun	#size-cells = <1>;
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun	iommu: iommu@a {
83*4882a593Smuzhiyun		reg = <0xa 0x1>;
84*4882a593Smuzhiyun		compatible = "vendor,some-iommu";
85*4882a593Smuzhiyun		#iommu-cells = <1>;
86*4882a593Smuzhiyun	};
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun	pci: pci@f {
89*4882a593Smuzhiyun		reg = <0xf 0x1>;
90*4882a593Smuzhiyun		compatible = "vendor,pcie-root-complex";
91*4882a593Smuzhiyun		device_type = "pci";
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun		/*
94*4882a593Smuzhiyun		 * The sideband data provided to the IOMMU is the RID with the
95*4882a593Smuzhiyun		 * function bits masked out.
96*4882a593Smuzhiyun		 */
97*4882a593Smuzhiyun		iommu-map = <0x0 &iommu 0x0 0x10000>;
98*4882a593Smuzhiyun		iommu-map-mask = <0xfff8>;
99*4882a593Smuzhiyun	};
100*4882a593Smuzhiyun};
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun
103*4882a593SmuzhiyunExample (3)
104*4882a593Smuzhiyun===========
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun/ {
107*4882a593Smuzhiyun	#address-cells = <1>;
108*4882a593Smuzhiyun	#size-cells = <1>;
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun	iommu: iommu@a {
111*4882a593Smuzhiyun		reg = <0xa 0x1>;
112*4882a593Smuzhiyun		compatible = "vendor,some-iommu";
113*4882a593Smuzhiyun		#iommu-cells = <1>;
114*4882a593Smuzhiyun	};
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun	pci: pci@f {
117*4882a593Smuzhiyun		reg = <0xf 0x1>;
118*4882a593Smuzhiyun		compatible = "vendor,pcie-root-complex";
119*4882a593Smuzhiyun		device_type = "pci";
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun		/*
122*4882a593Smuzhiyun		 * The sideband data provided to the IOMMU is the RID,
123*4882a593Smuzhiyun		 * but the high bits of the bus number are flipped.
124*4882a593Smuzhiyun		 */
125*4882a593Smuzhiyun		iommu-map = <0x0000 &iommu 0x8000 0x8000>,
126*4882a593Smuzhiyun			    <0x8000 &iommu 0x0000 0x8000>;
127*4882a593Smuzhiyun	};
128*4882a593Smuzhiyun};
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun
131*4882a593SmuzhiyunExample (4)
132*4882a593Smuzhiyun===========
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun/ {
135*4882a593Smuzhiyun	#address-cells = <1>;
136*4882a593Smuzhiyun	#size-cells = <1>;
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun	iommu_a: iommu@a {
139*4882a593Smuzhiyun		reg = <0xa 0x1>;
140*4882a593Smuzhiyun		compatible = "vendor,some-iommu";
141*4882a593Smuzhiyun		#iommu-cells = <1>;
142*4882a593Smuzhiyun	};
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun	iommu_b: iommu@b {
145*4882a593Smuzhiyun		reg = <0xb 0x1>;
146*4882a593Smuzhiyun		compatible = "vendor,some-iommu";
147*4882a593Smuzhiyun		#iommu-cells = <1>;
148*4882a593Smuzhiyun	};
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun	iommu_c: iommu@c {
151*4882a593Smuzhiyun		reg = <0xc 0x1>;
152*4882a593Smuzhiyun		compatible = "vendor,some-iommu";
153*4882a593Smuzhiyun		#iommu-cells = <1>;
154*4882a593Smuzhiyun	};
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun	pci: pci@f {
157*4882a593Smuzhiyun		reg = <0xf 0x1>;
158*4882a593Smuzhiyun		compatible = "vendor,pcie-root-complex";
159*4882a593Smuzhiyun		device_type = "pci";
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun		/*
162*4882a593Smuzhiyun		 * Devices with bus number 0-127 are mastered via IOMMU
163*4882a593Smuzhiyun		 * a, with sideband data being RID[14:0].
164*4882a593Smuzhiyun		 * Devices with bus number 128-255 are mastered via
165*4882a593Smuzhiyun		 * IOMMU b, with sideband data being RID[14:0].
166*4882a593Smuzhiyun		 * No devices master via IOMMU c.
167*4882a593Smuzhiyun		 */
168*4882a593Smuzhiyun		iommu-map = <0x0000 &iommu_a 0x0000 0x8000>,
169*4882a593Smuzhiyun			    <0x8000 &iommu_b 0x0000 0x8000>;
170*4882a593Smuzhiyun	};
171*4882a593Smuzhiyun};
172