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/OK3568_Linux_fs/u-boot/arch/mips/dts/
H A Dar934x.dtsi17 #size-cells = <0>;
19 cpu@0 {
22 reg = <0>;
32 #clock-cells = <0>;
54 reg = <0x1b000100 0x100>;
61 reg = <0x18020000 0x20>;
67 gmac0: eth@0x19000000 {
69 reg = <0x19000000 0x200>;
77 #size-cells = <0>;
78 phy0: ethernet-phy@0 {
[all …]
H A Dar933x.dtsi18 #size-cells = <0>;
20 cpu@0 {
23 reg = <0>;
33 #clock-cells = <0>;
45 reg = <0x18040000 0x100>;
64 reg = <0x1b000100 0x100>;
71 reg = <0x18020000 0x20>;
77 gmac0: eth@0x19000000 {
79 reg = <0x19000000 0x200>;
87 #size-cells = <0>;
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/arm/mediatek/
H A Dmediatek,jpgdecsys.txt20 reg = <0 0x19000000 0 0x1000>;
H A Dmediatek,vencltsys.txt20 reg = <0 0x19000000 0 0x1000>;
H A Dmediatek,ipu.txt23 reg = <0 0x19000000 0 0x1000>;
29 reg = <0 0x19010000 0 0x1000>;
35 reg = <0 0x19180000 0 0x1000>;
41 reg = <0 0x19280000 0 0x1000>;
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/iproc-common/
H A Dsysmap.h10 #define IHOST_PROC_CLK_PLLARMA 0X19000C00
11 #define IHOST_PROC_CLK_PLLARMB 0X19000C04
14 #define IHOST_PROC_CLK_WR_ACCESS 0X19000000
15 #define IHOST_PROC_CLK_POLICY_FREQ 0X19000008
20 #define IHOST_PROC_CLK_POLICY_CTL 0X1900000C
21 #define IHOST_PROC_CLK_POLICY_CTL__GO 0
23 #define IHOST_PROC_CLK_PLLARMB__PLLARM_NDIV_FRAC_R 0
26 #define IHOST_PROC_CLK_POLICY_FREQ__POLICY0_FREQ_R 0
29 #define IHOST_PROC_CLK_PLLARMA__PLLARM_SOFT_RESETB 0
30 #define IHOST_PROC_CLK_CORE0_CLKGATE 0X19000200
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/memory-controllers/
H A Dingenic,nemc.yaml14 pattern: "^memory-controller@[0-9a-f]+$"
40 ".*@[0-9]+$":
91 reg = <0x13410000 0x10000>;
94 ranges = <1 0 0x1b000000 0x1000000>,
95 <2 0 0x1a000000 0x1000000>,
96 <3 0 0x19000000 0x1000000>,
97 <4 0 0x18000000 0x1000000>,
98 <5 0 0x17000000 0x1000000>,
99 <6 0 0x16000000 0x1000000>;
108 pinctrl-0 = <&pins_nemc_cs6>;
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mtd/
H A Dingenic,nand.yaml61 reg = <0x13410000 0x10000>;
64 ranges = <1 0 0x1b000000 0x1000000>,
65 <2 0 0x1a000000 0x1000000>,
66 <3 0 0x19000000 0x1000000>,
67 <4 0 0x18000000 0x1000000>,
68 <5 0 0x17000000 0x1000000>,
69 <6 0 0x16000000 0x1000000>;
75 reg = <1 0 0x1000000>;
78 #size-cells = <0>;
89 pinctrl-0 = <&pins_nemc>;
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dintegrator.dtsi12 reg = <0x0 0x0>;
17 reg = <0x10000000 0x200>;
20 led@c.0 {
22 offset = <0x0c>;
23 mask = <0x01>;
32 reg = <0x12000000 0x100>;
36 reg = <0x13000000 0x100>;
42 reg = <0x13000100 0x100>;
48 reg = <0x13000200 0x100>;
57 reg = <0x14000000 0x100>;
[all …]
H A Dbcm-cygnus-clock.dtsi39 #clock-cells = <0>;
46 #clock-cells = <0>;
49 reg = <0x19000000 0x1000>;
54 #clock-cells = <0>;
63 #clock-cells = <0>;
73 reg = <0x0301d000 0x2c>, <0x0301c020 0x4>;
81 #clock-cells = <0>;
90 #clock-cells = <0>;
100 reg = <0x0301d02c 0x1c>, <0x0301c020 0x4>;
109 reg = <0x180a9800 0x2c>, <0x0301c020 0x4>, <0x180aa024 0x4>;
[all …]
H A Dbcm-hr2.dtsi45 #size-cells = <0>;
47 cpu0: cpu@0 {
51 reg = <0x0>;
64 ranges = <0x00000000 0x19000000 0x00023000>;
68 a9pll: arm_clk@0 {
69 #clock-cells = <0>;
72 reg = <0x0 0x1000>;
77 reg = <0x20200 0x100>;
84 reg = <0x20600 0x20>;
92 reg = <0x20620 0x20>;
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/net/dsa/
H A Dar9331.txt26 reg = <0x19000000 0x200>;
40 reg = <0x1a000000 0x200>;
56 #size-cells = <0>;
60 #size-cells = <0>;
63 reg = <0x10>;
75 #size-cells = <0>;
77 switch_port0: port@0 {
78 reg = <0x0>;
91 reg = <0x1>;
97 reg = <0x2>;
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/net/
H A Dqca,ar71xx.yaml43 const: 0
82 reg = <0x19000000 0x200>;
95 reg = <0x1a000000 0x200>;
113 #size-cells = <0>;
117 #size-cells = <0>;
120 reg = <0x10>;
132 #size-cells = <0>;
134 switch_port0: port@0 {
135 reg = <0x0>;
148 reg = <0x1>;
[all …]
/OK3568_Linux_fs/kernel/arch/mips/sni/
H A Da20r.c30 PORT(0x3f8, 4),
31 PORT(0x2f8, 3),
45 .start = 0x1c081ffc,
46 .end = 0x1c081fff,
59 .start = 0x18000000,
60 .end = 0x18000004,
64 .start = 0x18010000,
65 .end = 0x18010004,
69 .start = 0x1ff00000,
70 .end = 0x1ff00020,
[all …]
/OK3568_Linux_fs/kernel/arch/powerpc/boot/dts/fsl/
H A Dp1022ds.dtsi36 nor@0,0 {
40 reg = <0x0 0x0 0x8000000>;
44 partition@0 {
45 reg = <0x0 0x03000000>;
51 reg = <0x03000000 0x00e00000>;
57 reg = <0x03e00000 0x00200000>;
63 reg = <0x04000000 0x00400000>;
69 reg = <0x04400000 0x03b00000>;
74 reg = <0x07f00000 0x00080000>;
80 reg = <0x07f80000 0x00080000>;
[all …]
/OK3568_Linux_fs/kernel/arch/mips/boot/dts/qca/
H A Dar9331.dtsi12 #size-cells = <0>;
14 cpu@0 {
18 reg = <0>;
34 #clock-cells = <0>;
57 reg = <0x18000000 0x100>;
64 reg = <0x18020000 0x14>;
76 reg = <0x18040000 0x34>;
92 reg = <0x18050000 0x100>;
102 reg = <0x18060010 0x8>;
113 reg = <0x1806001c 0x4>;
[all …]
/OK3568_Linux_fs/kernel/arch/mips/pci/
H A Dpci-lantiq.c27 #define PCI_CR_FCI_ADDR_MAP0 0x00C0
28 #define PCI_CR_FCI_ADDR_MAP1 0x00C4
29 #define PCI_CR_FCI_ADDR_MAP2 0x00C8
30 #define PCI_CR_FCI_ADDR_MAP3 0x00CC
31 #define PCI_CR_FCI_ADDR_MAP4 0x00D0
32 #define PCI_CR_FCI_ADDR_MAP5 0x00D4
33 #define PCI_CR_FCI_ADDR_MAP6 0x00D8
34 #define PCI_CR_FCI_ADDR_MAP7 0x00DC
35 #define PCI_CR_CLK_CTRL 0x0000
36 #define PCI_CR_PCI_MOD 0x0030
[all …]
/OK3568_Linux_fs/kernel/arch/arm/mach-integrator/
H A Dhardware.h14 #define IO_BASE 0xF0000000 // VA of IO
15 #define IO_SIZE 0x0B000000 // How much?
20 #define IO_ADDRESS(x) (((x) & 0x000fffff) | (((x) >> 4) & 0x0ff00000) | IO_BASE)
30 #define INTEGRATOR_BOOT_ROM_LO 0x00000000
31 #define INTEGRATOR_BOOT_ROM_HI 0x20000000
45 #define INTEGRATOR_SSRAM_BASE 0x00000000
46 #define INTEGRATOR_SSRAM_ALIAS_BASE 0x10800000
49 #define INTEGRATOR_FLASH_BASE 0x24000000
52 #define INTEGRATOR_MBRD_SSRAM_BASE 0x28000000
58 #define INTEGRATOR_SDRAM_BASE 0x00040000
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/bcmdhd/
H A Dsiutils_priv.h88 #define AI_SLAVE_WRAPPER 0
108 /* for some combo chips, BT side accesses chipcommon->0x190, as a 16 byte addr */
109 /* register at 0x19C doesn't exist, so error is logged at the slave wrapper */
111 #define BT_CC_SPROM_BADREG_LO 0x18000190
113 #define BT_CC_SPROM_BADREG_HI 0
122 #define BCM4378_BT_ADDR_HI 0
123 #define BCM4378_BT_ADDR_LO 0x19000000 /* BT address space */
124 #define BCM4378_BT_SIZE 0x01000000 /* BT address space size */
125 #define BCM4378_UNUSED_AXI_ID 0xffffffff
126 #define BCM4378_CC_AXI_ID 0
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd/
H A Dsiutils_priv.h88 #define AI_SLAVE_WRAPPER 0
108 /* for some combo chips, BT side accesses chipcommon->0x190, as a 16 byte addr */
109 /* register at 0x19C doesn't exist, so error is logged at the slave wrapper */
111 #define BT_CC_SPROM_BADREG_LO 0x18000190
113 #define BT_CC_SPROM_BADREG_HI 0
122 #define BCM4378_BT_ADDR_HI 0
123 #define BCM4378_BT_ADDR_LO 0x19000000 /* BT address space */
124 #define BCM4378_BT_SIZE 0x01000000 /* BT address space size */
125 #define BCM4378_UNUSED_AXI_ID 0xffffffff
126 #define BCM4378_CC_AXI_ID 0
[all …]
/OK3568_Linux_fs/kernel/arch/arm/mach-s3c/
H A Dmach-qt2410.c50 { 0xe0000000, __phys_to_pfn(S3C2410_CS3+0x01000000), SZ_1M, MT_DEVICE }
58 [0] = {
59 .hwport = 0,
60 .flags = 0,
67 .flags = 0,
74 .flags = 0,
157 .default_display = 0,
159 .lpcsel = ((0xCE6) & ~7) | 1<<4,
165 [0] = DEFINE_RES_MEM(0x19000000, 17),
178 .dev_id = "s3c24xx_led.0",
[all …]
/OK3568_Linux_fs/u-boot/board/renesas/sh7753evb/
H A Dlowlevel_init.S29 mov #0, r14
40 /* If CPU runs on SDRAM (PC=0x5???????) or not. */
41 PC_MASK: .long 0x20000000
67 cmp/eq #0, r0
201 EXPEVT_A: .long 0xff000024
202 EXPEVT_POWER_ON_RESET: .long 0x00000000
205 MRSTCR0_A: .long 0xffd50030
206 MRSTCR0_D: .long 0xfe1ffe7f
207 MRSTCR1_A: .long 0xffd50034
208 MRSTCR1_D: .long 0xfff3ffff
[all …]
/OK3568_Linux_fs/u-boot/board/renesas/sh7752evb/
H A Dlowlevel_init.S44 PDCR_A: .long 0xffec0006
45 PGCR_A: .long 0xffec000c
46 PJCR_A: .long 0xffec0012
47 PTCR_A: .long 0xffec0026
48 PSEL1_A: .long 0xffec0072
49 PSEL2_A: .long 0xffec0074
50 PSEL5_A: .long 0xffec007a
52 PDCR_D: .long 0x0000
53 PGCR_D: .long 0x0004
54 PJCR_D: .long 0x0000
[all …]
/OK3568_Linux_fs/u-boot/board/renesas/sh7757lcr/
H A Dlowlevel_init.S74 PGDR_A: .long 0xffec0040
75 PACR_A: .long 0xffec0000
76 PBCR_A: .long 0xffec0002
77 PCCR_A: .long 0xffec0004
78 PDCR_A: .long 0xffec0006
79 PECR_A: .long 0xffec0008
80 PFCR_A: .long 0xffec000a
81 PGCR_A: .long 0xffec000c
82 PHCR_A: .long 0xffec000e
83 PICR_A: .long 0xffec0010
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/mediatek/
H A Dmt6797.dtsi25 #size-cells = <0>;
27 cpu0: cpu@0 {
31 reg = <0x000>;
38 reg = <0x001>;
45 reg = <0x002>;
52 reg = <0x003>;
59 reg = <0x100>;
66 reg = <0x101>;
73 reg = <0x102>;
80 reg = <0x103>;
[all …]

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