drivers/bcmdhd/siutils_priv.h

88 #define AI_SLAVE_WRAPPER        0
108 /* for some combo chips, BT side accesses chipcommon->0x190, as a 16 byte addr */
109 /* register at 0x19C doesn't exist, so error is logged at the slave wrapper */
111 #define BT_CC_SPROM_BADREG_LO   0x18000190
113 #define BT_CC_SPROM_BADREG_HI   0
122 #define BCM4378_BT_ADDR_HI	0
123 #define BCM4378_BT_ADDR_LO	0x19000000	/* BT address space */
124 #define BCM4378_BT_SIZE		0x01000000	/* BT address space size */
125 #define BCM4378_UNUSED_AXI_ID	0xffffffff
126 #define BCM4378_CC_AXI_ID	0
129 #define BCM4387_BT_ADDR_HI	0
130 #define BCM4387_BT_ADDR_LO	0x19000000	/* BT address space */
131 #define BCM4387_BT_SIZE		0x01000000	/* BT address space size */
132 #define BCM4387_UNUSED_AXI_ID	0xffffffff
133 #define BCM4387_CC_AXI_ID	0
136 #define BCM_AXI_ID_MASK	0xFu
137 #define BCM_AXI_ACCESS_TYPE_MASK 0xF0u
164 	uint32  csp2ba[SI_MAXCORES];		/**< Second slave port base addr 0 */
236 					 * the first(0)/second(1)/...
250 #define BADCOREADDR	0
302 #define	ILP_DIV_5MHZ		0		/**< ILP = 5 MHz */
425 #define ub_scan(a, b, c) do {} while (0)
426 #define ub_flag(a) (0)
427 #define ub_setint(a, b) do {} while (0)
428 #define ub_coreidx(a) (0)
429 #define ub_corevendor(a) (0)
430 #define ub_corerev(a) (0)
431 #define ub_iscoreup(a) (0)
432 #define ub_setcoreidx(a, b) (0)
433 #define ub_core_cflags(a, b, c) (0)
434 #define ub_core_cflags_wo(a, b, c) do {} while (0)
435 #define ub_core_sflags(a, b, c) (0)
436 #define ub_corereg(a, b, c, d, e) (0)
437 #define ub_core_reset(a, b, c) do {} while (0)
438 #define ub_core_disable(a, b) do {} while (0)
439 #define ub_numaddrspaces(a) (0)
440 #define ub_addrspace(a, b)  (0)
441 #define ub_addrspacesize(a, b) (0)
442 #define ub_view(a, b) do {} while (0)
443 #define ub_dumpregs(a, b) do {} while (0)
446 #define nci_uninit(a) do {} while (0)
447 #define nci_scan(a) (0)
448 #define nci_dump_erom(a) do {} while (0)
452 #define nci_findcoreidx(a, b, c) (0)
454 #define nci_corereg_writeonly(a, b, c, d, e) (0)
455 #define nci_corereg(a, b, c, d, e) (0)
456 #define nci_corerev_minor(a) (0)
457 #define nci_corerev(a) (0)
458 #define nci_corevendor(a) (0)
459 #define nci_get_wrap_reg(a, b, c, d) (0)
460 #define nci_core_reset(a, b, c) do {} while (0)
461 #define nci_core_disable(a, b) do {} while (0)
463 #define nci_coreid(a, b) (0)
464 #define nci_numcoreunits(a, b) (0)
465 #define nci_addr_space(a, b, c) (0)
466 #define nci_addr_space_size(a, b, c) (0)
468 #define nci_intflag(a) (0)
469 #define nci_flag(a) (0)
470 #define nci_flag_alt(a) (0)
471 #define nci_setint(a, b) do {} while (0)
472 #define nci_oobr_baseaddr(a, b) (0)
473 #define nci_coreunit(a) (0)
474 #define nci_corelist(a, b) (0)
475 #define nci_numaddrspaces(a) (0)
476 #define nci_addrspace(a, b, c) (0)
477 #define nci_addrspacesize(a, b, c) (0)
478 #define nci_coreaddrspaceX(a, b, c, d) do {} while (0)
479 #define nci_core_cflags(a, b, c) (0)
480 #define nci_core_cflags_wo(a, b, c) do {} while (0)
481 #define nci_core_sflags(a, b, c) (0)
482 #define nci_wrapperreg(a, b, c, d) (0)
483 #define nci_invalidate_second_bar0win(a) do {} while (0)
484 #define nci_backplane_access(a, b, c, d, e) (0)
485 #define nci_backplane_access_64(a, b, c, d, e) (0)
486 #define nci_num_slaveports(a, b) (0)
488 #define nci_dumpregs(a, b) do {} while (0)
491 #define nci_view(a, b) do {} while (0)
492 #define nci_viewall(a, b) do {} while (0)
494 #define nci_get_nth_wrapper(a, b) (0)
495 #define nci_get_axi_addr(a, b) (0)
497 #define nci_wrapper_dump_binary(a, b) (0)
498 #define nci_wrapper_dump_last_timeout(a, b, c, d, e) (0)
500 #define nci_get_core_baaddr(a, b, c) (0)
501 #define nci_clear_backplane_to(a) (0)
502 #define nci_clear_backplane_to_per_core(a, b, c, d) (0)
504 #define nci_wrapper_get_last_error(a, b, c, d, e, f) do {} while (0)
505 #define nci_get_axi_timeout_reg() (0)
506 #define nci_findcoreidx_by_axiid(a, b) (0)
508 #define nci_wrapper_dump_binary(a, b) (0)
509 #define nci_wrapper_dump_last_timeout(a, b, c, d, e) (0)
511 #define nci_wrapper_dump_buf_size(a) (0)