1*4882a593SmuzhiyunMediatek IPU controller 2*4882a593Smuzhiyun============================ 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunThe Mediatek ipu controller provides various clocks to the system. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunRequired Properties: 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun- compatible: Should be one of: 9*4882a593Smuzhiyun - "mediatek,mt8183-ipu_conn", "syscon" 10*4882a593Smuzhiyun - "mediatek,mt8183-ipu_adl", "syscon" 11*4882a593Smuzhiyun - "mediatek,mt8183-ipu_core0", "syscon" 12*4882a593Smuzhiyun - "mediatek,mt8183-ipu_core1", "syscon" 13*4882a593Smuzhiyun- #clock-cells: Must be 1 14*4882a593Smuzhiyun 15*4882a593SmuzhiyunThe ipu controller uses the common clk binding from 16*4882a593SmuzhiyunDocumentation/devicetree/bindings/clock/clock-bindings.txt 17*4882a593SmuzhiyunThe available clocks are defined in dt-bindings/clock/mt*-clk.h. 18*4882a593Smuzhiyun 19*4882a593SmuzhiyunExample: 20*4882a593Smuzhiyun 21*4882a593Smuzhiyunipu_conn: syscon@19000000 { 22*4882a593Smuzhiyun compatible = "mediatek,mt8183-ipu_conn", "syscon"; 23*4882a593Smuzhiyun reg = <0 0x19000000 0 0x1000>; 24*4882a593Smuzhiyun #clock-cells = <1>; 25*4882a593Smuzhiyun}; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyunipu_adl: syscon@19010000 { 28*4882a593Smuzhiyun compatible = "mediatek,mt8183-ipu_adl", "syscon"; 29*4882a593Smuzhiyun reg = <0 0x19010000 0 0x1000>; 30*4882a593Smuzhiyun #clock-cells = <1>; 31*4882a593Smuzhiyun}; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyunipu_core0: syscon@19180000 { 34*4882a593Smuzhiyun compatible = "mediatek,mt8183-ipu_core0", "syscon"; 35*4882a593Smuzhiyun reg = <0 0x19180000 0 0x1000>; 36*4882a593Smuzhiyun #clock-cells = <1>; 37*4882a593Smuzhiyun}; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyunipu_core1: syscon@19280000 { 40*4882a593Smuzhiyun compatible = "mediatek,mt8183-ipu_core1", "syscon"; 41*4882a593Smuzhiyun reg = <0 0x19280000 0 0x1000>; 42*4882a593Smuzhiyun #clock-cells = <1>; 43*4882a593Smuzhiyun}; 44