1*4882a593SmuzhiyunMediatek vencltsys controller 2*4882a593Smuzhiyun============================ 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunThe Mediatek vencltsys controller provides various clocks to the system. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunRequired Properties: 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun- compatible: Should be: 9*4882a593Smuzhiyun - "mediatek,mt8173-vencltsys", "syscon" 10*4882a593Smuzhiyun- #clock-cells: Must be 1 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunThe vencltsys controller uses the common clk binding from 13*4882a593SmuzhiyunDocumentation/devicetree/bindings/clock/clock-bindings.txt 14*4882a593SmuzhiyunThe available clocks are defined in dt-bindings/clock/mt*-clk.h. 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunExample: 17*4882a593Smuzhiyun 18*4882a593Smuzhiyunvencltsys: clock-controller@19000000 { 19*4882a593Smuzhiyun compatible = "mediatek,mt8173-vencltsys", "syscon"; 20*4882a593Smuzhiyun reg = <0 0x19000000 0 0x1000>; 21*4882a593Smuzhiyun #clock-cells = <1>; 22*4882a593Smuzhiyun}; 23