1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/memory-controllers/ingenic,nemc.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Ingenic SoCs NAND / External Memory Controller (NEMC) devicetree bindings 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Paul Cercueil <paul@crapouillou.net> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyunproperties: 13*4882a593Smuzhiyun $nodename: 14*4882a593Smuzhiyun pattern: "^memory-controller@[0-9a-f]+$" 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun compatible: 17*4882a593Smuzhiyun oneOf: 18*4882a593Smuzhiyun - enum: 19*4882a593Smuzhiyun - ingenic,jz4740-nemc 20*4882a593Smuzhiyun - ingenic,jz4780-nemc 21*4882a593Smuzhiyun - items: 22*4882a593Smuzhiyun - const: ingenic,jz4725b-nemc 23*4882a593Smuzhiyun - const: ingenic,jz4740-nemc 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun "#address-cells": 26*4882a593Smuzhiyun const: 2 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun "#size-cells": 29*4882a593Smuzhiyun const: 1 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun ranges: true 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun reg: 34*4882a593Smuzhiyun maxItems: 1 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun clocks: 37*4882a593Smuzhiyun maxItems: 1 38*4882a593Smuzhiyun 39*4882a593SmuzhiyunpatternProperties: 40*4882a593Smuzhiyun ".*@[0-9]+$": 41*4882a593Smuzhiyun type: object 42*4882a593Smuzhiyun properties: 43*4882a593Smuzhiyun reg: 44*4882a593Smuzhiyun minItems: 1 45*4882a593Smuzhiyun maxItems: 255 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun ingenic,nemc-bus-width: 48*4882a593Smuzhiyun $ref: /schemas/types.yaml#/definitions/uint32 49*4882a593Smuzhiyun enum: [8, 16] 50*4882a593Smuzhiyun description: Specifies the bus width in bits. 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun ingenic,nemc-tAS: 53*4882a593Smuzhiyun $ref: /schemas/types.yaml#/definitions/uint32 54*4882a593Smuzhiyun description: Address setup time in nanoseconds. 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun ingenic,nemc-tAH: 57*4882a593Smuzhiyun $ref: /schemas/types.yaml#/definitions/uint32 58*4882a593Smuzhiyun description: Address hold time in nanoseconds. 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun ingenic,nemc-tBP: 61*4882a593Smuzhiyun $ref: /schemas/types.yaml#/definitions/uint32 62*4882a593Smuzhiyun description: Burst pitch time in nanoseconds. 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun ingenic,nemc-tAW: 65*4882a593Smuzhiyun $ref: /schemas/types.yaml#/definitions/uint32 66*4882a593Smuzhiyun description: Address wait time in nanoseconds. 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun ingenic,nemc-tSTRV: 69*4882a593Smuzhiyun $ref: /schemas/types.yaml#/definitions/uint32 70*4882a593Smuzhiyun description: Static memory recovery time in nanoseconds. 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun required: 73*4882a593Smuzhiyun - reg 74*4882a593Smuzhiyun 75*4882a593Smuzhiyunrequired: 76*4882a593Smuzhiyun - compatible 77*4882a593Smuzhiyun - "#address-cells" 78*4882a593Smuzhiyun - "#size-cells" 79*4882a593Smuzhiyun - ranges 80*4882a593Smuzhiyun - reg 81*4882a593Smuzhiyun - clocks 82*4882a593Smuzhiyun 83*4882a593SmuzhiyunadditionalProperties: false 84*4882a593Smuzhiyun 85*4882a593Smuzhiyunexamples: 86*4882a593Smuzhiyun - | 87*4882a593Smuzhiyun #include <dt-bindings/clock/jz4780-cgu.h> 88*4882a593Smuzhiyun #include <dt-bindings/gpio/gpio.h> 89*4882a593Smuzhiyun nemc: memory-controller@13410000 { 90*4882a593Smuzhiyun compatible = "ingenic,jz4780-nemc"; 91*4882a593Smuzhiyun reg = <0x13410000 0x10000>; 92*4882a593Smuzhiyun #address-cells = <2>; 93*4882a593Smuzhiyun #size-cells = <1>; 94*4882a593Smuzhiyun ranges = <1 0 0x1b000000 0x1000000>, 95*4882a593Smuzhiyun <2 0 0x1a000000 0x1000000>, 96*4882a593Smuzhiyun <3 0 0x19000000 0x1000000>, 97*4882a593Smuzhiyun <4 0 0x18000000 0x1000000>, 98*4882a593Smuzhiyun <5 0 0x17000000 0x1000000>, 99*4882a593Smuzhiyun <6 0 0x16000000 0x1000000>; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun clocks = <&cgu JZ4780_CLK_NEMC>; 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun ethernet@6 { 104*4882a593Smuzhiyun compatible = "davicom,dm9000"; 105*4882a593Smuzhiyun davicom,no-eeprom; 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun pinctrl-names = "default"; 108*4882a593Smuzhiyun pinctrl-0 = <&pins_nemc_cs6>; 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun reg = <6 0 1>, /* addr */ 111*4882a593Smuzhiyun <6 2 1>; /* data */ 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun ingenic,nemc-tAS = <15>; 114*4882a593Smuzhiyun ingenic,nemc-tAH = <10>; 115*4882a593Smuzhiyun ingenic,nemc-tBP = <20>; 116*4882a593Smuzhiyun ingenic,nemc-tAW = <50>; 117*4882a593Smuzhiyun ingenic,nemc-tSTRV = <100>; 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun reset-gpios = <&gpf 12 GPIO_ACTIVE_HIGH>; 120*4882a593Smuzhiyun vcc-supply = <ð0_power>; 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun interrupt-parent = <&gpe>; 123*4882a593Smuzhiyun interrupts = <19 4>; 124*4882a593Smuzhiyun }; 125*4882a593Smuzhiyun }; 126